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PowerPC 603e RISC Microprocessor Family PID7t-603e Specification TSPC603R

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Screening / Quality / Packaging
PowerPC 603e RISC Microprocessor Family PID7t-603e Specification TSPC603R
Description
The PID7t-603e implementation of PowerPC603e (after named 603r) is a low-power implementation of reduced instruction set computer (RISC) microprocessors PowerPC family. The 603r implements 32-bit effective addresses, integer data types of 8, 16 and 32 bits, and floating-point data types of 32 and 64 bits. The 603r is a low-power 2.5 / 3.3-volt design and provides four software controllable power-saving modes. The 603r is a superscalar processor capable of issuing and retiring as many as three instructions per clock. Instructions can execute out of order for increased performance however, the 603r makes completion appear sequential. The 603r integrates five execution units and is able to execute five instructions in parallel. The 603r provides independent on-chip, 16K byte, four-way set-associative, physically addressed caches for instructions and data and on-chip instruction and data memory management units (MMUs). The MMUs contain 64-entry, two-way set-associative, data and instruction translation look aside buffers that provide support for demand-paged virtual memory address translation and variable-sized block translation. The 603r has a selectable 32 or 64-bit data bus and a 32-bit address bus. The 603r interface protocol allows multiple masters to complete for system resources through a central external arbiter. The 603r supports single-beat and burst data transfers for memory accesses, and supports memory-mapped I / O.
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The 603r uses an advanced, 2.5 / 3.3V CMOS process technology and maintains full interface compatibility with TTL devices. The 603r integrates in system testability and debugging features through JTAG boundary-scan capability.
G suffix CBGA 255 Ceramic Ball Grid Array GS suffix CI-CGA 255 Ceramic Ball Grid Array with Solder Column Interposer (SCI)
General Description
Figure 1. Block Diagram
Fetch Unit Completion Unit Dispatch Unit Branch Unit
Integer Unit
Gen Reg Unit
Gen Rename
Load / Store Unit
FP Rename
FP Reg File
Float Unit
D MMU 16K Data Cache
I MMU 16K Inst. Cache
Bus Interface Unit 32b address 64b data
System Bus
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Introduction
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Pin Assignments
CBGA 255 and CI-CGA 255 Packages Figure 2 (pin matrix) shows the pinout as viewed from the top of the CBGA and CI-CGA packages. The direction of the top surface view is shown by the side profile of the packages.
Figure 2. CBGA 255 and CI-CGA 255 Top View
Substrate Assembly
CBGA 255
Encapsulant
Not to scale
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Pinout Listing Table 1. Power and Ground Pins
VDD2 PLL (AVDD) Internal Logic Output Drivers A10 F06, F08, F09, F11, G07, G10, H06, H08, H09, H11, J06, J08, J09, J11, K07, K10, L06, L08, L09, L11 C07, E05, E07, E10, E12, G03, G05, G12, G14, K03, K05, K12, K14, M05, M07, M10, M12, P07, P10 C05, C12, E03, E06, E08, E09, E11, E14, F05, F07, F10, F12, G06, G08, G09, G11, H05, H07, H10, H12, J05, J07, J10, J12, K06, K08, K09, K11, L05, L07, L10, L12, M03, M06, M08, M09, M11, M14, P05, P12 GND
Table 2. Signal Pinout Listing
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Table 2. Signal Pinout Listing
CBGA Pin Number D11 D12 B10 C13 A08, B09, A09, D09 D03 J03 D01 A16 B14 C09 H14 C02 A14 A02, A03 C11 A11 A12 H13 C04 B11 C10 J13 A13, D10, B12 B13, A15, B16, C14, C15 D02 B07, B08, C03, C06, C08, D05, D06, F03, H04, J16
Active Low Low High Low Low Low Low Low Low High Low High High High Low Low High Low Low High High Low Low
I / O Input Input Input Input Input Input Output Output Input Input Input Input Input I / O Output Input Input Output Input Input Input Input I / O I / O I / O Output Input
VOLTDETGND(3) F03 Low Output Notes: 1. These are test signals for factory use only and must be pulled up to OVDD for normal machine operation. 2. OVDD inputs supply power to the I / O drivers and VDD inputs supply power to the processor core. 3. NC (no-connect) in the 603e BGA package internally tied to GND in the 603r BGA package to indicate to the power supply that a low-voltage processor is present.
Signal Description
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Figure 3. Functional Signal Groups
BR ADDRESS ARBITRATION BG ABB TS A0-31 ADDRESS BUS AP0-3 APE TT0-4 TBST TSIZ0-2 GBL TRANSFER ATTRIBUTE CI WT CSE0-1 TC0-1 1 1 1 1 1 1 DBG DBWO DBB DATA ATTRIBUTION
ADDRESS START
PROCESSOR STATUS
JTAG / COP INTERFACE LSSD TEST CONTROL
POWER SUPPLY
Table 3. Address and data bus signal index
Signal Name Address Bus Data Bus Data Bus Mnemonic A0-31 DH0-31 DL0-31 Signal function if output, physical address of data to be transferred. if input, represents the physical address of a snoop operation. Represents the state of data, during a data write operation if output, or during a data read operation if input. Represents the state of data, during a data write operation if output, or during a data read operation if input. Signal type I / O I / O I / O
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Table 4. Signal index
Signal Name Address Acknowledge Address Bus Busy Mnemonic AACK ABB Signal function The address phase of a transaction is complete If output, the 603r is the address bus master If input, the address bus is in use If output, represents odd parity for each of 4 bytes of the physical address for a transaction If input, represents odd parity for each of 4 bytes of the physical address for snooping operations Incorrect address bus parity detected on a snoop If output, detects a condition in which a snooped address tenure must be retried If input, must retry the preceding address tenure May, with the proper qualification, assume mastership of the address bus Request mastership of the address bus A single-beat transfer will not be cached Provides PLL clock output for PLL testing and monitoring Must terminate operation by internally gating off all clocks, and release all outputs Has detected a checkstop condition and has ceased operation Cache replacement set element for the current transaction reloading into or writing out of the cache If output, the 603r is the data bus master If input, another device is bus master (For a write transaction) must release data bus and the data bus parity to high impedance during the following cycle May, with the proper qualification, assume mastership of the data bus May run the data bus tenure If output, odd parity for each of 8 bytes of data write transactions If input, odd parity for each byte of read data Incorrect data bus parity Must invalidate the data from the previous read operation If output, a transaction is global If input, a transaction must be snooped by the 603r Initiates a complete hard reset operation Initiates an interrupt if bit EE of MSR register is set LSSD test control signal for factory use only LSSD test control signal for factory use only LSSD test control signal for factory use only Signal type Input I / O
Address Bus Parity
AP0-3
Address Parity Error Address Retry Bus Grant Bus Request Cache Inhibit Test Clock Checkstop Input Checkstop Output Cache Set Entry Data Bus Busy Data Bus Disable Data Bus Grant Data Bus Write Only Data Bus Parity Data Parity Error Data Retry Global Hard Reset Interrupt
Output I / O Input Output Output Output Input Output Output I / O Input Input Input I / O Output Input I / O Input Input Input Input Input
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Table 4. Signal index
Transfer start
Transfer Type Write-Through Power supply indicator
TT0-4 WT VOLTDETGND
I / O Output Output
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Detailed Specifications
Scope Applicable Documents Requirements
General Design and construction The microcircuits are in accordance with the applicable documents and as specified herein. · Terminal connections The terminal connections shall be as shown in Figure 15 and Figure 3. · Lead material and finish Lead material and finish shall be as specified in MIL-STD-1835. Absolute Maximum Ratings Absolute maximum ratings are stress rating only and functional operation at the maximum is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. This drawing describes the specific requirements for the microprocessor TSPC603r, in compliance with MIL-STD-883 class B or ATMEL-Grenoble standard screening. 1. MIL-STD-883: Test methods and procedures for electronics. 2. MIL-PRF-38535: General specifications for microcircuits.
Table 5. Absolute Maximum Rating for the 603r
Parameter Core Supply Voltage PLL Supply Voltage I / O Supply Voltage Input Voltage Storage Temperature Range Notes: Symbol Vdd AVdd OVdd Vin Tstg Min -0.3 -0.3 -0.3 -0.3 -55 Max 2.75 2.75 3.6 5.5 +150 Unit V V V V °C
1. Functional operating conditions are given in AC and DC electrical specifications. Stresses beyond the absolute maximums listed may affect device reliability or cause permanent damage to the device. 2. Caution: Input voltage must not be greater than OVdd by more than 2.5V at any times, including during power-on reset. 3. Caution: OVdd voltage must not be greater than Vdd / AVdd by more than 1.2V at any times, including during power-on reset. 4. Caution: Vdd / AVdd voltage must not be greater than OVdd by more than 0.4V at any times, including during power-on reset.
Recommended Operating Conditions
Parameter Core Supply Voltage PLL Supply Voltage I / O Supply Voltage Input Voltage Operating Temperature
These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed.
Symbol Vdd AVdd OVdd Vin Tc Min 2.375 2.375 3.135 GND -55 Max 2.625 2.625 3.465 5.5 +125 Unit V V V V °C
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Figure 4. CBGA Thermal Management Example
Rsa (°C / W) Heat Sink Thermal Resistance 7 6 5 4 3 2 1 0 0 1 2 Approach air velocity (m / sec) 3
Assuming an air velocity of 1.0 m / sec, the associated overall thermal resistance and junction temperature, found in Table 6 will result. Table 6. Thermal Resistance and Junction Temperature
Configuration With 2328B heat sink Rja (°C / W) 5.0 Tj (°C) 106
Vendors such as Aavid Engineering Inc., Thermalloy, and Wakefield Engineering can supply heat sinks with a wide range of thermal performance. Power Consideration The PowerPC603r is a microprocessor specifically designed for low-power operation. As the 603e microprocessor version, the 603r provides both automatic and program-controllable power reduction modes for progressive reduction of power consumption. This chapter describes the hardware support provided by the 603r for power management. · Dynamic Power Management Dynamic power management automatically powers up and down the individual execution units of the 603r, based upon the contents of the instruction stream. For example, if no floating-point instructions are being executed, the floating-point unit is automatically powered down. Power is not actually removed from the execution unit instead, each execution unit has an independent clock input, which is automatically controlled on a clock-by-clock basis. Since CMOS circuits consume negligible power when they are not switching, stopping the clock to an execution unit effectively eliminates its power consumption. The operation of DPM is completely transparent to software or any external hardware. Dynamic power management is enabled by setting bit 11 in HID0 on power-up, of following HRESET. · Programmable Power Modes The 603r provides four programmable power states-full power, doze, nap and sleep. Software selects these modes by setting one (and only one) of the three power saving mode bits. Hardware can enable a power management state through external asynchronous interrupts The hardware interrupt causes the transfer of program flow to interrupt handler code. The appropriate mode is then set by the software. The 603r provides a separate interrupt and interrupt vector for power management-the system management interrupt (SMI). The 603r also contains a decrement timer which allows it to enter the nap or doze mode for a predetermined amount of time and then return to full power operation through the decrementer interrupt (DI).
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Note that the 603r cannot switch from on power management mode to another without first returning to full on mode. The nap and sleep modes disable bus snooping therefore, a hardware handshake is provided to ensure coherency before the 603r enters these power management modes. Table 7 summarizes the four power states. Table 7. Power PC 603r Microprocessor Programmable Power Modes
PM Mode Full Power Full Power (with DPM) Doze Functioning Units All units active Requested logic by demand - Bus snooping - Data cache as needed - Decrementer timer Decrementer timer Activation Method - By instruction dispatch Controlled by SW Full-Power Wake Up Method - - External asynchronous exceptions(1) Decrementer interrupt Reset External asynchronous exceptions Decrementer interrupt Reset External asynchronous exceptions Reset
Controlled by hardware and software Controlled by hardware and software
Sleep Note:
1. Exceptions are referred to as interrupts in the architecture specification
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Transition to full-power state takes no more than a few processor cycles. PLL running and locked to SYSCLK.
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Return to full-power mode after PLL and SYSCLK disabled in sleep mode: - Enable SYSCLK. - Reconfigure PLL into desired processor clock mode. - System logic waits for PLL startup and relock time (100 µsec). - System logic asserts one of the sleep recovery signals (for example, INT or SMI).
166 MHz Full-On Mode (DPM Enabled) Typical Max Doze Mode Typical Nap Mode Typical Sleep Mode Typical 96 110 123 135 150 mW 100 120 140 160 180 mW 1.5 1.7 1.8 2.0 2.1 W 2.1 3.2 2.5 4.0 3.0 4.6 3.5 5.3 4.0 6.0 W W 200 MHz 233 MHz 266 MHz 300 MHz Units
Sleep Mode-PLL Disabled Typical 60 60 60 60 60 mW
Sleep Mode-PLL and SYSCLK Disabled Typical Maximum Notes: 25 60 25 60 25 60 25 80 25 100 mW mW
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Marking
Electrical Characteristics
General Requirements All static and dynamic electrical characteristics specified for inspection purposes and the relevant measurement conditions are given below: · · Table 9: Static electrical characteristics for the electrical variants. Table 10: Dynamic electrical characteristics for the 603r.
Min 2.0 GND 2.4 GND 2.4 -
Max 5.5 0.8 5.5 0.4 30 300 30 300 0.4 10.0 15.0
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Dynamic Characteristics · Clock AC Specifications Table 10 provides the clock AC timing specifications as defined in Figure 5.
Figure 5. SYSCLK Input Timing Diagram
· Input AC specifications
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166, 200 MHz Num 10a 10b 10c 11a 11b 11c Notes: Characteristics Address / data / transfer attribute inputs valid to SYSCLK (input setup) All other inputs valid to SYSCLK (input setup) Mode select inputs valid to HRESET (input setup) (for DRTRY, QACK and TLBISYNC) SYSCLK to address / data / transfer attribute inputs invalid (input hold) SYSCLK to all other inputs invalid (input hold) HRESET to mode select inputs invalid (input hold) (for DRTRY, QACK, and TLBISYNC) Min 2.5 4.0 8 1.0 1.0 0 Max 233, 266 MHz Min 2.5 3.5 8 1.0 1.0 0 Max 300 MHz Min 2.5 3.5 8 1.0 1.0 0 Max Unit ns ns tsysclk ns ns ns Note 2 3 4, 5, 6, 7 2 3 4, 6, 7
1. All input specifications are measured from the TTL level (0.8 or 2.0V) of the signal in question to the 1.4V of the rising edge of the input SYSCLK. Both input and output timings are measured at the pin. See Figure 7. 2. Address / data / transfer attribute input signals are composed of the following: A0-31, AP0-3, TT0-4, TC0-1, TBST, TSIZ0-2, GBL, DH0-31, DL0-31, DP9-7. 3. All other input signals are composed of the following: TS, ABB, DBB, ARTRY, BG, AACK, DBG, DBWO, TA, DRTRY, TEA, DBDIS, HRESET, SRESET, INT, SMI, MCP, TBEN, QACK, TLBISYNC. 4. The setup and hold time is with respect to the rising edge of HRESET. See Figure 7. 5. tsysclk is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question. 6. These values are guaranteed by design, and are not tested. 7. This specification is for configuration mode only. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL relock time (100 µs) during the power-on reset sequence.
Figure 6. Input Timing Diagram
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Figure 7. Mode Select Input Timing Diagram
166, 200 MHz Num 12 13a 13b 14a 14b 15 16 17 18 19 20 21 Notes: Characteristic SYSCLK to output driven (output enable time) SYSCLK to output valid (5.5V to 0.8V-TS, ABB, ARTRY, DBB) SYSCLK to output valid (TS, ABB, ARTRY, DBB) SYSCLK to output valid (5.5V to 0.8V-all except TS, ABB, ARTRY, DBB) SYSCLK to output valid (all except TS, ABB, ARTRY, DBB) SYSCLK to output invalid (output hold) SYSCLK to output high impedance (all except ARTRY, ABB, DBB) SYSCLK to ABB, DBB, high impedance after precharge SYSCLK to ARTRY high impedance before precharge SYSCLK to ARTRY precharge enable Maximum delay to ARTRY precharge SYSCLK to ARTRY high impedance after precharge Min 1.0 1.0 0.2 tsysclk + 1.0 Max 9.0 8.0 11.0 9.0 8.5 1.0 8.0 1.0 2.0 233, 266 MHz Min 1.0 1.0 0.2 tsysclk + 1.0 Max 9.0 8.0 11.0 9.0 8.0 1.0 7.5 1.0 2.0 300 MHz Min 1.0 1.0 0.2 tsysclk + 1.0 Max 9.0 8.0 11.0 9.0 8.0 1.0 7.5 1.0 2.0 Unit ns ns ns ns ns ns ns tsysclk ns ns tsysclk tsysclk 3, 5, 8 5, 8 6, 8 5, 7 4 6 4 6 3 Note
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5. tsysclk is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question. 6. Output signal transitions from GND to 2.0V or Vdd to 0.8V. 7. Nominal precharge width for ABB and DBB is 0.5 tsysclk. 8. Nominal precharge width for ARTRY is 1.0 tsysclk.
Figure 8. Output Timing Diagram
Num Characteristic TCK frequency of operation 1 2 3 4 5 6 7 8 9 TCK cycle time TCK clock pulse width measured at 1.4V TCK rise and fall times TRST setup time to TCK rising edge TRST assert time Boundary scan input data setup time Boundary scan input data hold time TCK to output data valid TCK to output high impedance Min 0 62.5 25 0 13 40 6 27 4 3 Max 16 - - 3 - - - - 25 24 Unit MHz ns ns ns ns ns ns ns ns ns 2 2 3 3 1 Notes
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Num 10 11 12 13 Notes: 1. 2. 3. Characteristic TMS, TDI data setup time TMS, TDI data hold time TCK to TDO data valid Min 0 25 4 Max - - 24 15 Unit ns ns ns ns Notes
TCK to TDO high impedance 3 TRST is an asynchronous signal. The setup time is for test purposes only. Non-test signal input timing with respect to TCK. Non-test signal output timing with respect to TCK.
Figure 9. Clock Input Timing Diagram
Figure 10. TRST Timing Diagram
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Figure 11. Boundary-scan Timing Diagram
Figure 12. Test Access Port Timing Diagram
Functional Description
PowerPC Registers and Programming Model The PowerPC architecture defines register-to-register operations for most computational instructions. Source operands for these instructions are accessed from the registers or are provided as immediate values embedded in the instruction opcode. The three-register instruction format allows specification of a target register distinct from the two source operands. Load and store instructions transfer data between registers and memory. PowerPC processors have two levels of privilege - supervisor mode of operation (typically used by the operating system) and user mode of operation (used by the application software). The programming models incorporate 32 GPRs, 32 FPRs, special-purpose registers (SPRs) and several miscellaneous registers. Each PowerPC microprocessor also has its own unique set of hardware implementation (HID) registers.
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(mfspr) instructions) or implicit, as the part of the execution of an instruction. Some registers are accessed both explicitly and implicitly. Il the 603r, all SPRs are 32 bits wide. USER-LEVEL SPRs: The following 603r SPRs are accessible by user-level software: · Link register (LR) - The link register can be used to provide the branch target address and to hold the return address after branch and link instructions. The LR is 32 bits wide in 32-bit implementations. Count register (CTR) - The CRT is decremented and tested automatically as a result of branch-and-count instructions. The CTR is 32 bits wide in 32-bit implementations. Integer exception register (XER) - The 32-bit XER contains the summary overflow bit, integer carry bit, overflow bit, and a field specifying the number of bytes to be transferred by a Load String Word Indexed (lswx) or Store String Word Indexed (stswx) instruction.
SUPERVISOR-LEVEL SPRs: The 603r also contains SPRs that can be accessed only by supervisor-level software. These registers consist of the following: · · · · The 32-bit DSISR defines the cause of data access and alignment exceptions. The data address register (DAR) is a 32-bit register that holds the address of an access after an alignment or DSI exception. Decrementer register (DEC) is a 32-bit decrementing counter that provides a mechanism for causing a decrementer exception after a programmable delay. The 32-bit SDR1 specifies the page table format used in virtual-to-physical address translation for pages. (Note that physical address is referred to as real address in the architecture specification). The machine status save / restore register 0 (SRR0) is a 32-bit register that is used by the 603r for saving the address of the instruction that caused the exception, and the address to return to when a Return from Interrupt (rfi) instruction is executed. The machine status save / restore register 1 (SRR1) is a 32-bit register used to save machine status on exceptions and to restore machine status when an rfi instruction is executed. The 32-bit SPRG0-SPRG3 registers are provided for operating system use. The external access register (EAR) is a 32-bit register that controls access to the external control facility through the External Control In Word Indexed (eciwx) and External Control Out Word Indexed (ecowx) instructions. The time base register (TB) is a 64-bit register that maintains the time of day and operates interval timers. The TB consists of two 32-bit fields - time base upper (TBU) and time base lower (TBL). The processor version register (PVR) is a 32-bit, read-only register that identifies the version (model) and revision level of the PowerPC processor. Block address translation (BAT) arrays - The PowerPC architecture defines 16 BAT registers, divided into four pairs of data BATs (DBATs) and four pairs of instruction BATs (IBATs). See Figure 13 for a list of the SPR numbers for the BAT arrays. The following supervisor-level SPRs are implementation-specific to the 603r: The DMISS and IMISS registers are read-only registers that are loaded automatically upon an instruction or data TLB miss. The HASH1 and HASH2 registers contain the physical addresses of the primary and secondary page table entry groups (PTEGs). The ICMP and DCMP registers contain a duplicate of the first word in the page table entry (PTE) for which the table search is looking.
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Figure 13 shows all the 603r registers available at the user and supervisor level. The number to the right of the SPRs indicate the number that is used in the syntax of the instruction operands to access the register.
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Figure 13. PowerPC Microprocessor Programming Model - Register
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Instruction Set and Addressing Modes The following subsections describe the PowerPC instruction set and addressing modes in general. · PowerPC Instruction Set and Addressing Modes All PowerPC instructions are encoded as single-word (32-bit) opcodes. Instruction formats are consistent among all instruction types, permitting efficient decoding to occur in parallel with operand accesses. This fixed instruction length and consistent format greatly simplifies instruction pipelining. PowerPC INSTRUCTION SET: The PowerPC instructions are divided into the following categories: · Integer instructions - These include computational and logical instructions. - Integer arithmetic instructions. - Integer compare instructions. - Integer logical instructions. - Integer rotate and shift instructions. Floating-point instructions -These include floating-point computational instructions, as well as instructions that affect the FPSCR. - Floating-point arithmetic instructions. - Floating-point multiply / add instructions. - Floating-point rounding and conversion instructions. - Floating-point compare instructions. - Floating-point status and control instructions. Load / store instructions - These include integer and floating-point load and store instructions. - Integer load and store instruction. - Integer load and store multiple instructions. - Floating-point load and store. - Primitives used to construct atomic memory operations (lwarx and stwcx. instructions). Flow control instructions - These include branching instructions, condition register logical instructions, trap instructions, and other instructions that affect the instruction flow. - Branch and trap instructions. - Condition register logical instructions. Processor control instructions - These instructions are used for synchronizing memory accesses and management of caches, TLBs, and the segment registers. - Move to / from SPR instructions. - Move to / from MSR. - Synchronize. - Instruction synchronize. Memory control instruction - These instructions provide control of caches, TLBs, and segment registers. - Supervisor-level cache management instructions. - User-level cache instructions. - Segment register manipulation instructions. - Translation look aside buffer management instructions.
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These simple addressing modes allow efficient address generation for memory accesses. Calculation of the effective address for aligned transfers occurs in a single clock cycle. For a memory access instruction, if the sum of the effective address and the operand length exceeds the maximum effective address, the memory operand is considered to wrap around from the maximum effective address to effective address 0. Effective address computations for both data and instruction accesses use 32-bit unsigned binary arithmetic. A carry from bit 0 is ignored in 32-bit implementations. · PowerPC 603r Microprocessor Instruction Set The 603r instruction set is defined as follows: · · The 603r provides hardware support for all 32-bit PowerPC instructions. The 603r provides two implementation-specific instructions used for software table search operations following TLB misses: - Load Data TLB Entry (tlbld). - Load Instruction TLB Entry (tlbli). The 603r implements the following instructions which are defined as optional by the PowerPC architecture : - External Control In Word Indexed (eciwx). - External Control Out Word Indexed (ecowx). - Floating Select (fsed). - Floating Reciprocal Estimate Single-Precision (fres). - Floating Reciprocal Square Root Estimate (frsqrte). - Store Floating-Point as Integer Word (stfiwx).
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Exception Model
The following subsections describe the PowerPC exception model and the 603r implementation, respectively. · PowerPC Exception Model The PowerPC exception mechanism allows the processor to change to supervisor state as a result of external singles, errors, or unusual conditions arising in the execution of instructions, and differ from the arithmetic exceptions defined by the IEEE for floating-point operations. When exceptions occur, information about the state of the processor is saved to certain registers and the processor begins execution at an address (exception vector) predetermined for each exception. Processing of exceptions occurs in supervisor mode. Although multiple exception conditions can map to a single exception vector, a more specific condition may be determined by examining a register associated with the exception - for example, the DSISR and the FPSCR. Additionally, some exception conditions can be explicitly enable or disabled by software. The PowerPC architecture requires that exceptions be handled in program order therefore, although a particular implementation may recognize exception conditions out of order, they are presented strictly in order. When an instruction-caused exception is recognized, any unexecuted instructions that appear earlier in the instruction stream, including any that have not yet entered the execute state, are required to complete before the exception is taken. Any exceptions caused by those instructions are handled first. Likewise, exceptions that are asynchronous and precise are recognized when they occur, but are not handled until the instruction currently in the completion state successfully completes execution or generates an exception, and the completed store queue is emptied.
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Table 14. PowerPC 603r Microprocessor Exception Classifications
Synchronous / Asynchronous Asynchronous, Non Maskable Precise / Imprecise Imprecise Exception Type Machine check System reset External interrupt Decrementer System management interrupt Instruction-caused exceptions
Asynchronous, Maskable Synchronous
Precise Precise
External interrupt
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Table 15. Exceptions and Conditions (Continued)
Program
Floating-point unavailable Decrementer Reserved System call Trace Reserved Reserved Instruction translation miss Data load translation miss Data store translation miss
00900 00A00-00BFF 00C00 00D00 00E00 00E10-00FFF 01000 01100 01200
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Table 15. Exceptions and Conditions (Continued)
01500-02FFF
Memory Management
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A superscalar processor is one that issues multiple independent instructions into multiple pipelines allowing instructions to execute in parallel. The 603r has five independent execution units, one each for integer instructions, floating-point instructions, branch instructions, load / store instructions, and system register instructions. The IU and the FPU each have dedicated register files for maintaining operands (GPRs and FPRs, respectively), allowing integer calculations and floating-point calculations to occur simultaneously without interference. Because the PowerPC architecture can be applied to such a wide variety of implementations, instruction timing among various PowerPC processors varies accordingly.
Preparation for Delivery
Packaging Certificate of Compliance Microcircuits are prepared for delivery in accordance with MIL-PRF-38535. ATMEL-Grenoble offers a certificate of compliances with each shipment of parts, affirming the products are in compliance either with MIL-STD-883 and guarantying the parameters not tested at temperature extremes for the entire temperature range. MOS devices must be handled with certain precautions to avoid damage due to accumulation of static charge. Input protection devices have been designed in the chip to minimize the effect of this static buildup. However, the following handling practices are recommended: 1. Devices should be handled on benches with conductive and grounded surfaces. 2. Ground test equipment, tools and operator. 3. Do not handle devices by the leads. 4. Store devices in conductive foam or carriers. 5. Avoid use of plastic, rubber, or silk in MOS areas. 6. Maintain relative humidity above 50 percent if practical.
Handling
Packages Mechanical Data
CBGA Package Parameters
The following sections provide the package parameters and mechanical dimensions for the CBGA packages. The package parameters are as provided in the following list. The package type is 21 mm, 255-lead ceramic ball grid array (CBGA).
Package outline Interconnects Pitch Maximum module height
21 mm x 21 mm 255 1.27 mm 3.00 mm
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Mechanical dimensions of the CBGA package Figure 15 provides the mechanical dimensions and bottom surface nomenclature of the CBGA package.
Figure 15. Mechanical Dimensions and Bottom Surface Nomenclature of the CBGA Package
Notes: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Controlling dimension: millimeter
Millimeters Min Max 21.000 BSC 21.000 BSC 2.450 3.000 0.820 0.930 1.270 BSC 0.790 0.990 0.635 BSC 5.000 16.000 5.000 16.000
Inches Min Max 0.827 BSC 0.827 BSC 0.097 0.118 0.032 0.036 0.050 BSC 0.031 0.039 0.025 BSC 0.197 0.630 0.197 0.630
CI-CGA Package Parameters
The package parameters are as provided in the following list. The package type is 21 mm, 255-lead ceramic ball grid array (CI-CGA). Package outline Interconnects Pitch Typical module height 21 mm x 21 mm 255 1.27 mm 3.84 mm
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Mechanical Dimensions of the CICGA Package
Figure 16 provides the mechanical dimensions and bottom surface nomenclature of the CBGA package.
Figure 16. Mechanical Dimensions and Bottom Surface Nomenclature of the CI-CGA Package
Notes: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Controlling dimension: millimeter.
Millimeters Min Max 21.000 BSC 21.000 BSC 3.84 BSC 0.790 0.990 1.270 BSC 1.545 1.695 0.635 BSC 5.000 16.000 5.000 16.000 3.02 BSC 0.10 BSC 0.25 0.35
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Clock Relationships Choice
The 603r microprocessors offer customers numerous clocking options. An internal phase-lock loop synchronizes the processor (CPU) clock to the bus or system clock (SYSCLK) at various ratios. Inside each PowerPC microprocessor is a phase-lock loop circuit. A voltage controlled oscillator (VCO) is precisely controlled in frequency and phase by a frequency / phase detector which compares the input bus frequency (SYSCLK frequency) to a submultiple of the VCO. The ratio of CPU to SYSCLK frequencies is often referred to as the bus mode (for example, 2:1 bus mode). In the Table 16, the horizontal scale represents the bus frequency (SYSCLK) and the vertical scale represents the PLL-CFG0-3 signals. For a given SYSCLK (bus) frequency, the PLL configuration signals set the internal CPU and VCO frequency of operation. Table 16. CPU Frequencies for Common Bus Frequencies and Multipliers
CPU Frequency in MHZ (VCO Frequency in MHz) Bus-toCore Multiplier 2x 2x 2.5x 3x 3.5x 4x 4.5x 5x 5.5x 6x Core-to VCO Multiplier 2x 4x 2x 2x 2x 2x 2x 2x 2x 2x Bus 25 MHz 150 (300) Bus 33.33 MHz 150 (300) 166 (333) 183 (366) 200 (400) Bus 40 MHz 160 (320) 180 (360) 200 (400) 220 (440) 240 (480) PLL bypass Clock off Bus 50 MHz 150 (300) 175 (350) 200 (400) 225 (450) 250 (500) 275 (550) 300 (600) Bus 60 MHz 150 (300) 180 (360) 210 (420) 240 (480) 270 (540) 300 (600) Bus 66.67 MHz 166 (333) 200 (400) 233 (466) 267 (533) 300 (600) Bus 75 MHz 150 (300) 187 (375) 225 (450) 263 (525) 300 (600) -
1. Some PLL configurations may select bus, CPU or VCO frequencies which are not supported 2. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode is set for 1:1 mode operation. This mode is intended for factory use only. Note: the AC timing specifications given in this document do not apply in PLL-bypass mode. 3. In clock-off mode, no clocking occurs inside the 603e regardless of the SYSCLK input.
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System Design Information
PLL Power Supply Filtering The A Vdd power signal is provided on the 603e to provide power to the clock generation phase-locked loop. To ensure stability of the internal clock, the power supplied to the AVdd input signal should be filtered using a circuit similar to the one shown in Figure 17. The circuit should be placed as close to the AVdd pin to ensure it filters out as much noise as possible. The 0.1 µF capacitor should be closest to the AVdd pin, followed by the 10 µF capacitor, and finally the 10 resistor to Vdd. These traces should be kept short and direct. Figure 17. PLL Power Supply Filter Circuit
Vdd 10 10 µF AVdd 0.1 µF
Decoupling Recommendations
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to Vdd. Unused active high inputs should be connected to GND. ALL NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all external Vdd, OVdd, and GND pins of the 603e.
Pull-up Resistor Requirements
The 603e requires high-resistive (weak: 10 K) pull-up resistors on several control signals of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the 603e or other bus master. These signals are: TS, ABB, DBB, and ARTRY.
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Ordering Information
TS (X) PC603R M G B / Q 12 L (C) Revision level Bus divider (to be confirmed) L : Any bus @ 75 MHz
Prefix Prototype Type Temperature range : TC M : -55, +125°C V : -40, +1 10°C
Max internal processor speed 6 8 10 12 14 : : : : : 166 MHz 200 MHz 233 MHz 266 MHz 300 MHz
Package : G : GS : CBGA CI-CGA
Note:
Standard MIL-STD-883, class Q according to MIL-STD-883 Upscreening Upscreening + burn-in
For availability of the different versions, contact your ATMEL-Grenoble sales office.
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