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SPECint95, SPECfp95 (estimated) Superscalar instructions clock peak) Dual Caches Selectable Clock 32-bit Compatibility PowerPC Implementation Chip Debug Support typical Watts (266 MHz), Full Operating Conditions Nap, Doze Sleep Modes Power Savings Branch Folding 64-bit Data (32-bit Data Option) byte Direct Addressing Range Pipelined Single/double Precision Float Unit IEEE Compatible IEEE 1149-1 Test Mode (JTAG/C0P) fint fbus Compatible CMOS Input Output
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This product manufactured full compliance with: CI-CGA 255: MIL-STD-883 class According ATMEL-Grenoble standards CBGA 255: Upscreenings based upon ATMEL-Grenoble standards Full Military Temperature Range -55°C, +125°C) IndustriaL Temperature Range -40°C, +110°C) Internal Power Supply 3.3V CBGA Package CBGA with (CI-CGA) Package
PowerPC 603eRISC Microprocessor Family PID7t-603e Specification TSPC603R
Description
PID7t-603e implementation PowerPC603e (after named 603r) low-power implementation reduced instruction computer (RISC) microprocessors PowerPC family. 603r implements 32-bit effective addresses, integer data types bits, floating-point data types bits. 603r low-power 2.5/3.3-volt design provides four software controllable power-saving modes. 603r superscalar processor capable issuing retiring many three instructions clock. Instructions execute order increased performance; however, 603r makes completion appear sequential. 603r integrates five execution units able execute five instructions parallel. 603r provides independent on-chip, byte, four-way set-associative, physically addressed caches instructions data on-chip instruction data memory management units (MMUs). MMUs contain 64-entry, two-way set-associative, data instruction translation look aside buffers that provide support demand-paged virtual memory address translation variable-sized block translation. 603r selectable 64-bit data 32-bit address bus. 603r interface protocol allows multiple masters complete system resources through central external arbiter. 603r supports single-beat burst data transfers memory accesses, supports memory-mapped I/O.
Rev. 2125A-12/01
603r uses advanced, 2.5/3.3V CMOS process technology maintains full interface compatibility with devices. 603r integrates system testability debugging features through JTAG boundary-scan capability.
suffix CBGA Ceramic Ball Grid Array suffix CI-CGA Ceramic Ball Grid Array with Solder Column Interposer (SCI)
General Description
Figure Block Diagram
Fetch Unit Completion Unit Dispatch Unit Branch Unit
Integer Unit
Unit
Rename
Load/ Store Unit
Rename
File
Float Unit
Data Cache
Inst. Cache
Interface Unit address data
System
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Introduction
603r low-power implementation PowerPC microprocessor family reduced instruction computer (RISC) microprocessors. 603r implements 32-bit portion PowerPC architecture, which provides 32-bit effective addresses, integer data types bits, floating-point data types bits. 64-bit PowerPC microprocessors, PowerPC architecture provides 64-bit integer data types, 64-bit addressing, other features required complete 64-bit architecture. 603r provides four software controllable power-saving modes. Three modes (the nap, doze, sleep modes) static nature, progressively reduce amount power dissipated processor. fourth dynamic power management mode that causes functional units 603r automatically enter low-power mode when functional units idle without affecting operational performance, software execution, external hardware. 603r superscalar processor capable issuing retiring many three instructions clock. Instructions execute order increased performance; however, 603r makes completion appear sequential. 603e integrates five execution units-an integer unit (IU), floating-point unit (FPU), branch processing unit (BPU), load/store unit (LSU) system register unit (SRU). ability execute five instructions parallel simple instructions with rapid execution times yield high efficiency throughput 603r-based systems. Most integer instructions execute clock cycle. pipelined single-precision multiply-add instruction issued every clock cycle. 603r provides independent on-chip, byte, four-way set-associative, physically addressed caches instructions data on-chip instruction data memory management units (MMUs). MMUs contain 64-entry, two-way set-associative, data instruction translation look aside buffers (DTLB ITLB) that provide support demand-paged virtual memory address translation variable-sized block translation. TLBs caches least recently used (LRU) replacement algorithm. 603r also supports block address translation through independent instruction data block address translation (IBAT DBAT) arrays four entries each. Effective addresses compared simultaneously with four entries array during block translation. accordance with PowerPC architecture, effective address hits both array, translation takes priority. 603r selectable 64-bit data 32-bit address bus. 603r interface protocol allows multiple masters compete system resources through central external arbiter. 603r provides three-state coherency protocol that supports exclusive, modified, invalid cache states. This protocol compatible subset MESI four-state protocol operates coherently systems that contain four-state caches. 603r supports single-beat burst data transfers memory accesses, supports memory-mapped I/O. 603r uses advanced, 0.29 metal layer CMOS process technology maintains full interface compatibility with devices.
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Assignments
CBGA CI-CGA Packages Figure (pin matrix) shows pinout viewed from CBGA CI-CGA packages. direction surface view shown side profile packages.
Figure CBGA CI-CGA View
matrix view
Substrate Assembly
View
CBGA
Encapsulant
CI±CGA
scale
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Pinout Listing Table Power Ground Pins
VDD2 (AVDD) Internal Logic Output Drivers F06, F08, F09, F11, G07, G10, H06, H08, H09, H11, J06, J08, J09, J11, K07, K10, L06, L08, L09, C07, E05, E07, E10, E12, G03, G05, G12, G14, K03, K05, K12, K14, M05, M07, M10, M12, P07, C05, C12, E03, E06, E08, E09, E11, E14, F05, F07, F10, F12, G06, G08, G09, G11, H05, H07, H10, H12, J05, J07, J10, J12, K06, K08, K09, K11, L05, L07, L10, L12, M03, M06, M08, M09, M11, M14, P05,
Table Signal Pinout Listing
Signal Name A[0-31] AACK AP[0-3] ARTRY CKSTP_IN CKSTP_OUT CLK_OUT CSE[0-1] DBDIS DBWO DH[0-31] DL[0-31] DP[0-7] DRTRY HRESET CBGA Number C16, E04, D13, F02, D14, G01, D15, E02, D16, D04, E13, G02, E15, H01, E16, H02, F13, J01, F14, J02, F15, H03, F16, F04, G13, K01, G15, K02, H16, M01, J15, C01, B04, B03, B01, P14, T16, R15, T15, R13, R12, P11, N11, R11, T12, T11, R10, P09, N09, T10, R09, T09, P08, N08, R08, T08, N07, R07, T07, P06, N06, R06, T06, R05, N05, T05, K13, K15, K16, L16, L15, L13, L14, M16, M15, M13, N16, N15, N13, N14, P16, P15, R16, R14, T14, N10, P13, N12, T13, P03, N03, N04, R03, T01, T02, P04, T03, M02, L03, N02, L04, R01, P02, M04, Active High High High High High High Input Output Input Output Output Input Output Output Output Input Input Input Output Input Input Input
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Table Signal Pinout Listing
Signal Name L1_TSTCLK(1) L2_TSTCLK
CBGA Number A08, B09, A09, A02, A13, D10, B13, A15, B16, C14, B07, B08, C03, C06, C08, D05, D06, F03, H04,
Active High High High High High High High High
Input Input Input Input Input Input Output Output Input Input Input Input Input Output Input Input Output Input Input Input Input Output Input
LSSD_MODE
PLL_CFG[0-3] QACK QREQ RSRV SRESET SYSCLK TBEN TBST TC[0-1] TLBISYNC TRST TSIZ[0-2] TT[0-4]
VOLTDETGND(3) Output Notes: These test signals factory only must pulled OVDD normal machine operation. OVDD inputs supply power drivers inputs supply power processor core. (no-connect) 603e package; internally tied 603r package indicate power supply that low-voltage processor present.
Signal Description
Figure Table Table describe signals TSPC603r indicate signal functions. test signals, TRST, TMS, TCK, TDO, comply with subset P-1149.1 IEEE testability standard. signals LSSD_MODE, LI_TSTCLK L2_TSTCLK test signals factory only must pulled normal machine operations.
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Figure Functional Signal Groups
ADDRESS ARBITRATION A[0-31] ADDRESS AP[0-3] TT[0-4] TBST TSIZ[0-2] TRANSFER ATTRIBUTE CSE[0-1] TC[0-1] DBWO DATA ATTRIBUTION
ADDRESS START
DH[0-31], DL[0-31] DP[0-7] DBDIS DRTRY INT, CKSTP_IN, CKSTP_OUT HRESET, SRESET RSRV QREQ, QACK TBEN TLBISYNC INTERRUPTS CHECKSTOPS RESET DATA TERMINATION DATA TRANSFER
603r
PROCESSOR STATUS
AACK ADDRESS TERMINATION ARTRY SYSCLK CLOCKS CLK_OUT PLL_CFG[0-3] POWER SUPPLY INDICATOR VOLTDETGND
TRST, TCK, TMS, TDI, LSSD_MODE, L1_TSTCLK, L2_TSTCLK OVDD AVDD
JTAG/COP INTERFACE LSSD TEST CONTROL
POWER SUPPLY
Table Address data signal index
Signal Name Address Data Data Mnemonic A[0-31] DH[0-31] DL[0-31] Signal function output, physical address data transferred. input, represents physical address snoop operation. Represents state data, during data write operation output, during data read operation input. Represents state data, during data write operation output, during data read operation input. Signal type
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Table Signal index
Signal Name Address Acknowledge Address Busy Mnemonic AACK Signal function address phase transaction complete output, 603r address master input, address output, represents parity each bytes physical address transaction input, represents parity each bytes physical address snooping operations Incorrect address parity detected snoop output, detects condition which snooped address tenure must retried input, must retry preceding address tenure May, with proper qualification, assume mastership address Request mastership address single-beat transfer will cached Provides clock output testing monitoring Must terminate operation internally gating clocks, release outputs detected checkstop condition ceased operation Cache replacement element current transaction reloading into writing cache output, 603r data master input, another device master (For write transaction) must release data data parity high impedance during following cycle May, with proper qualification, assume mastership data data tenure output, parity each bytes data write transactions input, parity each byte read data Incorrect data parity Must invalidate data from previous read operation output, transaction global input, transaction must snooped 603r Initiates complete hard reset operation Initiates interrupt register LSSD test control signal factory only LSSD test control signal factory only LSSD test control signal factory only Signal type Input
Address Parity
AP[0-3]
Address Parity Error Address Retry Grant Request Cache Inhibit Test Clock Checkstop Input Checkstop Output Cache Entry Data Busy Data Disable Data Grant Data Write Only Data Parity Data Parity Error Data Retry Global Hard Reset Interrupt
ARTRY CLK_OUT CKSTP_IN CKSTP_OUT CSE[0-1] DBDIS DBW0 DP[0-7] DRTRY HRESET LSSD_MODE L1_TSTCLK L2_TSTCLK
Output Input Output Output Output Input Output Output Input Input Input Output Input Input Input Input Input Input
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Table Signal index
Signal Name Machine Check Interrupt Configuration Quiescent Acknowledge Quiescent Request Reservation System Management Interrupt Soft Reset System Clock Transfer Acknowledge Timebase Enable Transfer Burst Transfer Code Test Clock Test Data Input Test Data Output Transfer Error Acknowledge TLBI Sync Test Mode Select Test Reset Transfer Size Mnemonic PLL_CFG[0-3] QACK QREQ RSRV SRESET SYSCLK TBEN TBST TC[0-1] TLBISYNC TRST TSIZ[0-2] Signal function Initiates machine check interrupt operation register EMCP HID0 register Configures operation internal processor clock frequency activity terminated 603r enter quiescent power) state requesting activity normally enter quiescent (low power) state Represents state reservation coherency reservation address register Initiates system management interrupt operation register Initiates processing reset exception Represents primary clock input 603r, clock frequency 603r operation single-beat data transfer completed successfully data beat burst transfer completed successfully timebase should continue clocking output, burst transfer progress input, when snooping single-beat reads Special encoding transfer progress Clock signal IEEE P1149.1 test access port (TAP) Serial data input Serial data output error occurred Instruction execution should stop after execution tlbsync instruction Selects principal operations test-support circuitry Provides asynchronous reset controller memory accesses, these signals along with TBST indicate data transfer size current operation output, begun memory transaction address transfer attribute signals valid input, another master begun transaction address transfer attribute signals valid snooping (see GBL) Type transfer progress single-beat transaction write-through Available only package Indicates power supply that low-voltage processor present. Signal type Input Input Input Output Output Input Input Input Input Input Output Input Input Output Input Input Input Input
Transfer start
Transfer Type Write-Through Power supply indicator
TT[0-4] VOLTDETGND
Output Output
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Detailed Specifications
Scope Applicable Documents Requirements
General Design construction microcircuits accordance with applicable documents specified herein. Terminal connections terminal connections shall shown Figure Figure Lead material finish Lead material finish shall specified MIL-STD-1835. Absolute Maximum Ratings Absolute maximum ratings stress rating only functional operation maximum guaranteed. Stresses beyond those listed affect device reliability cause permanent damage device. This drawing describes specific requirements microprocessor TSPC603r, compliance with MIL-STD-883 class ATMEL-Grenoble standard screening. MIL-STD-883: Test methods procedures electronics. MIL-PRF-38535: General specifications microcircuits.
Table Absolute Maximum Rating 603r
Parameter Core Supply Voltage Supply Voltage Supply Voltage Input Voltage Storage Temperature Range Notes: Symbol AVdd OVdd Tstg -0.3 -0.3 -0.3 -0.3 2.75 2.75 +150 Unit
Functional operating conditions given electrical specifications. Stresses beyond absolute maximums listed affect device reliability cause permanent damage device. Caution: Input voltage must greater than OVdd more than 2.5V times, including during power-on reset. Caution: OVdd voltage must greater than Vdd/AVdd more than 1.2V times, including during power-on reset. Caution: Vdd/AVdd voltage must greater than OVdd more than 0.4V times, including during power-on reset.
Recommended Operating Conditions
Parameter Core Supply Voltage Supply Voltage Supply Voltage Input Voltage Operating Temperature
These recommended tested operating conditions. Proper device operation outside these conditions guaranteed.
Symbol AVdd OVdd 2.375 2.375 3.135 2.625 2.625 3.465 +125 Unit
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Thermal Characteristics data found this section concerns 603r's packaged 255-lead multi-layer ceramic (MLC), ceramic package. Data shown case using Thermalloy #2328B heat sink. internal thermal resistance this package negligible exposed design. thermal interface material recommended package lid-to-heat sink interface minimize thermal contact resistance. Additionally, CBGA package offers excellent thermal connection card power planes. Heat generated chip dissipated through package, heat sink (when used) card. parallel heat flow paths result lowest overall thermal resistance well offer significantly better power dissipation capability heat sink used. thermal characteristics flip-chip CBGA CI-CGA packages follows: Thermal resistance (junction-to-case) 0.095°C/Watt packages. Thermal resistance (junction-to-ball) 3.5°C/Watt CBGA package. Thermal resistance (junction-to-bottom SCI) 3.7°C/Watt CI-CGA package. junction temperature calculated from junction ambient thermal resistance, follow: Junction temperature: (Rjc Rsa) Where: ambient temperature vicinity device junction-to-case thermal resistance device case-to-heat sink thermal resistance interface material heat sink-to-ambient thermal resistance power dissipated device During operation, die-junction temperatures (Tj) should maintained less than value specified Table thermal resistance thermal interface material (Rcs) typically about 1°C/Watt. Assuming 85°C consumption Watts, junction temperature device would follow: 85°C (0.095°C/Watt 1°C/Watt Rsa) Watts. Thermalloy heat sink #2328B, heat sink-to-ambient thermal resistance (Rsa) versus airflow velocity shown Figure
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Figure CBGA Thermal Management Example
(°C/W) Heat Sink Thermal Resistance Approach velocity (m/sec)
Assuming velocity m/sec, associated overall thermal resistance junction temperature, found Table will result. Table Thermal Resistance Junction Temperature
Configuration With 2328B heat sink (°C/W) (°C)
Vendors such Aavid Engineering Inc., Thermalloy, Wakefield Engineering supply heat sinks with wide range thermal performance. Power Consideration PowerPC603r microprocessor specifically designed low-power operation. 603e microprocessor version, 603r provides both automatic program-controllable power reduction modes progressive reduction power consumption. This chapter describes hardware support provided 603r power management. Dynamic Power Management Dynamic power management automatically powers down individual execution units 603r, based upon contents instruction stream. example, floating-point instructions being executed, floating-point unit automatically powered down. Power actually removed from execution unit; instead, each execution unit independent clock input, which automatically controlled clock-by-clock basis. Since CMOS circuits consume negligible power when they switching, stopping clock execution unit effectively eliminates power consumption. operation completely transparent software external hardware. Dynamic power management enabled setting HID0 power-up, following HRESET. Programmable Power Modes 603r provides four programmable power states-full power, doze, sleep. Software selects these modes setting (and only one) three power saving mode bits. Hardware enable power management state through external asynchronous interrupts hardware interrupt causes transfer program flow interrupt handler code. appropriate mode then software. 603r provides separate interrupt interrupt vector power management-the system management interrupt (SMI). 603r also contains decrement timer which allows enter doze mode predetermined amount time then return full power operation through decrementer interrupt (DI).
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Note that 603r cannot switch from power management mode another without first returning full mode. sleep modes disable snooping; therefore, hardware handshake provided ensure coherency before 603r enters these power management modes. Table summarizes four power states. Table Power 603r Microprocessor Programmable Power Modes
Mode Full Power Full Power (with DPM) Doze Functioning Units units active Requested logic demand snooping Data cache needed Decrementer timer Decrementer timer Activation Method instruction dispatch Controlled Full-Power Wake Method External asynchronous exceptions(1) Decrementer interrupt Reset External asynchronous exceptions Decrementer interrupt Reset External asynchronous exceptions Reset
Controlled hardware software Controlled hardware software
Sleep Note:
None
Exceptions referred interrupts architecture specification
Power Management Modes following sections describe characteristics 603r's power management modes, requirements entering exiting various modes, system capabilities provided 603r while power management modes active. FULL-POWER MODE WITH DISABLED: Full-power mode with disabled power mode selected when enable (bit HID0 cleared. Default state following power-up HRESET. functional units operating full processor speed times.
FULL-POWER MODE WITH ENABLED: Full-power mode with enabled (HID0[11] provides on-chip power management without affecting functionality performance 603r. Required functional units operating full processor speed. Functional units clocked only when needed. software hardware intervention required after mode set. Software/hardware performance transparent.
DOZE MODE: Doze mode disables most functional units maintains cache coherency enabling interface unit snooping. snoop will cause 603r enable data cache, copy data back memory, disable cache, fully return doze state. Most functional units disabled. snooping time base/decrementer still enabled. Dose mode sequence: doze (HID0[8) 603r enters doze mode after several processor clocks. Several methods returning full-power mode: Assert INT, SMI, decrementer interrupts. Assert hard reset soft reset.
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Transition full-power state takes more than processor cycles. running locked SYSCLK.
MODE: mode disables 603r still maintains phase locked loop (PLL) time base/decrementer. time base used restore 603r full-on state after programmed amount time. Because snooping disabled sleep mode, hardware handshake using quiesce request (QREQ) quiesce acknowledge (QACK) signals requires maintain data coherency. 603r will assert QREQ signal indicate that ready disable snooping. When system ensured that snooping longer necessary, will assert QACK 603r will enter sleep mode. Time base/decrementer still enabled. Most functional units disabled (including snooping). nonessential input receivers disables. mode sequence: (HID0[9] 603r asserts quiesce request (QREQ) signal. System asserts quiesce acknowledge (QACK) signal. 603r enters sleep mode after several processor clocks. Several methods returning full-power mode: Assert INT, SPI, decrementer interrupts. Assert hard reset soft reset. Transition full-power takes more than processor cycles. running locked SYSCLK.
SLEEP MODE: Sleep mode consumes least amount power four modes since functional units disabled. conserve maximum amount power, disabled SYSCLK removed. fully static design 603r, internal processor state preserved when internal clock present. Because time base decrementer disabled while 603r sleep mode, 603r's time base contents will have updated from external time base following sleep mode accurate time-of-day maintenance required. Before 603r enters sleep mode, 603r will assert QREQ signal indicate that ready disable snooping. When system ensured that snooping longer necessary, will assert QACK 603r will enter sleep mode. functional units disabled (including snooping time base). nonessential input receivers disabled: Internal clock regenerators disabled. still running (see below). Sleep mode sequence: sleep (HID0[10] 603r asserts quiesce request (QREQ). System asserts quiesce acknowledge (QACK). 603r enters sleep mode after several processor clocks. Several methods returning full-power mode: Assert INT, SMI, interrupts. Assert hard reset soft reset. disabled SYSCLK removed while sleep mode.
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Return full-power mode after SYSCLK disabled sleep mode: Enable SYSCLK. Reconfigure into desired processor clock mode. System logic waits startup relock time (100 µsec). System logic asserts sleep recovery signals (for example, SMI).
Power Management Software Considerations Since 603r dual issue processor with out-of-order execution capability, care must taken power management mode entered. Furthermore, sleep modes require outstanding operations completed before power management mode entered. Normally during system configuration time, power management modes would selected setting appropriate HID0 mode bit. Later power management mode invoked setting MSR[POW] bit. provide clean transition into power management mode, stmsr[POW] should preceded sync instruction followed isync instruction. Power Dissipation Table Power Dissipation Vdd/AVdd OVdd 125°C Clock Frequency
Full-On Mode (DPM Enabled) Typical Doze Mode Typical Mode Typical Sleep Mode Typical Units
Sleep Mode-PLL Disabled Typical
Sleep Mode-PLL SYSCLK Disabled Typical Maximum Notes:
These values apply valid PLL_CFG[0-3] settings include output driver power (OVDD) analog supply power (AVDD). OVDD power system dependent typically VDD. Worst-case AVDD Typical power average value measured AVDD 2.5V, 3.3V, system executing typical applications benchmark sequences. Maximum power measured 2.625V using worst-case instruction mix. calculate power consumption temperature (-55°C), factor 1.25.
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Marking
document where defined marking identified related reference documents. Each microcircuit legible permanently marked with following information minimum: ATMEL logo, Manufacturer's part number, Class identification applicable, Date-code inspection lot, identifier available, Country manufacturing.
Electrical Characteristics
General Requirements static dynamic electrical characteristics specified inspection purposes relevant measurement conditions given below: Table Static electrical characteristics electrical variants. Table Dynamic electrical characteristics 603r.
These specifications processor core frequencies. processor core frequency determined (SYSCLK) frequency settings PLL_CFG0 PLL_CFG3 signals. timings specified respective rise edge SYSCLK. Static Characteristics Table Electrical Characteristics AVdd 2.5V OVdd -55°C 125°C
Characteristics Input High Voltage (all inputs except SYSCLK) Input Voltage (all inputs except SYSCLK) SYSCLK Input High Voltage SYSCLK Input Voltage Input Leakage Current Hi-Z (off-state) Leakage Current Output High Voltage Output Voltage 3.465V
(1)(3)
Symbol CVIH CVIL ITSI ITSI 5.5V(1)(3) 3.465V(1)(3) 5.5V
(1)(3)
10.0 15.0
Unit
Capacitance, (excludes ABB, DBB, ARTRY) Capacitance, MHz(2) (for ABB, DBB, ARTRY) Notes:
Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK, JTAG signals). Capacitance periodically sampled rather than 100% tested. Leakage currents measured nominal OVdd both OVdd Vdd. Same variation (for example, both OVdd vary either -5%).
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Dynamic Characteristics Clock Specifications Table provides clock timing specifications defined Figure
Table Clock Timing Specifications AVdd 2.5V OVdd -55°C 125°C
Characteristics Processor Frequency Frequency SYSCLK (bus) Frequency SYSCLK Cycle Time SYSCLK Rise Fall Time SYSCLK Duty Cycle (1.4V measured) SYSCLK Jitter 603r Internal Relock Time Notes: 40.0 66.7 60.0 ±150 33.3 13.3 40.0 66.7 60.0 ±150 33.3 13.3 40.0 60.0 ±150 33.3 13.3 40.0 60.0 ±150 33.3 13.3 40.0 60.0 ±150 Unit Note
Rise fall times SYSCLK input measured from 0.4V 2.4V. Cycle-to-cycle jitter guaranteed design. Timing guaranteed design characterization, tested. relock time maximum amount time required lock after stable Vdd, OVdd, AVdd SYSCLK reached during power-on reset sequence. This specification also applies when been disabled subsequently re-enabled during sleep mode. Also note that HRESET must held asserted minimum clocks after relock time (100 during power-on reset sequence. Caution: SYSCLK frequency PLL_CFG[0-3] settings must chosen such that resulting SYSCLK (bus) frequency, (core) frequency, (VCO) frequency exceed their respective maximum minimum operating frequencies. Refer PLL_CFG[0-3] signal description valid PLL_CFG[0-3] settings.
Figure SYSCLK Input Timing Diagram
Input specifications
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Table provides input timing specifications 603r defined Figure Figure Table Input Timing Specifications AVdd 2.5V OVdd -55°C 125°C
166,200 Notes: Characteristics Address/data/transfer attribute inputs valid SYSCLK (input setup) other inputs valid SYSCLK (input setup) Mode select inputs valid HRESET (input setup) (for DRTRY, QACK TLBISYNC) SYSCLK address/data/transfer attribute inputs invalid (input hold) SYSCLK other inputs invalid (input hold) HRESET mode select inputs invalid (input hold) (for DRTRY, QACK, TLBISYNC) 233,266 Unit tsysclk Note 4,5,6, 4,6,7
input specifications measured from level (0.8 2.0V) signal question 1.4V rising edge input SYSCLK. Both input output timings measured pin. Figure Address/data/transfer attribute input signals composed following: A[0-31], AP[0-3], TT[0-4], TC[0-1], TBST, TSIZ[0-2], GBL, DH[0-31], DL[0-31], DP[9-7]. other input signals composed following: ABB, DBB, ARTRY, AACK, DBG, DBWO, DRTRY, TEA, DBDIS, HRESET, SRESET, INT, SMI, MCP, TBEN, QACK, TLBISYNC. setup hold time with respect rising edge HRESET. Figure tsysclk period external clock (SYSCLK) nanoseconds (ns). numbers given table must multiplied period SYSCLK compute actual time duration nanoseconds) parameter question. These values guaranteed design, tested. This specification configuration mode only. Also note that HRESET must held asserted minimum clocks after relock time (100 during power-on reset sequence.
Figure Input Timing Diagram
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Figure Mode Select Input Timing Diagram
Output Specifications Table provides output timing specifications 603r (shown Figure Table Output Timing Specifications AVdd 2.5V OVdd -55°C 125°C
166,200 Notes: Characteristic SYSCLK output driven (output enable time) SYSCLK output valid (5.5V 0.8V-TS, ABB, ARTRY, DBB) SYSCLK output valid (TS, ABB, ARTRY, DBB) SYSCLK output valid (5.5V 0.8V-all except ABB, ARTRY, DBB) SYSCLK output valid (all except TS,ABB,ARTRY,DBB) SYSCLK output invalid (output hold) SYSCLK output high impedance (all except ARTRY, ABB, DBB) SYSCLK ABB, DBB, high impedance after precharge SYSCLK ARTRY high impedance before precharge SYSCLK ARTRY precharge enable Maximum delay ARTRY precharge SYSCLK ARTRY high impedance after precharge tsysclk 11.0 233,266 tsysclk 11.0 tsysclk 11.0 Unit tsysclk tsysclk tsysclk Note
output specifications measured from 1.4V rising edge SYSCLK level (0.8V 2.0V) signal question. Both input output timings measured pin. Figure maximum timing specifications assume This minimum parameter assumes SYSCLK output valid (5.5V 0.8V) includes extra delay associated with discharging external voltage from 5.5V 0.8V instead from 0.8V CMOS levels instead 3.3V CMOS levels).
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tsysclk period external clock (SYSCLK) nanoseconds (ns). numbers given table must multiplied period SYSCLK compute actual time duration nanoseconds) parameter question. Output signal transitions from 2.0V 0.8V. Nominal precharge width tsysclk. Nominal precharge width ARTRY tsysclk.
Figure Output Timing Diagram
JTAG Timing Specifications Table JTAG Timing Specifications (independent SYSCLK) AVdd 2.5V OVdd -55°C 125°C
Characteristic frequency operation cycle time clock pulse width measured 1.4V rise fall times TRST setup time rising edge TRST assert time Boundary scan input data setup time Boundary scan input data hold time output data valid output high impedance 62.5 Unit Notes
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Table JTAG Timing Specifications (independent SYSCLK) AVdd 2.5V OVdd -55°C 125°C
Notes: Characteristic TMS, data setup time TMS, data hold time data valid Unit Notes
high impedance TRST asynchronous signal. setup time test purposes only. Non-test signal input timing with respect TCK. Non-test signal output timing with respect TCK.
Figure Clock Input Timing Diagram
Figure TRST Timing Diagram
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Figure Boundary-scan Timing Diagram
Figure Test Access Port Timing Diagram
Functional Description
PowerPC Registers Programming Model PowerPC architecture defines register-to-register operations most computational instructions. Source operands these instructions accessed from registers provided immediate values embedded instruction opcode. three-register instruction format allows specification target register distinct from source operands. Load store instructions transfer data between registers memory. PowerPC processors have levels privilege supervisor mode operation (typically used operating system) user mode operation (used application software). programming models incorporate GPRs, FPRs, special-purpose registers (SPRs) several miscellaneous registers. Each PowerPC microprocessor also unique hardware implementation (HID) registers.
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Having access privilege instructions, registers, other resources allows operating system control application environment (providing virtual memory protecting operating-system critical machine resources). Instructions that control state processor, address translation mechanism, supervisor registers executed only when processor operating supervisor mode. following sections summarize PowerPC registers that implemented 603r. General-Purpose Registers (GPRs) PowerPC architecture defines user-level, general-purpose registers (GPRs). These registers either bits wide 32-bit PowerPC microprocessors bits wide 64-bit PowerPC microprocessors. GPRs serve data source destination integer instructions. Floating-Point Registers (FPRs) PowerPC architecture also defines user-level, 64-bit floating-point registers (FPRs). FPRs serve data source destination floating-point instructions. These registers contain data objects either single- double-precision floating-point formats. Condition Register (CR) 32-bit user-level register that consists eight four-bit fields that reflect results certain operations, such move, integer floating-point compare, arithmetic, logical instructions, provide mechanism testing branching. Floating-Point Status Control Register (FPSCR) floating-point status control register (FPSCR) user-level register that contains exception signal bits, exception summary bits, exception enable bits, rounding control bits needed compliance with IEEE standard. Machine State Register (MSR) machine state register (MSR) supervisor-level register that defines state processor. contents this register saved when exception taken restored when exception handling completes. 603r implements 32-bit register, 64-bit PowerPC processors implement 64-bit MSR. Segment Registers (SRs) memory management, 32-bit PowerPC microprocessors implement sixteen 32-bit segment registers (SRs). speed access, 603r implements segment registers arrays; main array (for data memory accesses) shadow array (for instruction memory accesses). Loading segment entry with Move Segment Register (stsr) instruction loads both arrays. Special-Purpose Registers (SPRs) powerPC operating environment architecture defines numerous special-purpose registers that serve variety functions, such providing controls, indicating status, configuring processor, performing special operations. During normal execution, program access registers, shown Figure depending program's access privilege (supervisor user, determined privilege-level (PR) MSR). Note that register such GPRs FPRs accessed through operands that part instructions. Access registers explicit (that through specific instructions that purpose such Move Special-Purpose Register (mtspr) Move from Special-Purpose Register
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(mfspr) instructions) implicit, part execution instruction. Some registers accessed both explicitly implicitly. 603r, SPRs bits wide. USER-LEVEL SPRs: following 603r SPRs accessible user-level software: Link register (LR) link register used provide branch target address hold return address after branch link instructions. bits wide 32-bit implementations. Count register (CTR) decremented tested automatically result branch-and-count instructions. bits wide 32-bit implementations. Integer exception register (XER) 32-bit contains summary overflow bit, integer carry bit, overflow bit, field specifying number bytes transferred Load String Word Indexed (lswx) Store String Word Indexed (stswx) instruction.
SUPERVISOR-LEVEL SPRs: 603r also contains SPRs that accessed only supervisor-level software. These registers consist following: 32-bit DSISR defines cause data access alignment exceptions. data address register (DAR) 32-bit register that holds address access after alignment exception. Decrementer register (DEC) 32-bit decrementing counter that provides mechanism causing decrementer exception after programmable delay. 32-bit SDR1 specifies page table format used virtual-to-physical address translation pages. (Note that physical address referred real address architecture specification). machine status save/restore register (SRR0) 32-bit register that used 603r saving address instruction that caused exception, address return when Return from Interrupt (rfi) instruction executed. machine status save/restore register (SRR1) 32-bit register used save machine status exceptions restore machine status when instruction executed. 32-bit SPRG0-SPRG3 registers provided operating system use. external access register (EAR) 32-bit register that controls access external control facility through External Control Word Indexed (eciwx) External Control Word Indexed (ecowx) instructions. time base register (TB) 64-bit register that maintains time operates interval timers. consists 32-bit fields time base upper (TBU) time base lower (TBL). processor version register (PVR) 32-bit, read-only register that identifies version (model) revision level PowerPC processor. Block address translation (BAT) arrays PowerPC architecture defines registers, divided into four pairs data BATs (DBATs) four pairs instruction BATs (IBATs). Figure list numbers arrays. following supervisor-level SPRs implementation-specific 603r: DMISS IMISS registers read-only registers that loaded automatically upon instruction data miss. HASH1 HASH2 registers contain physical addresses primary secondary page table entry groups (PTEGs). ICMP DCMP registers contain duplicate first word page table entry (PTE) which table search looking.
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required physical address (RPA) register loaded processor with second word correct during page table search. hardware implementation (HID0 HID1) registers provide means enabling 603r's checkstops features, allows software read configuration configuration signals. instruction address breakpoint register (IABR) loaded with instruction address that compared instruction addresses dispatch queue. When address match occurs, instruction address breakpoint exception generated.
Figure shows 603r registers available user supervisor level. number right SPRs indicate number that used syntax instruction operands access register.
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Figure PowerPC Microprocessor Programming Model Register
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Instruction Addressing Modes following subsections describe PowerPC instruction addressing modes general. PowerPC Instruction Addressing Modes PowerPC instructions encoded single-word (32-bit) opcodes. Instruction formats consistent among instruction types, permitting efficient decoding occur parallel with operand accesses. This fixed instruction length consistent format greatly simplifies instruction pipelining. PowerPC INSTRUCTION SET: PowerPC instructions divided into following categories: Integer instructions These include computational logical instructions. Integer arithmetic instructions. Integer compare instructions. Integer logical instructions. Integer rotate shift instructions. Floating-point instructions -These include floating-point computational instructions, well instructions that affect FPSCR. Floating-point arithmetic instructions. Floating-point multiply/add instructions. Floating-point rounding conversion instructions. Floating-point compare instructions. Floating-point status control instructions. Load/store instructions These include integer floating-point load store instructions. Integer load store instruction. Integer load store multiple instructions. Floating-point load store. Primitives used construct atomic memory operations (lwarx stwcx. instructions). Flow control instructions These include branching instructions, condition register logical instructions, trap instructions, other instructions that affect instruction flow. Branch trap instructions. Condition register logical instructions. Processor control instructions These instructions used synchronizing memory accesses management caches, TLBs, segment registers. Move to/from instructions. Move to/from MSR. Synchronize. Instruction synchronize. Memory control instruction These instructions provide control caches, TLBs, segment registers. Supervisor-level cache management instructions. User-level cache instructions. Segment register manipulation instructions. Translation look aside buffer management instructions.
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Note that this grouping instructions does indicate which execution unit executes particular instruction group instructions. Integer instructions operate byte, half-word, word operands. Floating-point instructions operate single-precision (one word) double-precision (one double word) floating-point operands. PowerPC architecture uses instructions that four bytes long word-aligned. provides byte, half-word, word operand loads stores between memory GPRs. also provides word double-word operand loads stores between memory floating-point registers (FPRs). Computational instructions modify memory. memory operand computation then modify same another memory location, memory contents must loaded into register, modified, then written back target location with distinct instructions. PowerPC processors follow program flow when they normal execution state. However, flow instructions interrupted directly execution instruction asynchronous event. Either kind exception cause several components system software invoked. CALCULATING EFFECTIVE ADDRESSES: effective address (EA) 32-bit address computed processor when executing memory access branch instruction when fetching next sequential instruction. PowerPC architecture supports simple memory addressing modes: (RA|0) offset (including offset (register indirect with immediate index). (RA|0) (register indirect with index).
These simple addressing modes allow efficient address generation memory accesses. Calculation effective address aligned transfers occurs single clock cycle. memory access instruction, effective address operand length exceeds maximum effective address, memory operand considered wrap around from maximum effective address effective address Effective address computations both data instruction accesses 32-bit unsigned binary arithmetic. carry from ignored 32-bit implementations. PowerPC 603r Microprocessor Instruction 603r instruction defined follows: 603r provides hardware support 32-bit PowerPC instructions. 603r provides implementation-specific instructions used software table search operations following misses: Load Data Entry (tlbld). Load Instruction Entry (tlbli). 603r implements following instructions which defined optional PowerPC architecture External Control Word Indexed (eciwx). External Control Word Indexed (ecowx). Floating Select (fsed). Floating Reciprocal Estimate Single-Precision (fres). Floating Reciprocal Square Root Estimate (frsqrte). Store Floating-Point Integer Word (stfiwx).
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Cache Implementation following subsections describe PowerPC architecture's treatment cache general, 603r specific implementation, respectively. PowerPC Cache Characteristics PowerPC architecture does define hardware aspects cache implementations. example, some PowerPC processors, including 603r, have separate instruction data caches (hardware architecture), while others, such PowerPC microprocessor, implement unified cache. PowerPC microprocessor control following memory access modes page block basis: Write-back/write-through mode. Cache-inhibited mode. Memory coherency.
Note that 603r, cache line defined eight words. defines cache management instructions that provide means which application programmer affect cache contents. PowerPC 603r Microprocessor Cache Implementation 603r 16-Kbyte, four-way set-associative (instruction data) caches. caches physically addressed, data cache operate either write-back write-through mode specified PowerPC architecture. data cache configured sets lines each. Each line consists bytes, state bits, address tag. state bits implement three-state (modified/exclusive/invalid) protocol. Each line contains eight 32-bit words. Note that PowerPC architecture defines term block cacheable unit. 603r, block size equivalent cache line. block diagram data cache organization shown Figure instruction cache also consists sets lines, each line consists bytes, address tag, valid bit. instruction cache written except through line fill operation. instruction cache snooped, cache coherency must maintained software. fast hardware invalidation capability provided support cache maintenance. organization instruction cache very similar data cache shown Figure Each cache line contains eight contiguous words from memory that loaded from 8-word boundary (that bits A27-A32 effective addresses zero); thus, cache line never crosses page boundary. Misaligned accesses across page boundary incur performance penalty. 603's cache lines loaded four beats bits each. burst load performed "critical double word first". cache that being loaded blocked internal accesses until load completes. critical double word simultaneously written cache forwarded requesting unit, thus minimizing stalls load delays. ensure coherency among caches multiprocessor multiple caching-device) implementation, 603r implemements protocol. These three states, modified, exclusive, invalid, indicate state cache block follows: Modified cache line modified with respect system memory; that data this address valid only cache system memory. Exclusive This cache line holds valid data that identical data this address system memory. other cache this data. Invalid This cache line does hold valid data.
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Cache coherency enforced on-chip snooping logic. Since 603r's data cache tags single ported, simultaneous load store snoop access represent resource contention. snoop access given first access tags. load store then occurs clock following snoop. Figure Data Cache Organization
Exception Model
following subsections describe PowerPC exception model 603r implementation, respectively. PowerPC Exception Model PowerPC exception mechanism allows processor change supervisor state result external singles, errors, unusual conditions arising execution instructions, differ from arithmetic exceptions defined IEEE floating-point operations. When exceptions occur, information about state processor saved certain registers processor begins execution address (exception vector) predetermined each exception. Processing exceptions occurs supervisor mode. Although multiple exception conditions single exception vector, more specific condition determined examining register associated with exception example, DSISR FPSCR. Additionally, some exception conditions explicitly enable disabled software. PowerPC architecture requires that exceptions handled program order; therefore, although particular implementation recognize exception conditions order, they presented strictly order. When instruction-caused exception recognized, unexecuted instructions that appear earlier instruction stream, including that have entered execute state, required complete before exception taken. exceptions caused those instructions handled first. Likewise, exceptions that asynchronous precise recognized when they occur, handled until instruction currently completion state successfully completes execution generates exception, completed store queue emptied.
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Unless catastrophic causes system reset machine check exception, only exception handled time. example, single instruction encounters multiple exception conditions, those conditions encountered sequentially. After exception handler handles exception, instruction execution continues until next exception condition encountered. However, many cases there attempt re-execute instruction. This method recognizing handling exception conditions sequentially guarantees that exceptions recoverable. Exception handlers should save information stored SRR0 SRR1 early prevent program state from being lost system reset machine check exception instruction-caused exception exception handler, before enabling external interrupts. PowerPC architecture support four types exceptions: Synchronous, precise These causes instructions. instruction-caused exceptions handled precisely; that machine state time exception occurs known completely restored. This means that (excluding trap system call exceptions) address faulting instruction provided exception handler that neither faulting instruction subsequent instructions code stream will complete execution before exception taken. Once exception processed, execution resumes address faulting instruction alternate address provided exception handler). When exception taken trap system call instruction, execution resumes address provided handler. Synchronous, imprecise PowerPC architecture defines imprecise floating-point exception modes, recoverable nonrecoverable. Even though 603r provides means enable imprecise modes, implements these modes identically precise mode (-hat enabled floating-point enabled exceptions always precise 603r). Asynchronous, maskable external, SMI, decrementer interrupts maskable asynchronous exceptions. When these exceptions occur, their handling postponed until next instruction, exceptions associated with that instruction, completes execution. there instructions execution units, exception taken immediately upon determination correct restart address (for loading SRR0). Asynchronous, maskable There maskable asynchronous exceptions: system reset machine check exception. These exceptions recoverable, provide limited degree recoverability. exceptions report recoverability through SMR[RI] bit.
PowerPC 603r Microprocessor Exception Model specified PowerPC architecture, 603r exceptions described either precise imprecise either synchronous asynchronous. Asynchronous exceptions (some which maskable) caused events external processor's execution; synchronous exceptions, which handled precisely 603r, caused instructions. 603r exception classes shown Table
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Table PowerPC 603r Microprocessor Exception Classifications
Synchronous/Asynchronous Asynchronous, Maskable Precise/Imprecise Imprecise Exception Type Machine check System reset External interrupt Decrementer System management interrupt Instruction-caused exceptions
Asynchronous, Maskable Synchronous
Precise Precise
Although exceptions have other characteristics well, such whether they maskable maskable, distinctions shown Table define categories exceptions that 603r handles uniquely. Note that Table includes synchronous imprecise instructions. While PowerPC architecture supports imprecise handling floating-point exceptions, 603r implements these exception modes precise exceptions. 603r's exceptions, conditions that cause them, listed Table Exceptions that specific 603r indicated. Table Exceptions Conditions
Exception Type Reserved System Reset Machine Check Vector Offset (hex) 00000 00100 00200 00300 Causing Conditions system reset caused assertion either SRESET HRESET. machine check caused assertion signal during data transaction, assertion MCP, address data parity error. cause exception determined settings DSISR, listed follows: translation attempted access found primary hash table entry group (HTEG), rehashed secondary HTEG, range DBAT register; otherwise cleared. memory access permitted page DBAT protection mechanism; otherwise cleared. eciwx ecowx instruction access address that marked write-through, execution load/store instruction that accesses direct-store segment. store operation cleared load operation. eciwx ecowx used EAR[E] cleared. exception caused when instruction fetch cannot performed following reasons: effective (logical) address cannot translated. That there page fault this portion translation, exception must taken load (and possibly page) into memory. fetch access violates memory protection. bits segment register bits prohibit read access, instructions cannot fetched from this location. external interrupt caused when MSR[EE] signal asserted.
00400
External interrupt
00500
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Table Exceptions Conditions (Continued)
Exception Type Alignment Vector Offset (hex) 00600 Causing Conditions alignment exception caused when 603e cannot perform memory access reasons described below: operand floating-point load store instruction word-aligned. operand lmw, stmw, lwarx, stwcx, instructions aligned. operand single-register load store operation aligned, 603e little-endian mode. instruction lmw, stmw, lswi, lwsx, stswi, stswx 603e little-endian mode. operand dcbz storage that write-through-required, caching inhibited. program exception caused following exception conditions, which correspond settings SRR1 arise during execution instruction: Floating-point enabled exception-A floating-point enabled exception condition generated when following condition met: (MSR[FE0] MSR[FE1]) FPSCR[FEX] FPSCR[FEX] execution floating-point instruction that causes enabled exception execution "move FPSCR" instructions that results both exception condition corresponding enable being FPSCR. Illegal instruction-An illegal instruction program exception generated when execution instruction attempted with illegal opcode illegal combination opcode extended opcode fields (including PowerPC instructions implemented 603e), when execution optional instruction provided 603e attempted (these include those optional instructions that treated no-ops). Privileged instruction-A privileged instruction type program exception generated when execution privileged instruction attempted register user privilege bit, MSR[PR], set. 603e, this exception generated mtspr mfspr with invalid field SPR[0] MSR[PR] This true PowerPC processors. Trap-A trap type program exception generated when conditions specified trap instruction met. floating-point unavailable exception caused attempt execute floating-point instruction (including floating-point load, store, more instructions) when floatingpoint available disabled, (MSR[FP] decrementer exception occurs when most significant decrementer (DEC) register transitions from Must also enabled with MSR[EE] bit. system call exception occurs when System Call (sc) instruction executed. trace execution taken when MSR[SE] when currently completing instruction branch MSR[BE] 603e does generate exception this vector. Other PowerPC processors this vector floating-point assist exceptions. instruction translation miss exception caused when effective address instruction fetch cannot translated ITLB. data load translation miss exception caused when effective address data load operation cannot translated DTLB. data store translation miss exception caused when effective address data store operation cannot translated DTLB; where DTLB occurs, change
Program
00700
Floating-point unavailable Decrementer Reserved System call Trace Reserved Reserved Instruction translation miss Data load translation miss Data store translation miss
00800
00900 00A00-00BFF 00C00 00D00 00E00 00E10-00FFF 01000 01100 01200
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Table Exceptions Conditions (Continued)
Exception Type Instruction address breakpoint System management interrupt Reserved Vector Offset (hex) 01300 Causing Conditions instruction address breakpoint exception occurs when address (bits 0-29) IABR matches next instruction complete completion unit, IABR enable (bit system management interrupt caused when MSR[EE] input signal asserted.
01400
01500-02FFF
Memory Management
following subsections describe memory management features PowerPC architecture, 603r implementation, respectively. PowerPC Memory Management primary functions translate logical (effective) addresses physical addresses memory accesses, provide access protection blocks pages memory. There types accesses generated 603r that require address translation- instruction accesses, data accesses memory generated load store instructions. PowerPC exception model support demand-paged virtual memory. Virtual memory management permits execution programs larger than size physical memory; demand-paged implies that individual pages loaded into physical memory from system memory only when they first accessed executing program. hashed page table variable-sized data structure that defines mapping between virtual page numbers physical page numbers. page table size power starting address multiple size. page table contains number page table entry groups (PTEGs). PTEG contains eight page table entries (PTEs) eight bytes each; therefore, each PTEG bytes long. PTEG addresses entry points table search operations. Address translations enabled setting bits MSR-MSR[IR] enables instruction address translations MSR[DR] enables data address translations. PowerPC 603r Microprocessor Memory Management instruction data memory management units 603r provide byte logical address space accessible supervisor user programs with byte page size 256M byte segment size. Block sizes range from 128K byte 256M byte software selectable. addition, 603r uses interim 52-bit virtual address hashed page tables generating 32-bit physical addresses. MMUs 603r rely exception processing mechanism implementation paged virtual memory environment enforcing protection designated memory areas. Instruction data TLBs provide address translation parallel with on-chip cache access, incurring additional time penalty event hit. cache most recently used page table entries. Software responsible maintaining consistency with memory. 603r's TLBs 64-entry, two-way set-associative caches that contain instruction data address translations. 603r provides hardware assist software table search operations through ashed page table misses. Supervisor software invalidate entries selectively.
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603r also provides independent four-entry arrays instructions data that maintain address translations blocks memory. These entries define blocks that vary from 128K byte 256M byte. arrays maintained system software. specified PowerPC architecture, hashed page table variable-sized data structure that defines mapping between virtual page numbers physical page numbers. page table size power starting address multiple size. Also specified PowerPC architecture, page table contains number page table entry groups (PTEGs). PTEG contains eight page table entries (PTEs) eight bytes each; therefore, each PTEG bytes long. PTEG addresses entry points table search operations. Instruction Timing 603r pipelined superscalar processor. pipelined processor which processing instruction reduced into discrete stages. Because processing instruction broken into series stages, instruction does require entire resources execution unit. example, after instruction completes decode stage, pass next stage, while subsequent instruction advance into decode stage. This improves throughput instruction flow. example, take three cycles floating-point instruction complete, there stalls floating-point pipeline, series floating-point instructions have throughput instruction cycle. instruction pipeline 603r four major pipeline stages, described follows: fetch pipeline stage primarily involves retrieving instructions from memory system determining location next instruction fetch. Additionally, decodes branches during fetch stage folds branch instructions before dispatch stage possible. dispatch pipeline stage responsible decoding instructions supplied instruction fetch stage, determining which instructions eligible dispatched current cycle. addition, source operands instructions read from appropriate register file dispatched with instruction execute pipeline stage. dispatch pipeline stage, dispatched instructions their operands latched appropriate execution unit. During execute pipeline stage each execution unit that executable instruction executes selected instruction (perhaps over multiple cycles), writes instruction's result into appropriate rename register, notifies completion stage that instruction finished execution. case internal exception, execution unit reports exception completion/writeback pipeline stage discontinues instruction execution until exception handled. exception signaled until that instruction next completed. Execution most floating-point instructions pipelined within allowing three instructions executing concurrently. pipeline stages floating-point unit multiply, add, round-convert. Execution most load/store instructions also pipelined. load/store units pipeline stages. first stage effective address calculation translation second stage accessing data cache. complete/writeback pipeline stage maintains correct architectural machine state transfers contents rename registers GPRs FPRs instructions retired. completion logic detects instruction causing exception, following instructions cancelled, their execution results rename registers discarded, instructions fetched from correct instruction stream.
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superscalar processor that issues multiple independent instructions into multiple pipelines allowing instructions execute parallel. 603r five independent execution units, each integer instructions, floating-point instructions, branch instructions, load/store instructions, system register instructions. each have dedicated register files maintaining operands (GPRs FPRs, respectively), allowing integer calculations floating-point calculations occur simultaneously without interference. Because PowerPC architecture applied such wide variety implementations, instruction timing among various PowerPC processors varies accordingly.
Preparation Delivery
Packaging Certificate Compliance Microcircuits prepared delivery accordance with MIL-PRF-38535. ATMEL-Grenoble offers certificate compliances with each shipment parts, affirming products compliance either with MIL-STD-883 guarantying parameters tested temperature extremes entire temperature range. devices must handled with certain precautions avoid damage accumulation static charge. Input protection devices have been designed chip minimize effect this static buildup. However, following handling practices recommended: Devices should handled benches with conductive grounded surfaces. Ground test equipment, tools operator. handle devices leads. Store devices conductive foam carriers. Avoid plastic, rubber, silk areas. Maintain relative humidity above percent practical.
Handling
Packages Mechanical Data
CBGA Package Parameters
following sections provide package parameters mechanical dimensions CBGA packages. package parameters provided following list. package type 255-lead ceramic ball grid array (CBGA).
Package outline Interconnects Pitch Maximum module height
1.27 3.00
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Mechanical dimensions CBGA package Figure provides mechanical dimensions bottom surface nomenclature CBGA package.
Figure Mechanical Dimensions Bottom Surface Nomenclature CBGA Package
Notes: Dimensioning tolerancing ASME Y14.5M-1994. Controlling dimension: millimeter
Millimeters 21.000 21.000 2.450 3.000 0.820 0.930 1.270 0.790 0.990 0.635 5.000 16.000 5.000 16.000
Inches 0.827 0.827 0.097 0.118 0.032 0.036 0.050 0.031 0.039 0.025 0.197 0.630 0.197 0.630
CI-CGA Package Parameters
package parameters provided following list. package type 255-lead ceramic ball grid array (CI-CGA). Package outline Interconnects Pitch Typical module height 1.27 3.84
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Mechanical Dimensions CICGA Package
Figure provides mechanical dimensions bottom surface nomenclature CBGA package.
Figure Mechanical Dimensions Bottom Surface Nomenclature CI-CGA Package
Notes: Dimensioning tolerancing ASME Y14.5M-1994. Controlling dimension: millimeter.
Millimeters 21.000 21.000 3.84 0.790 0.990 1.270 1.545 1.695 0.635 5.000 16.000 5.000 16.000 3.02 0.10 0.25 0.35
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Clock Relationships Choice
603r microprocessors offer customers numerous clocking options. internal phase-lock loop synchronizes processor (CPU) clock system clock (SYSCLK) various ratios. Inside each PowerPC microprocessor phase-lock loop circuit. voltage controlled oscillator (VCO) precisely controlled frequency phase frequency/phase detector which compares input frequency (SYSCLK frequency) submultiple VCO. ratio SYSCLK frequencies often referred mode (for example, mode). Table horizontal scale represents frequency (SYSCLK) vertical scale represents PLL-CFG[0-3] signals. given SYSCLK (bus) frequency, configuration signals internal frequency operation. Table Frequencies Common Frequencies Multipliers
Frequency (VCO Frequency MHz) Bus-toCore Multiplier 2.5x 3.5x 4.5x 5.5x Core-to Multiplier (300) 33.33 (300) (333) (366) (400) (320) (360) (400) (440) (480) bypass Clock (300) (350) (400) (450) (500) (550) (600) (300) (360) (420) (480) (540) (600) 66.67 (333) (400) (466) (533) (600) (300) (375) (450) (525) (600)
PLL_CFG[0-3] 0100 0101 0110 1000 1110 1010 0111 1011 1001 1101 0011 1111 Notes:
Some configurations select bus, frequencies which supported PLL-bypass mode, SYSCLK input signal clocks internal processor directly, disabled, mode mode operation. This mode intended factory only. Note: timing specifications given this document apply PLL-bypass mode. clock-off mode, clocking occurs inside 603e regardless SYSCLK input.
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System Design Information
Power Supply Filtering power signal provided 603e provide power clock generation phase-locked loop. ensure stability internal clock, power supplied AVdd input signal should filtered using circuit similar shown Figure circuit should placed close AVdd ensure filters much noise possible. capacitor should closest AVdd pin, followed capacitor, finally resistor Vdd. These traces should kept short direct. Figure Power Supply Filter Circuit
AVdd
Decoupling Recommendations
603e's dynamic power management feature, large address data buses, high operating frequencies, 603e generate transient power surges high frequency noise power supply, especially while driving large capacitive loads. This noise must prevented from reaching other components 603e system, 603e itself requires clean, tightly regulated source power. Therefore, recommended that system designer place least decoupling capacitor each OVdd 603e. also recommended that these decoupling capacitors receive their power from separate Vdd, OVdd, power planes PCB, utilizing short traces minimize inductance. These capacitors should vary value from provide both high-and low-frequency filtering, should placed close possible their associated OVdd pin. Suggested values pins (ceramic), 0,01 (ceramic) (ceramic). Suggested values OVdd pins 0,01 (ceramic), (ceramic), (tantalum). Only (surface mount technology) capacitors should used minimize lead inductance. addition, recommended that there several bulk storage capacitors distributed around PCB, feeding OVdd planes, enable quick recharging smaller chip capacitors. These bulk capacitors should also have (equivalent series resistance) rating ensure quick response time necessary. They should also connected power ground planes through vias minimize inductance. Suggested bulk capacitors (AVX tantalum) (AVX tantalum).
Connection Recommendations
ensure reliable operation, highly recommended connect unused inputs appropriate signal level. Unused active inputs should tied Vdd. Unused active high inputs should connected GND. (no-connect) signals must remain unconnected. Power ground connections must made external Vdd, OVdd, pins 603e.
Pull-up Resistor Requirements
603e requires high-resistive (weak: pull-up resistors several control signals interface maintain control signals negated state after they have been actively negated released 603e other master. These signals are: ABB, DBB, ARTRY.
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addition, 603e three open-drain style outputs that require pull-up resistors (weak stronger: they used system. These signals are: APE, DPE, CKSTP_OUT. During inactive periods bus, address transfer attributes driven master float high-impedance state relatively long periods time. Since 603e must continually monitor these signals snooping, this float condition cause excessive power draw input revivers 603e. recommended that these signals pulled trough weak pull-up resistors restored some manner system. snooped address transfer attribute inputs are: A[0-3], AP[0-3], TT[0-4], TBST, GBL. data input receivers normally turned when read operation progress require pull-up resistors data bus.
Ordering Information
PC603R Revision level divider confirmed)
Prefix Prototype Type Temperature range -55, +125°C -40, 10°C
internal processor speed
Package CBGA CI-CGA
Screening level B/Q:
Note:
Standard MIL-STD-883, class according MIL-STD-883 Upscreening Upscreening burn-in
availability different versions, contact your ATMEL-Grenoble sales office.
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