8-bit Gsps TS8388BF Radiation tolerance oriented design (150

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8-bit Gsps TS8388BF Radiation tolerance oriented design (150

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8-bit resolution. gain adjust. full power input bandwidth. Gsps (min) sampling rate. SINAD 44.3 (7.2 Effective Bits) SFDR Gsps, SINAD 42.9 (7.0 Effective Bits) SFDR Gsps, SINAD 40.3dB (6.8 Effective Bits) SFDR Gsps, 1000 2-tone -52dBc (489 MHz, MHz) 1GSPS. LSB. Error Rate (10-13 Gsps Very input capacitance mVpp differential single-ended analog inputs. Differential single-ended compatible clock inputs. LVDS/HSTL output compatibility. Data ready output with asynchronous reset. Gray Binary selectable output data output mode. Power consumption 70°C typical
8-bit Gsps
TS8388BF
Radiation tolerance oriented design (150 Krad (Si) measured).
APPLICATIONS
Digital Sampling Oscilloscopes. Satellite receiver. Electronic countermeasures Electronic warfare. Direct down-conversion.
form JTS8388B Evaluation board TSEV8388BF Demultiplexer TS81102G0 companion device available
SCREENING
Atmel-Grenoble standard screening level Mil-PRF-38535, level package version, DSCC 5962-0050401QYC Temperature range: -55°C +125°C
DESCRIPTION
TS8388BF monolithic 8-bit analog-to-digital converter, designed digitizing wide bandwidth analog signals very high sampling rates Gsps. TS8388BF using innovative architecture, including chip Sample Hold (S/H), fabricated with advanced high speed bipolar process. on-chip full power input bandwidth, providing excellent dynamic performance undersampling applications (High digitizing).
January 2002
Suffix CQFP Ceramic Quad Flat Pack
Product Specification
Product Specification
TABLE CONTENTS
SIMPLIFIED BLOCK DIAGRAM FUNCTIONAL DESCRIPTION SPECIFICATIONS
3.1. 3.2. 3.3. 3.4. 3.5. 3.6. 3.7. ABSOLUTE MAXIMUM RATINGS (SEE NOTES BELOW) RECOMMENDED CONDITIONS ELECTRICAL OPERATING CHARACTERISTICS.5 TIMING DIAGRAMS EXPLANATION TEST LEVELS. FUNCTIONS DESCRIPTION. DIGITAL OUTPUT CODING TS8388BF DESCRIPTION. TS8388BF PINOUT OUTLINE DIMENSIONS PINS CQFP THERMAL CHARACTERISTICS STATIC LINEARITY MSPS EFFECTIVE NUMBER BITS VERSUS POWER SUPPLIES VARIATION. TYPICAL RESULTS SPURIOUS FREE DYNAMIC RANGE VERSUS INPUT AMPLITUDE DYNAMIC PERFORMANCE VERSUS ANALOG INPUT FREQUENCY EFFECTIVE NUMBER BITS (ENOB) VERSUS SAMPLING FREQUENCY SFDR VERSUS SAMPLING FREQUENCY TS8388BF PERFORMANCES VERSUS JUNCTION TEMPERATURE TYPICAL FULL POWER INPUT BANDWIDTH STEP RESPONSE.
PACKAGE DESCRIPTION.
4.1. 4.2. 4.3. 4.4.
TYPICAL CHARACTERIZATION RESULTS
5.1. 5.2. 5.3. 5.4. 5.5. 5.6. 5.7. 5.8. 5.9. 5.10.
DEFINITION TERMS TS8388BF MAIN FEATURES.26
7.1. 7.2. 7.3. 7.4. 7.5. 7.6. 7.7. 7.8. 7.9. 7.10. TIMING INFORMATIONS PRINCIPLE DATA READY SIGNAL CONTROL DRRB INPUT COMMAND ANALOG INPUTS (VIN) (VINB) CLOCK INPUTS (CLK) (CLKB). NOISE IMMUNITY INFORMATIONS DIGITAL OUTPUTS RANGE GRAY BINARY OUTPUT DATA FORMAT SELECT DIODE GAIN CONTROL
EQUIVALENT INPUT OUTPUT SCHEMATICS
8.1. EQUIVALENT ANALOG INPUT CIRCUIT PROTECTIONS. 8.2. EQUIVALENT ANALOG CLOCK INPUT CIRCUIT PROTECTIONS. 8.3. EQUIVALENT DATA OUTPUT BUFFER CIRCUIT PROTECTIONS GAIN ADJUST EQUIVALENT INPUT CIRCUITS PROTECTIONS. 8.5. GORB EQUIVALENT INPUT SCHEMATIC PROTECTIONS. DRRB EQUIVALENT INPUT SCHEMATIC PROTECTIONS
TSEV8388BF DEVICE EVALUATION BOARD ORDERING INFORMATION
PACKAGE DEVICE 10.2. EVALUATION BOARD
TS8388BF
TS8388BF
SIMPLIFIED BLOCK DIAGRAM
GAIN
MASTER/SLAVE TRACK HOLD VIN,VINB RESISTOR CHAIN ANALOG ENCODING BLOCK INTERPOLATION STAGES
REGENERATION LATCHES ERROR CORRECTION DECODE LOGIC CLK, CLKB CLOCK BUFFER OUTPUT LATCHES BUFFERS DRRB DR,DRB GORB DATA,DATAB OR,ORB
FUNCTIONAL DESCRIPTION
TS8388BF 1GSPS based advanced high speed bipolar technology featuring cutoff frequency GHz. TS8388BF includes front-end master/slave Track Hold stage (S/H), followed analog encoding stage interpolation circuitry. Successive banks latches regenerating analog residues into logical data before entering error correction circuitry resynchronization stage followed differential output buffers. TS8388BF works fully differential mode from analog inputs digital outputs. TS8388BF features full power input bandwidth GHz. Control GORB provided select either Gray Binary data output format. Gain control provided order adjust gain. Data Ready output asynchronous reset (DRRB) available TS8388BF. TS8388BF uses only vertical isolated transistors together with oxide isolated polysilicon resistors, which allow enhanced radiation tolerance performance drift measured 150kRad total dose).
Product Specification
Product Specification
SPECIFICATIONS
3.1. ABSOLUTE MAXIMUM RATINGS (SEE NOTES BELOW)
Parameter Positive supply voltage Digital negative supply voltage Digital positive supply voltage Negative supply voltage Maximum difference between negative supply voltages Analog input voltages Maximum difference between VINB Digital input voltage Digital input voltage Digital output voltage Clock input voltage Maximum difference between VCLK VCLKB Maximum junction temperature Storage temperature Lead temperature (soldering 10s) Notes Symbol DVEE VPLUSD DVEE Comments Value -5.7 GND-0.3 Unit
VINB VINB VCLK VCLKB VCLK VCLKB Tstg Tleads GORB DRRB
-0.3 +0.3 -0.3 +0.9 VPLUSD-3 VPLUSD -0.5 +1.5 +135 +150 +300
Absolute maximum ratings limiting values (referenced GND=0V), applied individually, while other parameters within specified operating conditions. Long exposure maximum rating affect device reliability. thermal heat sink mandatory (see Thermal characteristics).
3.2. RECOMMENDED CONDITIONS
Parameter Positive supply voltage Positive digital supply voltage Symbol VPLUSD VPLUSD Negative supply voltages Differential analog input voltage (Full Scale) Clock input power level Operating temperature range VEE, DVEE VIN, VINB -VINB PCLK PCLKB single-ended clock input Commercial grade: Industrial grade: Military grade: differential single-ended output compatibility LVDS output compatibility +1.4 -5.25 ±113 Comments Min. 4.75 Typ. +2.4 -5.0 ±125 110° +125 +2.6 -4.75 ±137 Max. 5.25 Unit mVpp
TS8388BF
TS8388BF
3.3. ELECTRICAL OPERATING CHARACTERISTICS
DVEE -VINB mVpp Full Scale differential input Digital outputs differentially terminated (typical) 70°C. Full Temperature Range -55°C<Tc; Tj<+125°C.
Parameter
Symb
Test level
Unit
POWER REQUIREMENTS Positive supply voltage Analog Digital (ECL) Digital (LVDS) Positive supply current Analog Digital Negative supply voltage Negative supply current Analog Digital Nominal power dissipation Power supply rejection ratio RESOLUTION ANALOG INPUTS Full Scale Input Voltage range (differential mode) Volt common mode voltage Full Scale Input Voltage range (single-ended input option (see Application Notes) Analog input capacitance Input bias current Input Resistance Full Power input Bandwidth Small Signal input Bandwidth full scale) CLOCK INPUTS Logic compatibility clock inputs (see Application Notes) Clock inputs voltages (VCLK VCLKB) Logic voltage Logic voltage Logic current Logic current -1.1 into CCLK (note -1.5 specified clock input power level VINB VINB FPBW SSBW -125 -125 -250 (note VPLUSD VPLUSD IPLUSD AIEE DIEE PSRR -5.3 -4.7 mV/V bits
Clock input power level into termination Clock input power level Clock input capacitance
Product Specification
Product Specification
Parameter
Symb
Test level
Unit
DIGITAL OUTPUTS (notes 1,6) Single ended differential input mode, clock duty cycle (CLK,CLKB), Binary output data format, (typical) 70°C. Logic compatibility digital outputs Depending value VPLUSD (see Application Notes) Differential output voltage swings assuming VPLUSD open transmission lines levels differentially terminated differentially terminated Output levels assuming VPLUSD open transmission lines Logic voltage Logic voltage (note (note Logic voltage Differential Output Swing Output level drift with temperature ACCURACY Single ended differential input mode, clock duty cycle (CLK,CLKB), Binary output data format, (typical) 70°C. Differential linearity (notes 2,3) DNLDNL+ Integral linearity (notes 2,3) INLINL+ missing codes Gain error (note -1.0 -1.2 -0.5 -0.6 -0.25 -0.35 -1.16 -1.25 -1.40 -1.40 -1.10 -1.10 -1.32 -1.25 mV/°C -1.07 -1.41 -1.34 (note -0.88 -1.62 -0.8 -1.54 1.50 0.70 0.54 1.620 0.825 0.660 LVDS
Output levels assuming VPLUSD differentially terminated Logic voltage Logic voltage
Output levels assuming VPLUSD differentially terminated Logic voltage
Guaranteed over specified temperature range ppm/°C ppm/°C
Input offset voltage Gain error drift Offset error drift
TS8388BF
TS8388BF
Parameter Symb Test level Unit
TRANSIENT PERFORMANCE Error Rate Gsps 62.5 (note (note (notes 1E-12 Error/ sample
settling time -VinB mVpp Overvoltage recovery time PERFORMANCE
Single ended differential input clock mode, clock duty cycle (CLK,CLKB), Binary output data format, 70°C, unless otherwise specified. Signal Noise Distortion ratio Gsps Gsps Gsps 1000 (-1dB (note SINAD ENOB (note (note (note SFDR (note Bits Bits Bits Bits
Msps Effective Number bits Gsps Gsps Gsps 1000 (-1dBFs)
Msps Signal Noise Ratio Gsps Gsps Gsps 1000 (-1dBFs)
Msps Total Harmonic Distortion Gsps Gsps Gsps 1000 (-1dBFs)
Msps Spurious Free Dynamic Range Gsps Gsps Gsps Gsps 1000 (-1dBFs) 1000 (-3dBFs)
Msps Two-tone inter-modulation distortion FIN1 Gsps FIN2 Gsps
Product Specification
Product Specification
Parameter Symb Test level Unit
SWITCHING PERFORMANCE CHARACTERISTICS Timing Diagrams Figure Figure Maximum clock frequency Minimum clock frequency Minimum Clock pulse width (high) Minimum Clock pulse width (low) Aperture delay Aperture uncertainty Data output delay (Note (Notes (Notes (Note (Note Jitter TR/TF TR/TF 1150 0.280 0.350 0.500 0.500 +250 1360 1660 Gsps Msps (rms)
Output rise/fall time DATA (note Output rise/fall time DATA READY Data ready output delay Data ready reset delay Data data ready clock pulse width (See timing diagram, notes 13,14) Data data ready output delay (50% duty cycle) (See timing diagram, notes 1Gsps Data pipeline delay (note (Notes 2,10,
TRDR TODTDR
1110
1320
1620 1000
clock cycles
Note Note Note Note Note
Differential output buffers internally loaded resistors. Buffer bias current definition terms Histogram testing based sampling sinewave MSPS. Output error amplitude around worst code. Maximum jitter value obtained single-ended clock input JTS8388B (chip board) (500 expected TS8388BG)
Note Digital output back termination options depicted Application Notes figures 3,4,5 Note With typical value Gsps, timing safety margin data storing using ECLinPS 10E452 output registers from Motorola equally shared before after rising edge Data Ready signals (DR, DRB). Note clock inputs indifferently entered differential single-ended, using levels typical power level into termination resistor inphase clock input. into clock input correspond power level clock generator.) Note 1GSPS, 50/50 clock duty cycle, (TC1). -100 (typ) does depend sampling rate. Note Specified loading conditions digital outputs controlled impedance traces properly terminated, unterminated controlled impedance traces. Controlled impedance traces loaded standard ECLinPS register from Motorola.( e.g. 10E452 Typical input parasitic capacitance including package protections. Note Termination load parasitic capacitance derating values controlled impedance traces properly terminated additionnal ECLinPS load. Unterminated source terminated controlled impedance lines additionnal ECLinPS termination load. Note apply proper impedance traces propagation time derating values (155 ps/inch) TSEV8388BF Evaluation Board. Note Values track each other over temperature, variation temperature variation Therefore variation over temperature negligible. Moreover, internal onchip package skews between each Data TODs effect considered negligible.Consequently, minimum values never more than apart. same true maximum values (see Advanced Application Notes about variation over temperature section Note value guarantees performance. value guarantees functionality. Note value guarantees functionality. value guarantees performance.
TS8388BF
TS8388BF
3.4. TIMING DIAGRAMS
(VIN, VINB
TC=1000
(CLK, CLKB)
1360 TPD: Clock periods 1360
DIGITAL OUTPUTS
1000
DATA
DATA
1320
DATA
DATA
DATA
DATA
DATA
1320
Data Ready (DR, DRB)
TD1=TC1+TDR-TOD TC1-40
TRDR
TC2+TOD-TDR TC2+40ps
DRRB
(min)
Figure TS8388BF TIMING DIAGRAM GSPS CLOCK RATE Data Ready Reset Clock held level
250ps
(VIN, VINB
1000
(CLK, CLKB)
DIGITAL OUTPUTS
1360 1000
TPD: Clock periods
1360
DATA
DATA
1120
DATA
DATA
DATA
DATA
DATA
1320
TD1=TC1+TDR-TOD TC1-40
Data Ready (DR, DRB)
TC2+TOD-TDR TC2+40ps
TRDR 720ps
DRRB
(min)
Figure TS8388BF TIMING DIAGRAM GSPS CLOCK RATE Data Ready Reset Clock held HIGH level
Product Specification
Product Specification
3.5. EXPLANATION TEST LEVELS
100% production tested +25°C (for Temperature range production tested +25°C (1), sample tested specified temperatures (for Temperature ranges Sample tested only specified temperatures Parameter guaranteed design characterization testing (thermal steady-state conditions specified temperature). Parameter typical value only production tested over specified temperature range (for "B/Q" Temperature range
Only values guaranteed (typical values issuing from characterization results).
Unless otherwise specified, tests pulsed tests therefore where junction, case ambient temperature respectively. Refer ORDERING INFORMATION chapter.
3.6. FUNCTIONS DESCRIPTION
Name VPLUSD VIN, VINB CLK, CLKB <D0:D7> <D0B:D7B> GAIN GORB DIOD/DRRB Function Positive power supply Analog negative power supply Digital positive power supply Ground Differential analog inputs Differential clock inputs Differential output data port Differential data ready outputs range outputs gain adjust Gray Binary digital output select junction temp. measurement/ asynchronous data ready reset DVEE=-5V VEE=-5V
VPLUSD (ECL) VPLUSD=+2.4V (LVDS)
VINB CLKB GAIN GORB
TS8388BF
DIOD/
DRRB
3.7. DIGITAL OUTPUT CODING
(Non Return Zero) mode, ideal coding does include gain, offset, linearity voltage errors. Differential analog input Binary GORB floating +251 +251 +249 +126 +124 -124 -126 -249 -251 -251 Positive full scale Positive full scale Positive full scale Positive scale Positive1/2 scale Bipolar zero Bipolar zero Negative scale Negative scale Negative full scale Negative full scale Negative full scale Gray GORB Voltage level Digital output Range
TS8388BF
TS8388BF
PACKAGE DESCRIPTION.
4.1. TS8388BF DESCRIPTION
Symbol number Function Ground pins. connected external ground plane. Digital positive supply. compatibility, +2.4V LVDS compatibility). (note positive supply. analog negative supply. digital negative supply. phase analog input signal Sample Hold differential preamplifier. Inverted phase analog input signal (VIN). phase clock input signal. analog input sampled held rising edge signal. Inverted phase clock input signal (CLK). phase digital outputs. LSB. MSB. Inverted phase Digital outputs. inverted LSB. inverted MSB. phase Range Bit. Range high leading edge code code 256. Inverted phase Range (OR). phase output Data Ready Signal. Inverted phase output Data Ready Signal (DR). Gray Binary select output format control pin. Binary output format GORB floating VCC. Gray output format GORB connected ground gain adjust pin. This double function (can left open grounded used) DIOD junction temperature monitoring pin. DRRB asynchronous data ready reset function
VPLUSD
DVEE
54(1), 57(1) 40(1)
VINB CLKB D0B, D1B, D2B, D3B, D4B, D5B, D6B, GORB
GAIN DIOD/DRRB
Note Note
Following numbers (CLK), (CLKB), (VIN) (VINB) have connected through resistor close possible package.(50 termination preferred option). common mode level output buffers 1.2V below positive digital supply. compatibility positive digital supply must (ground LVDS compatibility (output common mode +1.2V) positive digital supply must 2.4V. subsequent LVDS circuitry withstand lower level input common mode, recommended lower positive digital supply level same proportion order spare power dissipation.
Product Specification
Product Specification
4.2. TS8388BF PINOUT
VIEW
VPLUSD VPLUSD
VPLUSD
VPLUSD
VPLUSD
VPLUSD
TS8388BF
TS8388BF
TS8388BF
4.3. OUTLINE DIMENSIONS PINS CQFP
pins Ceramic Quad Flat Pack view
20.32 .023 .002 0.58 0.05 .950 .006 24.13 0.152 1.133 1.147 28.78 29.13 .005 index 0.050 1.27
CQFP
.950 .006 24.13 0.152 1.133 1.147 28,78 29.13 .135 3.43 .075 .008 0.20
.004
.018 .035 0.46 0.88 .027 .037 0.70 0.95
.005 .010 0.13 0.25
Product Specification
Product Specification
4.4. THERMAL CHARACTERISTICS
Although power dissipation this performance, heat sink mandatory. will find here below some advise this topics. 4.4.1. THERMAL RESISTANCE FROM JUNCTION AMBIENT RTHJA
following table lists converter thermal performance parameters, with without heatsink. following measurements, heatsink been used. (see drawing part 4.4.3.)
thermal resistance CQFP68 board flow (m/s) Estimated Without heatsink 23,5 Targeted With heatsink
Rthja (deg/W) With heatsink Without heatsink
Heatsink glued backside package screwed pressed with thermal grease
flow (m/s)
4.4.2.
THERMAL RESISTANCE FROM JUNCTION CASE RTHJC
Typical value Rthjc given 4.75 oC/W. 4.4.3. CQFP68 BOARD ASSEMBLY WITH EXTERNAL HEATSINK
28.96 24.13 Printed circuit
Aluminum heatsink
15.0 Interface Af-filled epoxy thermal conductive grease max.
16.0
50.0
TS8388BF
TS8388BF
TYPICAL CHARACTERIZATION RESULTS
5.1. STATIC LINEARITY MSPS
5.1.1. INTEGRAL LINEARITY
code
Clock Frequency 50Msps Positive peak 0.78 Signal Frequency 10MHz Negative peak -0.73
5.1.2.
DIFFERENTIAL LINEARITY
code
Clock Frequency 50Msps Positive peak
Signal Frequency 10MHz Negative peak -0.39
Product Specification
Product Specification
5.2. EFFECTIVE NUMBER BITS VERSUS POWER SUPPLIES VARIATION
Effective number bits (VEEA) MSPS
ENOB (bits)
-6,5 -5,5 -4,5
VEEA
Effective number bits (VCC) MSPS
ENOB (bits)
Effective number bits (VEED) MSPS
ENOB (bits)
-5,5 -4,5 -3,5
VEED
TS8388BF
TS8388BF
5.3. TYPICAL RESULTS
5.3.1 GSPS, FIN=20 Single Ended differential GSPS Eff. Bits =7.2 SINAD 44.3 44.7dB -54dBc SFDR
Binary output coding clock duty cycle
5.3.2.
GSPS,
Single Ended differential GSPS Fin=495MHz Eff. Bits =6.8 SINAD 44.1 SFDR= Binary output coding clock duty cycle
5.3.3.
GSPS, -3DB FULL SCALE INPUT)
Single Ended differential GSPS Fin=995 Eff. Bits =6.6 SINAD =40.8 SFDR= Binary output coding clock duty cycle
Product Specification
Product Specification
5.4. SPURIOUS FREE DYNAMIC RANGE VERSUS INPUT AMPLITUDE
5.4.1. SAMPLING FREQUENCY FS=1 GSPS INPUT FREQUENCY FIN=995 GRAY BINARY OUTPUT CODING
Full Scale
SFDR
magnitude (code)
GSPS ENOB SINAD
44dB
Full Scale SFDR
-3dB Full Scale
SFDR magnitude (code)
GSPS ENOB SINAD 40.8
44dB
Full Scale) -48dBc SFDR -50dBc
TS8388BF
TS8388BF
5.5. DYNAMIC PERFORMANCE VERSUS ANALOG INPUT FREQUENCY
Fs=1 Gsps, 1600 MHz, Full Scale input (FS), Clock duty cycle Binary/Gray output coding, fully differential single-ended analog clock inputs
1000 1200 1400 1600 1800
ENOB (dB)
Input frequency (MHz)
(dB) 1000 1200 1400 1600 1800
Input frequency (MHz)
SFDR (dBc) 1000 1200 1400 1600 1800
Input frequency (MHz)
Product Specification
Product Specification
5.6. EFFECTIVE NUMBER BITS (ENOB) VERSUS SAMPLING FREQUENCY
Analog Input Frequency Nyquist conditions Clock duty cycle Binary output coding
n=500
ENOB (dB)
1000 1200 1400 1600
Sampling frequency (Msps)
5.7. SFDR VERSUS SAMPLING FREQUENCY
Analog Input Frequency Nyquist conditions Clock duty cycle Binary output coding
SFDR (dBc)
Fin= FS/2
Fin=500
1000 1200 1400 1600
Sampling frequency (Msps)
TS8388BF
TS8388BF
5.8. TS8388BF PERFORMANCES VERSUS JUNCTION TEMPERATURE
Effective number bits versus junction temperature GSPS Duty cycle
ENOB (bits)
Temperature
Signal noise ratio versus junction temperature GSPS Differential clock, Single-ended analog input (Vin=-1dBFs)
(dB)
Temperature
Total harmonic distorsion versus junction temperature GSPS Differential clock, Single-ended analog input (Vin=-1dBFs) (dB)
Temperature
Product Specification
Product Specification
Power consumption versus junction temperature cycl Power consumption
5.9. TYPICAL FULL POWER INPUT BANDWIDTH
(-2dBm full power input)
Frequency (MHz)
1100
1300
1500
1700
Magnitude (dB)
TS8388BF
TS8388BF
5.10. STEP RESPONSE
Test pulse input characteristics input full scale rise time 200ps. Note This step response obtained with TSEV8388B chip board (device form). 5.10.1. TEST PULSE DIGITIZED WITH
mV/div mV/div ps/div
time (ns)
5.10.2. SAME TEST PULSE DIGITIZED WITH TS8388BF
code
codes/div (Vpp ~260 ps/div calculated rise time between
time (ns)
N.B. ripples test setup (they present both measurements)
Product Specification
Product Specification
DEFINITION TERMS
(BER) (BW)
Error Rate Full power input bandwidth Signal noise distortion ratio Signal noise ratio Total harmonic distorsion Spurious free dynamic range
Probability exceed specified error threshold sample. error code code that differs more than from correct code. Analog input frequency which fundamental component digitally reconstructed output fallen with respect frequency value (determined analysis) input Full Scale. Ratio expressed signal amplitude, below Full Scale, other spectral components, including harmonics except Ratio expressed signal amplitude, below Full Scale, other spectral components excluding five first harmonics. Ratio expressed first five harmonic components, value measured fundamental spectral component. Ratio expressed signal amplitude, below Full Scale, value next highest spectral component (peak spurious spectral component). SFDR parameter selecting converter used frequency domain application Radar systems, digital receiver, network analyzer reported (i.e., degrades signal levels lowered), Dbfs (i.e. always related back converter full scale). SINAD 1.76 (A/V/2) Where actual input amplitude ENOB full scale range under test 6.02 Differential Linearity output code difference between measured step size code ideal step size. expressed LSBs. maximum value (i). error specification less than guarantees that there missing output codes that transfer function monotonic. Integral Linearity output code difference between measured input voltage which transition occurs ideal value this transition. expressed LSBs, maximum value |INL (i)|. peak gain variation percent) five different levels signal Full Scale peak peak amplitude. MHz. (TBC) Peak Phase variation degrees) five different levels signal Full Scale peak peak amplitude. MHz. (TBC) Delay between rising edge differential clock inputs (CLK,CLKB) (zero crossing point), time which (VIN,VINB) sampled. Sample sample variation aperture delay. voltage error jitter depends slew rate signal sampling point. Time delay achieve accuracy converter output when Full Scale step function applied differential analog input. Time recover accuracy output, after full scale step applied input reduced midscale. Delay from falling edge differential clock inputs (CLK,CLKB) (zero crossing point) next point change differential output data (zero crossing) with specified load. Time delay from Data transition Data ready. General expression with encoding clock period. Minimum clock pulse width (high) Minimum clock pulse width (low) Number clock cycles between sampling edge input data associated output data being made available, (not taking account TOD). TS8388BF clock periods. Delay between falling edge Data Ready output asynchronous Reset signal (DDRB) reset digital zero transition Data Ready output signal (DR). Time delay output DATA signals rize from delta between level
(SINAD) (SNR) (THD) (SFDR)
(ENOB) (DNL)
Effective Number Bits Differential linearity
(INL)
Integral linearity
(DG) (DP) (TA) (JITTER) (TS) (ORT) (TOD) (TD1) (TD2) (TC) (TPD)
Differential gain Differential phase Aperture delay Aperture uncertainty Settling time Overvoltage recovery time Digital data Output delay Time delay from Data Data Ready Time delay from Data Ready Data Encoding clock period Pipeline Delay
(TRDR) (TR)
Data Ready reset delay Rise time
TS8388BF
TS8388BF
high level. (TF) (PSRR) (NRZ) Fall time Power supply rejection ratio return zero Time delay output DATA signals fall from delta between level high level. Ratio input offset variation change power supply voltage. When input signal larger than upper bound input range, output code identical maximum code Range logic one. When input signal smaller than lower bound input range, output code identical minimum code, range logic one. assumed that input signal amplitude remains within absolute maximum ratings).
(IMD) (NPR)
InterModulation Distortion tones intermodulation distortion rejection ratio either input tone worst third order intermodulation products. input tones levels Full Scale. Noise Power Ratio measured characterize performance response broad bandwidth signals. When using notch-filtered broadband white-noise generator input under test, Noise Power Ratio defined ratio average out-of-notch average in-notch power spectral density magnitudes spectrum output sample test.
Product Specification
Product Specification
7.1.
7.1.1.
TS8388BF TIMING INFORMATIONS
TIMING VALUE TS8388BF
Timing values defined advanced data, issuing from electric simulations first characterizations results fitted with measurements. Timing values given CQFP68 package inputs/outputs, taking into account package internal controlled impedance traces propagation delays, gullwing model, specified termination loads. Propagation delays 50/75 ohms impedance traces taken into account TDR. Apply proper derating values corresponding termination topology. min/max timing values valid over full temperature range following conditions Note Specified Termination Load (Differential output Data Data Ready) ohms resistor parallel with standard ECLinPS register from Motorola, (e.g 10E452) (Typical ECLinPS inputs shows typical input capacitance (including package protections) addressing output Dmux, take care some Digital outputs have same termination load apply corresponding derating value given below. Note Output Termination Load derating values ps/pF additional ECLinPS load. Note :Propagation time delay derating values have also applied ps/mm (155 ps/inch) TSEV8388B Evaluation Board. Apply proper time delay derating value different dielectric layer used. 7.1.2. PROPAGATION TIME CONSIDERATIONS
Timing values given from include additional propagation times between device pins input/output termination loads. TSEV8388B Evaluation Board, propagation time delay 6ps/mm (155ps/inch) corresponding (@10GHz) dielectric constant RO4003 used Board. different dielectric layer used (for instance Teflon), please appropriate propagation time values. does depend propagation times because differential data. time difference between Data Ready output delay digital Data output delay) also most straightforward data measure, again because differential measured directly onto termination loads, with matched Oscilloscopes probes. 7.1.3. VARIATION OVER TEMPERATURE
Values track each other over temperature percent variation degrees Celsius temperature variation). Therefore variation over temperature negligible. Moreover, internal (onchip) package skews between each Data TODs effect considered negligible. Consequently, minimum values never more than apart. same true maximum values. other terms 1150 will 1620 maximum time delay 1660 will 1110 minimum time delay However, external values dictated total digital datas skews between every TODs (each digital data) Board bonding wires output lines lengths differences, output termination impedance mismatches. external board) skew effect been taken into account specification minimum maximum values TOD-TDR. 7.1.4.
PRINCIPLE OPERATION
Analog input sampled rising edge external clock input (CLK,CLKB) after (aperture delay) typically 250ps digitized data available after clock periods latency (pipeline delay (TPD)), clock rising edge, after 1360 typical propagation delay TOD. Data Ready differential output signal frequency (DR,DRB) half external clock frequency, that switches same rate digital outputs. Data Ready output signal (DR,DRB) switches external clock falling edge after propagation delay typically 1320 Master Asynchronous Reset input command DRRB compatible single-ended input) available initializing differential Data Ready output signal DR,DRB .This feature mandatory certain applications using interleaved ADCs using single with demultiplexed outputs. Actually, without Data Ready signal initialization, impossible store output digital datas defined order.
TS8388BF
TS8388BF
7.2.
7.2.1.
PRINCIPLE DATA READY SIGNAL CONTROL DRRB INPUT COMMAND
DATA READY OUTPUT SIGNAL RESET
Data Ready signal reset falling edge DRRB input command, logical level (-1.8V). DRRB also tied Data Ready output signal Master Reset. long DRRB remains logical level, tied 5V), Data Ready output remains logical zero independant external free running encoding clock. Data Ready output signal (DR,DRB) reset logical zero after TRDR= typical. TRDR measured between -1.3V point falling edge DRRB input command zero crossing point differential Data Ready output signal (DR,DRB). Data Ready Reset command pulse minimum time width. 7.2.2. DATA READY OUTPUT SIGNAL RESTART
Data Ready output signal restarts DRRB command rising edge, logical high levels (-0.8V). DRRB also Grounded, allowed float, normal free running Data Ready output signal. Data Ready signal restart sequence depends logical level external encoding clock, DRRB rising edge instant DRRB rising edge occurs when external encoding clock input (CLK,CLKB) Data Ready output first rising edge occurs after half clock period clock falling edge, after delay time 1320 already defined hereabove. DRRB rising edge occurs when external encoding clock input (CLK,CLKB) HIGH Data Ready output first rising edge occurs after clock period clock falling edge, delay 1320ps.
Consequently, analog input sampled clock rising edge, first digitized data corresponding first acquisition after Data Ready signal restart rising edge always strobed third rising edge data ready signal. time delay (TD1) specified between last point change differential output data (zero crossing point) rising falling edge differential Data Ready signal (DR,DRB) (zero crossing point). Note normal initialization Data Ready output signal, external encoding clock signal frequency level must controlled. reminded that minimum encoding clock sampling rate MSPS consequently clock cannot stopped. Note single used both DRRB input command junction temperature monitoring. denomination will DRRB/DIOD.( former version denomination DIOD. Temperature monitoring Data Ready control DRRB possible simultaneously.
7.3.
ANALOG INPUTS (VIN) (VINB)
analog input Full Scale range Volts peak peak (Vpp), into ohms termination resistor. differential mode input configuration, that means 0.25 Volt each input, around zero volt. input common mode GROUND. typical input capacitance TS8388B CQFP package. input capacitance mainly package. Differential inputs voltage span [mV]
VINB
-250
500mV Full Scale analog input -125
Volt
(VIN,VINB) diff
Differential versus single ended analog input operation TS8388BF operate full speed either differential single ended configuration. This explained fact uses high input impedance differential preamplifier stage, (preceeding Sample hold stage), which been designed order entered either differential mode single-ended mode.
Product Specification
Product Specification
This true long phase analog input VINB ohms terminated very closely neighboring shield ground pins (52, which constitute local ground reference inphase analog input (VIN). Thus differential analog input preamplifier will fully reject local ground noise capacitively inductively coupled noise) common mode effects. typical single-ended configuration, enter (VIN) input pin, with inverted phase input (VINB) grounded through ohms termination resistor. single-ended input configuration, in-phase input amplitude Volt peak peak,centered into ohms.) inverted phase input ground potential through ohms termination resistor. However, dynamic performances somewhat improved entering either analog clock inputs differential mode. Typical Single ended analog input configuration [mV] VINB
VINB
VINB double (pins
Full Scale analog input -250
VINB
(external)
diff reverse termination
7.4.
CLOCK INPUTS (CLK) (CLKB)
TS8388BF clocked full speed without noticeable performance degradation either differential single ended configuration. This explained fact uses differential preamplifier stage clock buffer, which been designed order entered either differential single-ended mode. Recommended sinewave generator characteristics typically -120 dBc/Hz phase noise floor spectral density, from carrier assuming single tone input clock signal. 7.4.1. SINGLE ENDED CLOCK INPUT (GROUND COMMON MODE)
Although clock inputs were intended driven differentially with nominal -0.8V -1.8V levels, TS8388BF clock buffer manage single-ended sinewave clock signal centered around Volt. This most convenient clock input configuration does require power splitter. performance degradation e.g. timing jitter) observed this particular single-ended configuration 1.2GSPS Nyquist conditions This true long inverted phase clock input ohms terminated very closely neighbouring shield ground pin, which constitutes local Ground reference inphase clock input. Thus TS8388BF differential clock input buffer will fully reject local ground noise capacitively inductively coupled noise) common mode effects. Moreover, very phase noise sinewave generator must used enhanced jitter performance. typical inphase clock input amplitude Volt peak peak, centered Volt (ground) common mode. This corresponds typical clock input power level into ohms termination resistor. exceed avoid saturation preamplifier input transistors. inverted phase clock input grounded through ohms termination resistor.
TS8388BF
TS8388BF
Single ended Clock input (Ground common mode) VCLK common mode Volt VCLKB=0 Volt typical clock input power level (into ohms termination resistor) +0.5V
CLKB double (pins CLKB
VCLK
VCLKB
(external)
-0.5V
reverse termination
Note exceed into ohms termination resistor single clock input power level. 7.4.2. DIFFERENTIAL CLOCK INPUT
clock inputs driven differentially with nominal -0.8V -1.8V levels. this mode, phase noise sinewave generator used drive clock inputs, followed power splitter (hybrid junction) order obtain degrees phase sinewave signals. Biasing tees used offseting common mode voltage levels. Note biasing tees propagation times matching, tunable delay line required order ensure signals degrees phase especially fast clock rates GSPS range. Differential Clock inputs (ECL Levels) [mV] -0.8V
CLKB double (pins
VCLK
VCLKB
CLKB
Common mode -1.3
(external)
-1.8V
reverse termination
7.4.3.
SINGLE ENDED CLOCK INPUT
single-ended configuration enter resp. CLKB with inverted phase Clock input CLKB (respectively CLK) connected 1.3V through ohms termination resistor. inphase input amplitude Volt peak peak, centered -1.3 Volt common mode. Single ended Clock input (ECL): VCLK common mode -1.3 Volt. VCLKB -1.3 Volt -0.8V
VCLK
VCLKB -1.3
-1.8V
Product Specification
Product Specification
7.5. NOISE IMMUNITY INFORMATIONS
Circuit noise immunity performance begins design level. Efforts have been made design order make device insensitive possible chip environment perturbations resulting from circuit itself induced external circuitry. (Cascode stages isolation, internal damping resistors, clamps, internal (onchip) decoupling capacitors.) Furthermore, fully differential operation from analog input digital outputs provides enhanced noise immunity common mode noise rejection. Common mode noise voltage induced differential analog clock inputs will canceled these balanced differential amplifiers. Moreover, proper active signals shielding been provided chip reduce amount coupled noise active inputs analog inputs clock inputs TS8388BF device have been surrounded ground pins, which must directly connected external ground plane.
7.6.
DIGITAL OUTPUTS
TS8388BF differential output buffers internally ohms loaded. ohms resistors connected digital ground pins through -0.8v level shift diode (see Figures 3,4,5 next page). TS8388BF output buffers designed driving ohms (default) ohms properly terminated impedance lines coaxial cables. bias current flowing alternately into ohms resistors when switching ensures 0.825 voltage drop across resistor (unterminated outputs). VPLUSD positive supply voltage allows adjustment output common mode level from -1.2V (VPLUSD=0V output compatibility) +1.2V (VPLUSD=2.4V LVDS output compatibility). Therefore, single ended output voltages vary approximately between -0.8V -1.625V, outputs unterminated around -1.2V common mode voltage. Three possible line driving back-termination scenarios proposed (assuming VPLUSD=0V) Ohms impedance transmission lines, ohms differentially terminated (Fig. Each output voltage varies between -1.42V (respectively +1.4V +1V), leading 0.41V =0.825 differential, around -1.21 (respectively +1.21V) common mode VPLUSD=0V (respectively 2.4V). ohms impedance transmission lines, ohms differentially termination (Fig. Each output voltage varies between -1.02V -1.35V (respectively +1.38V +1.05V), leading 0.33V=660 differential, around 1.18V (respectively +1.21V) common mode VPLUSD=0V (respectively 2.4V). ohms impedance open transmission lines (Fig. Each output voltage varies between -1.6 -0.8 (respectively +0.8V +1.6V), which true levels, leading 0.8V=1.6V differential, around -1.2V (respectively +1.2V) common mode VPLUSD=0V (respectively 2.4V). Therefore, possible drive directly high input impedance storing registers, without terminating ohms transmission lines. time domain, that means that incident wave will reflect ohms transmission line output travel back generator i.e. ohms data output buffer buffer output impedance ohms, back reflection will occur. Note This longer true ohms transmission line used, latter matching buffer ohms output impedance. Each differential output termination length must kept identical recommended decouple midpoint differential termination with capacitor avoid common mode perturbation case slight mismatch differential output line lengths. large mismatches keep differential line lengths will lead switching currents flowing into decoupling capacitor leading switching ground noise. differential output voltage levels ohms termination standard voltage levels, however possible drive standard logic circuitry like ECLinPS logic line from MOTOROLA. sampling rates exceeding 800MSPS, difficult trigger HP16500 other Acquisition System with digital outputs. becomes necessary regenerate digital data Data Ready means external amplifiers, order able test TS8388BF optimum performance conditions.
TS8388BF
TS8388BF
7.6.1. DIFFERENTIAL OUTPUT LOADING CONFIGURATIONS (LEVELS COMPATIBILITY)
VPLUSD
-0.8V impedance
-1.41V
Differential output 0.41V 0.825V Common mode level -1.2V (-1.2V below VPLUSD level) OutB -1.41V
DVEE VPLUSD
Figure DIFFERENTIAL OUTPUT TERMINATED
-0.8V impedance
-1.02V -1.35V
Differential output 0.33V 0.660V Common mode level -1.2V (-1.2V below VPLUSD level) OutB -1.35V -1.02V
DVEE
Figure DIFFERENTIAL OUTPUT TERMINATED
VPLUSD
-0.8V impedance
-0.8V -1.6V
Differential output 0.8V 1.6V Common mode level -1.2V (-1.2V below VPLUSD level) OutB -1.6V -0.8V
DVEE
Figure DIFFERENTIAL OUTPUT OPEN LOADED
Product Specification
Product Specification
7.6.1. DIFFERENTIAL OUTPUT LOADING CONFIGURATIONS (LEVELS LVDS COMPATIBILITY) VPLUSD 2.4V
1.6V impedance
1.4V 0.99V
Differential output 0.41V 0.825V Common mode level -1.2V (-1.2V below VPLUSD level) OutB 0.99V 1.4V
DVEE
Figure DIFFERENTIAL OUTPUT TERMINATED
VPLUSD 2.4V
1.6V impedance
1.38V 1.05V
Differential output 0.33V 0.660V Common mode level -1.2V (-1.2V below VPLUSD level) OutB 1.05V 1.38V
DVEE
Figure DIFFERENTIAL OUTPUT TERMINATED
VPLUSD 2.4V
1.6V impedance
1.6V 0.8V
Differential output 0.8V 1.6V Common mode level -1.2V (-1.2V below VPLUSD level) OutB 0.8V 1.6V
DVEE
Figure DIFFERENTIAL OUTPUT OPEN LOADED
7.7.
RANGE
Range (OR,ORB) provided that goes logical high state when input exceeds positive full scale falls below negative full scale. When analog input exceeds positive full scale, digital output datas remain high logical state, with (OR,ORB) logical one. When analog input falls below negative full scale, digital outputs remain logical state, with (OR,ORB) logical again.
TS8388BF
TS8388BF
7.8. GRAY BINARY OUTPUT DATA FORMAT SELECT
TS8388BF internal regeneration latches indecision (for inputs very close latches threshold) produce errors logic encoding circuitry leading large amplitude output errors. This fact that latches regenerating internal analog residues into logical states with finite voltage gain value (Av) within given positive amount time exp((t)/) with positive feedback regeneration time constant. TS8388BF been designed reducing probability occurrence such errors approximately 10-13 (targeted TS8388BF 1GSPS). standard technique reducing amplitude such errors down +/-1 consists output digital datas Gray code format. Though TS8388BF been designed featuring Error Rate 10-13 with binary output format, possible user select between Binary Gray output data format, order reduce amplitude such errors when occurring, storing Gray output codes. Digital Datas format selection BINARY output format GORB floating VCC. GRAY output format GORB connected ground (0V).
7.9.
DIODE
single used both DRRB input command junction monitoring. denomination DRRB/DIOD. Temperature monitoring Data Ready control DRRB possible simultaneously. (See section Data Ready Reset input command). operating junction temperature must kept below145 therefore adequate cooling system diode mounted transistor measured value versus junction temperature given below. 1000 (mV) Junction temperature (deg.C)
Product Specification
Product Specification
7.10. GAIN CONTROL
gain adjustable means (input impedance parallel with 2pF) gain adjust transfer function given below 1,20 1,15 1,10 Gain 1,05 1,00 0,95 0,90 0,85 0,80 -500 -400 -300 -200 -100 Vgain (command voltage) (mV)
more information, please refer document "DEMUX ADCs APPLICATION NOTES".
TS8388BF
TS8388BF
EQUIVALENT INPUT OUTPUT SCHEMATICS
8.1. EQUIVALENT ANALOG INPUT CIRCUIT PROTECTIONS
VCC=+5V
-0.8V
VCLAMP= +2.4V
-0.8V
GND=0V
-5.8V
-5.8V
+1.65V
E21V E21V
VINB
capacitance 340fF
capacitance 340fF 5.8V
-1.55V
0.8V
VEE=-5V
Note protection equivalent capacitance
8.2. EQUIVALENT ANALOG CLOCK INPUT CIRCUIT PROTECTIONS VCC=+5V +0.8V
-5.8V -5.8V
-5.8V
GND=0V
-5.8V
-5.8V
-5.8V
capacitance 340fF
CLKB
5.8V 0.8V
5.8V
capacitance 340fF
0.8V
VEE=-5V
Note protection equivalent capacitance
Product Specification
Product Specification
8.3. EQUIVALENT DATA OUTPUT BUFFER CIRCUIT PROTECTIONS VPLUSD=0V 2.4V
-5.8V
-5.8V
capacitance
OUTB
capacitance
5.8V
5.8V
I=11mA
0.8V
-3.7V
0.8V
0.8V
0.8V
VEE=-5V
DVEE=-5V
Note protection equivalent capacitance
VEE=-5V
8.4. GAIN ADJUST EQUIVALENT INPUT CIRCUITS PROTECTIONS
VCC=+5V
-0.8 +0.8 NP1032C2 -5.8
+1.6V
0.8V capacitance 0.8V
5.8V
Note protection equivalent capacitance
VEE=-5V
TS8388BF
TS8388BF
8.5. GORB EQUIVALENT INPUT SCHEMATIC PROTECTIONS
GORB: gray binary select input; floating tied binary
VCC=+5V
-0.8V -0.8V -5.8V
GORB
capacitance 180fF
5.8V
5.8V
5.8V
VEE=-5V
GND=0V
Note protection equivalent capacitance
8.6. DRRB EQUIVALENT INPUT SCHEMATIC PROTECTIONS
VCC=+5V
Actual protection range: 6.6V above VEE, fact stress above clipped diode used monitoring
GND=0V
NP1032C2
DRRB
capacitance
-1.3V -2.6V
VEE=-5V
Note protection equivalent capacitance
Product Specification
Product Specification
TSEV8388BF DEVICE EVALUATION BOARD
complete specification, separate TSEV8388BF document.
GENERAL DESCRIPTION
TSEV8388BF Evaluation Board (EB) board which been designed order facilitate evaluation characterization TS8388BF device full power bandwidth Gsps military temperature range. high speed TS8388BF requires careful attention circuit design layout achieve optimal performance. This four metal layer board with internal ground plane adequate functions order allow quick simple evaluation TS8388BF performances over temperature range. TSEV8388BF Evaluation Board very straightforward only implements TS8388BF ADC, connectors input output accesses 2.54 pitch connector compatible with HP16500C high frequency probes. board also implements de-embedding fixture order facilitate evaluation high frequency insertion loss input microstrip lines, junction temperature measurement setting. board constituted sandwich dielectric layers, featuring insertion loss enhanced thermal characteristics operation high frequency domain extended temperature range. board dimensions board comes fully assembled tested, with TS8388BF CQFP68 package installed.
TS8388BF
TS8388BF
ORDERING INFORMATION
10.1. PACKAGE DEVICE
8388B
Manufacturer prefix Device family Temperature range 125°C 110°C 90°C
Screening level standard Mil-PRF-38535, level
Package CQFP68 gullwing
10.2. EVALUATION BOARD
8388B
with MC100EL16 digital receivers Without receivers
Prototype board
Evaluation board prefix
CQFP68 package
evaluation board delivered with includes heat sink.
Product Specification
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TS8388BF

8-bit Gsps TS8388BF Radiation tolerance oriented design (150

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