PBLK Signal Processor Electronic Cameras AD9801 FUNCTIONAL B

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PBLK Signal Processor Electronic Cameras AD9801 FUNCTIONAL B

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FEATURES 10-Bit, MSPS Converter MSPS Full-Speed Noise, Wideband Internal Voltage Reference Missing Codes Guaranteed Single Supply Operation Power CMOS: 48-Pin TQFP Package
PBLK
Signal Processor Electronic Cameras AD9801
FUNCTIONAL BLOCK DIAGRAM
CLPDM
PGACONT1 PGACONT2
ADCCLK
CLAMP CLAMP REFERENCE
TIMING GENERATOR
DOUT
AD9801
DRVDD
CMLEVEL STBY
CLPOB
ACVDD
ADVDD
DVDD
PRODUCT DESCRIPTION
PRODUCT HIGHLIGHTS
AD9801 complete signal processor developed electronic cameras. well suited both video conferencing consumer level still camera applications. signal processing chain comprised high speed CDS, variable gain 10-bit ADC. Required clamping circuitry onboard voltage reference also provided. AD9801 operates from single supply with typical power consumption AD9801 packaged space saving 48-pin thin-quad flatpack (TQFP) specified over operating temperature range +70°C.
On-Chip Input Clamp Clamp circuitry high speed correlated double sampler allow simple coupling interface sensor full MSPS conversion rate. On-Chip AD9801 includes noise, wideband amplifier with analog variable gain from 31.5 (linear dB). 10-Bit, High Speed Converter linear 10-bit capable digitizing signals full MSPS conversion rate. (Typical missing code performance guaranteed.) Power AD9801 consumes fraction power presently available multichip solutions. part's powerdown mode further enhances desirability power, battery operated applications. Digital Functionality AD9801 offers three-state digital output control. Small Package Packaged 48-pin, surface-mount thin-quad flatpack, AD9801 well suited very tight, headroom designs.
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Site: http://www.analog.com Fax: 617/326-8703 Analog Devices, Inc., 1997
AD9801-SPECIFICATIONS otherwise noted)
Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE (For Functional Operation) ACVDD ADVDD DVDD DRVDD POWER SUPPLY CURRENT ACVDD ADVDD DVDD DRVDD POWER CONSUMPTION Normal Operation Power-Down Mode MAXIMUM SHP, SHD, ADCCLK RATE Resolution Differential Nonlinearity Missing Codes ADCCLK Rate Reference Voltage Reference Bottom Voltage Input Range Maximum Input Signal Pixel Rate PGA1 Maximum Gain High Gain Medium Gain Minimum Gain CLAMP Average Black Level (During CLPOB. Only Stable Over Range
(TMIN TMAX with ACVDD 3.15 ADVDD 3.15 DVDD 3.15 DRVDD 3.15 unless
Units
3.00 3.00 3.00 3.00
3.15 3.15 3.15 3.15 39.5 14.6 0.07
3.50 3.50 3.50 3.50
Bits
GUARANTEED 1.75 1.25
31.5
test conditions: gain PGACONT1 PGACONT2 high gain PGACONT1 PGACONT2 medium gain PGACONT1 PGACONT2 minimum gain PGACONT1 PGACONT2
Specifications subject change without notice.
DIGITAL SPECIFICATIONS
Parameter LOGIC INPUTS High Level Input Voltage Level Input Voltage High Level Input Current Level Input Current Input Capacitance LOGIC OUTPUTS High Level Output Voltage Level Output Voltage
TMAX with ACVDD 3.15 ADVDD 3.15 DVDD 3.15 DRVDD 3.15 unless otherwise noted)
Symbol
Units
Specifications subject change without notice.
REV.
AD9801 TIMING SPECIFICATIONS
Parameter ADCCLK CLOCK PERIOD ADCCLK High Level Period ADCCLK Level Period SHP, Clock Period Digital Output Delay
TMAX with ACVDD 3.15 ADVDD 3.15 DVDD 3.15 DRVDD 3.15 unless otherwise noted)
55.6 24.8 24.8 55.6
27.8 27.8
Units
Digital Output Data Control
Mode1
Mode2
Digital Output Data (D9-D0) Normal Operation High Impedance
ABSOLUTE MAXIMUM RATINGS*
Parameter ADVDD ACVDD DVDD DRVDD SHP, ADCCLK, CLOB, CLPDM PGACONT1, PGACONT2 PIN, DOUT VRT, CLAMP_BIAS CCDBYP1, CCDBYP2 STBY MODE1, MODE2 DRVSS, DVSS, ACVSS, ADVSS Junction Temperature Storage Temperature Lead Temperature sec)
With Respect ADVSS, SUBST ACVSS, SUBST DVSS, DSUBST DRVSS, DSUBST DSUBST DSUBST SUBST SUBST DSUBST SUBST SUBST SUBST DSUBST SUBST SUBST, DSUBST
-0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3
DVDD DVDD ACVDD ACVDD DRVDD ADVDD ACVDD ACVDD DVDD ADVDD +0.3 +150 +150 +300
Units
Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum ratings extended periods affect device reliability.
ORDERING GUIDE
Model AD9801
Temperature +70°C
Package Description 48-Pin TQFP
Package Option* ST-48
Thin Quad Flatpack Package.
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD9801 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
REV.
AD9801
CONFIGURATION
CLAMP_BIAS PGACONT2 PGACONT1 INT_BIAS1 CCDBYP1 CCDBYP2
DVSS CLPDM CLPOB PBLK STBY DVDD ADCCLK DVSS IDENTIFIER DSUBST DRVSS
ACVDD
ACVDD
ACVDD
ACVSS
CMLEVEL INT_BIAS2 MODE2 MODE1 ADVSS ADVDD ADVDD ADVSS ADVSS SUBST
AD9801
VIEW (Not Scale)
ADVSS
(MSB)
(LSB)
2-11
Name ADVSS D0-D9 DRVDD DRVSS DSUBST DVSS ADCCLK DVDD STBY PBLK CLPOB CLPDM DVSS CCDBYP2 CCDBYP1 PGACONT1 PGACONT2 ACVSS CLAMP_BIAS ACVDD ACVDD ACVDD INT_BIAS1 CMLEVEL INT_BIAS2 MODE2 MODE1 ADVSS ADVDD ADVDD ADVSS ADVSS SUBST
Type
Description Analog Ground Digital Data Outputs Digital Driver Supply Digital Driver Ground Digital Substrate Digital Ground Sample Clock Input Digital Supply Power down (Active HIGH) Pixel Blanking (Active LOW) Black Level Restore Clamp (Active LOW) Reference Sample Clock Input Data Sample Clock Input Input Clamp (Active Low) Digital Ground Bypass (Decouple Analog Ground Through Input (Tie AC-Couple Output Through Input (See Above) Bypass (Decouple Analog Ground Through Coarse Gain Control (0.3 V-2.7 Decoupled Analog Ground Through Fine Gain Control (0.3 V-2.7 Decoupled Analog Ground Through Analog Ground Clamp Bias Level (Decouple Analog Ground Through Analog Supply Analog Supply Analog Supply Internal Bias Level (Decouple Analog Ground Through Common-Mode Level (Decouple Analog Ground Through Internal Bias Level (Decouple Analog Ground Through Test Mode Control (See Digital Output Data Control) Test Mode Control (See Digital Output Data Control) Analog Ground Analog Supply Analog Supply Analog Ground Analog Ground Substrate (Connect Analog Ground) Bottom Reference Bypass (Decouple Analog Ground Through Reference Bypass (Decouple Analog Ground Through REV.
DRVDD
AD9801
EQUIVALENT INPUT CIRCUITS
DVDD DRVDD
ACVDD
10pF
SUBST ACVSS
Figure (DIN) (PIN)
DVSS
DRVSS
ACVDD PGACONT1
Figure Pins 2-11 (DB0-DB9)
SUBST PGACONT2 ACVDD
DVDD
Figure (PGACONT1) (PGACONT2)
ACVSS
DSUBST
DVSS
5.25k SUBST ACVSS
Figure (SHP) (SHD)
DVDD ADVDD
9.3k ADVSS
Figure (CLAMP BIAS)
DSUBST
DVSS
Figure (ADCCLK)
Figure (CMLEVEL)
ACVDD
ACVDD
SUBST
ADVSS
Figure (VRT) (VRB)
SUBST
DVSS
Figure (CCDBYP2) (CCDBYP1)
REV.
AD9801
EFFECTIVE PIXEL INTERVAL BLACK LEVEL INTERVAL BLANKING INTERVAL DUMMY BLACK INTERVAL EFFECTIVE PIXEL INTERVAL
CLPOB
PBLK
CLPDM
ADCCLK
DATA
NOTE: CLPDM OVERWRITES PBLK CLAMP TIMING NEEDS ADJUSTED RELATIVE CCD'S BLACK PIXELS
Figure Typical Horizontal Interval Timing
REV.
AD9801
SIGNAL (DELAYED MATCH ACTUAL SAMPLING EDGE)
ACTUAL SAMPLING EDGE 35ns ADCCLK 35ns
DIGITAL
DATA DATA
OUTPUT LOAD 20pF
OUTPUT DELAY 15ns HOLD TIME INTERNAL CLOCK DELAY LATENCY CYCLES
Figure Timing Diagram
PRE-ADC OUTPUT LATCH
10ns
PRE-ADC OUTPUT LATCH DATA TRANSITION ADCCLK 15ns INHIBITED PERIOD ADCCLK CHANGE RISING EDGE ANYWHERE THIS PERIOD
Figure ADCCLK Timing Edge
REV.
AD9801
THEORY OPERATION Introduction
GAIN
AD9801 10-bit analog-to-digital interface cameras. block level diagram system shown Figure device includes correlated double sampler (CDS), dB-31 variable gain amplifier (PGA), black level correction loop, input clamp voltage reference. only external analog circuitry required system level emitter follower buffer between output AD9801 inputs.
CLAMP BLACK LEVEL
PGACONT1 Volts
GAIN
Figure
Figure
Correlated Double Sampling (CDS)
important high performance systems method removing several types noise. Basically, samples output taken: with signal present ("data") without ("reference"). Subtracting these samples removes noise that common-or correlated-to both. Figure shows block diagram AD9801's CDS. blocks directly driven input sampling function performed passively, without amplifiers.
FROM
shown Figure control provided through PGACONT1 PGACONT2 inputs. PGACONT1 provides coarse PGACONT2 fine (1/16) gain control.
PGACONT1 PGACONT2
PGACONT1 COURSE CONTROL PGACONT2 FINE CONTROL (1/16)
Figure
Black Level Clamping
10pF
correct processing, signal must referenced well established "black level" AD9801. edge CCD, there collection pixels that covered with metal prevent light penetration. read out, these "black pixels" provide calibration signal that used establish black level. feedback loop shown Figure closed around during calibration interval (CLPOB LOW) black level. black pixels being processed, integrator block measures difference between input level desired reference level. This difference, error, signal amplified passed block where added incoming pixel data. result this process, black pixels digitized range, taking maximum advantage available linear range system.
Figure
This implementation relies off-chip emitter follower buffer drive sampling capacitors. Only capacitor time seen input pin. AD9801 actually uses circuits "ping pong" fashion allow system more acquisition time. this way, output from blocks will valid entire clock cycle. Thus, bandwidth requirement subsequent gain stage reduced compared that single channel system. This lower bandwidth translates lower power noise.
Programmable Gain Amplifier (PGA)
CLPOB
INTEGRATOR
on-chip provides (linear gain range dB-31.5 typical gain characteristic plot shown Figure Only range from intended actual use.
Figure
REV.
AD9801
actual implementation this loop slightly more complicated shown Figure Because there separate blocks, black level feedback loops required offset voltages developed. Figure also shows additional block feedback loop labeled "RPGA."
CDS1 CDS1 CLPOB RPGA2 RPGA1 INT2 INT1
avoid problems associated with processing these transients, AD9801 includes input blanking function. When active (PBLK LOW), this function stops operation allows user disconnect inputs from buffer. input voltage exceeds supply rail more than protection diodes will turned increasing current flow into AD9801 (see Equivalent Input Circuits). Such voltage levels should externally clamped prevent device damage reliability degradation.
10-Bit Analog-to-Digital Converter (ADC)
CONTROL
Figure
RPGA uses same control inputs PGA, inverse gain. RPGA functions attenuate same factor amplifies, keeping gain bandwidth loop constant.
Input Bias Level Clamping
employs multibit pipelined architecture, which well-suited high throughput rates while being both area power efficient. multistep pipeline presents input capacitance resulting lower on-chip drive requirements. fully differential implementation used overcome headroom constraints single power supply.
Differential Reference
buffered output connected AD9801 through external coupling capacitor. bias point this coupling capacitor established during clamping (CLPDM LOW) period using "dummy clamp" loop shown Figure When closed around CDS, this loop establishes desired bias point coupling capacitor.
CLPDM INPUT CLAMP
AD9801 includes reference based differential, continuous-time bandgap cell. external bypass capacitor reduces reference drive requirements, thus lowering power dissipation. differential architecture chosen ability reject supply substrate noise. Recommended decoupling shown Figure
0.1µF 0.1µF
Figure
Internal Timing
BLACK LEVEL
Figure
Input Blanking
AD9801's on-chip timing circuitry generates clocks necessary operation blocks. user needs only synchronize clocks with waveform, other timing handled internally. ADCCLK signal used strobe output data, adjusted accommodate desired timing.
some applications, AD9801's input exposed large signals from CCD. These signals very large, relative AD9801's input range, could thus saturate on-chip circuit blocks. Recovery time from such saturation conditions could substantial.
REV.
AD9801
APPLICATION INFORMATION Generating Clock Signals
best performance, AD9801 should driven logic levels. shown Equivalent Input Circuits, logic ADCCLK will turn protection diode DVDD, increasing current flow into this pin. result, noise power dissipation will increase. clock inputs, SHD, have additional protection withstand direct levels. External clamping diodes resistor dividers used translate levels levels, lowest power dissipation achieved with logic transceiver chip. National Semiconductor's 74LVX4245 provides level shift eight clock signals, features three-state option power consumption. Philips Semiconductor Quality also manufacture similar devices.
Digitally Programmable Gain Control
PGACONT2 SHDN
PGACONT1 0.1µF
AD8402-10
Figure Digital Control
reference used. REF193 from Analog Devices features power, dropout performance, maintaining output with minimum supply when lightly loaded.
Power Grounding Recommendations
AD9801's controlled analog input voltage some applications, digital gain control preferable. Figure shows circuit using Analog Devices' AD8402 Digital Potentiometer generate control voltage. AD8402 functions individual potentiometers, with serial digital interface program position each wiper over positions. device will operate with supplies, features power-down mode reset function. keep external components minimum, ends "potentiometers" tied ground used coarse gain adjust, PGACONT1, with steps about dB/LSB. other used fine gain control, PGACONT2, capable around 0.01 steps eight bits used. outputs should filtered with larger capacitors minimize noise into PGACONT pins AD9801. disadvantage this circuit that control voltage will supply dependent. additional precision required, external used amplify VREFT (1.75 VREFB (1.25 pins AD9801 desired voltage level. These reference voltages stable over operating supply range AD9801. power, cost, rail-to-rail output amplifiers such AD820, OP150 OP196 specified operation. Alternatively, precision voltage
AD9801 should treated analog component when used system. same power supply ground plane should used pins. two-ground system, this requires that digital supply pins decoupled analog ground plane digital ground pins connected analog ground best noise performance. pins AD9801 connected system digital ground, noise capacitively couple inside AD9801 (through package parasitics) from digital circuitry analog circuitry. Separate digital supplies used, particularly slightly different driver supplies needed, digital power pins should still decoupled same point digital ground pins (analog ground plane). AD9801 digital outputs need drive substantial load, buffer should used AD9801's outputs, with buffer referenced system digital ground. some cases, when system digital noise substantial, acceptable split ground pins AD9801 separate analog digital ground planes. this done, sure connect ground pins together AD9801. further improve performance, isolating driver supply DRVDD from DVDD with ferrite bead help reduce kickback effects during major code transitions. Alternatively, damping resistors digital outputs will reduce output risetimes, reducing kickback effect.
-10-
REV.
AD9801
EVALUATION BOARD
Figure shows schematic AD9801 evaluation board. Notice common ground supply AD9801, extensive supply reference decoupling.
AVCC AVCC
AVCC AVCC TP25 PGACONT1 10µF
0.1µF 0.1µF
0.01µF
0.1µF 0.1µF
0.01µF TP24
AD707
AD707
PGACONT2 10µF
0.1µF AVSS
0.01µF
0.1µF AVSS
0.01µF
0.1µF 0.1µF 0.1µF 0.1µF PGACONT1 PGACONT2
0.1µF
0.1µF DVSS CLPDM CLPOB STBY
INT_BIAS1 ACVDD
PGACONT1
CCDBYP1
CLAMP_BIAS
PGACONT2
CCDBYP2
ACVSS
ACVDD
ACVDD
0.1µF
0.1µF
0.1µF
CMLEVEL INT_BIAS2 MODE2 MODE1 ADVSS ADVDD ADVDD ADVSS ADVSS SUBST
CLPDM CLPOB PBLK
AD9801
PBLK STBY DVDD ADCCLK DVSS DSUBST DRVSS
0.1µF
ADCCLK
(MSB) DRVDD
(LSB)
ADVSS
0.1µF
0.1µF
0.01µF HEADER
0.1µF
0.1µF
0.1µF TP27 0.1µF 22µF 0.1µF AVCC TP28 22µF 0.1µF
0.01µF
0.1µF
TP26 22µF 0.1µF AVSS
TP29
(MSB) (LSB)
ADCCLK
Figure AD9801EB Schematic
REV.
-11-
AD9801
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
48-Terminal Plastic Thin Quad Flatpack (ST-48)
0.354 (9.00) 0.276 (7.0)
0.030 (0.75) 0.018 (0.45)
0.030 (0.75) 0.057 (1.45) 0.018 (0.45) 0.053 (1.35)
SEATING PLANE VIEW
(PINS DOWN)
0.006 (0.15) 0.002 (0.05)
0.007 (0.18) 0.004 (0.09)
0.019 (0.5)
0.011 (0.27) 0.006 (0.17)
0.354 (9.00)
0.276 (7.0)
-12-
REV.
PRINTED U.S.A.
C2975-12-1/97
0.063 (1.60)

PBLK Signal Processor Electronic Cameras AD9801 FUNCTIONAL B

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