11-Bit Resolution Simultaneous Sampling Converter AD7861 2.5V REF

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11-Bit Resolution Simultaneous Sampling Converter AD7861 2.5V REF

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FEATURES 11-Bit Resolution Analog-to-Digital Converter Single-Ended Analog Inputs Input Channels Simultaneously Sampled Expansion with Multiplexed Inputs Internal Reference Conversion Time Channel User Definable Channel Sequencing Single Supply Operation Double Buffered Register Outputs 6.25 12.5 Operating Clock Range APPLICATIONS Motor Control 3-Phase Power Measurement Cellular Phones Data Acquisition GENERAL DESCRIPTION
11-Bit Resolution Simultaneous Sampling Converter AD7861
2.5V REFERENCE BUSY OUTPUT REGISTERS CLKIN AUX0 AUX1 AUX2 AUX3 CONVST RESET SGND AGND
VIN1 VIN2 VIN3
11-BIT
AD7861
DGND
AD7861 multichannel simultaneous sampling Converter (ADC) configured acquisition voltage inputs motor control solution three-phase power system. AD7861 combined with Analog Devices' 16-bit fixedpoint digital signal processor (DSP) provides cost 16-bit fixed-point microcontroller solution. input stage been designed accommodate types signals frequently found motor drives. VIN1, VIN2, VIN3 channels simultaneously sampled inputs suitable stator current acquisition. AUX0-AUX3 channels multiplexed suitable slower moving inputs such temperature voltage diode rectifier output motor control application.
PRODUCT HIGHLIGHTS Simultaneous Sampling Four Inputs
Four channel sample hold amplifier (SHA) allows phase input signals sampled simultaneously, preserving relative phase information. Sample-and-hold acquisition time conversion time channel (using 12.5 system clock).
Flexible Analog Channel Sequencing
AD7861 supports acquisition channels group. Converted channel results stored registers data read order. sampling conversion time channels three channels 11.2 four channels 14.4 (using 12.5 system clock).
Single Operation
power, digital process.
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Analog Devices, Inc., 1995 Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD7861-SPECIFICATIONS unless otherwise noted)
Parameter ACCURACY Resolution Relative Accuracy Differential Nonlinearity Bias Offset Error Bias Offset Error Match Full-Scale Error Full-Scale Error Match DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Peak Harmonic Spurious Noise Channel-to-Channel Isolation REFERENCE Input Voltage Range (REF Input Current Onboard Reference Output (REF OUT) Reference Tolerance Reference Drive Capability SAMPLE-AND-HOLD Acquisition Time Aperture Delay Time Aperture Delay Time Match Droop Rate LOGIC Input High Voltage (VIH) Input Voltage (VIL) Input Leakage Current Input Capacitance (VOH) (VOL) Three-State Leakage Current CONVERSION RATE Conversion Time/Channel CONVST Pulse Width ANALOG INPUTS Nominal Input Level Input Current Input Capacitance SYSTEM CLOCK POWER REQUIREMENTS AD7861AP Units 6.25-12.5 Bits mV/ms Cycles
(VDD
REFIN 12.5 MHz,
Conditions/Comments Twos Complement Data Format Integral Nonlinearity Missing Codes Guaranteed Channel Between Channels Channel Between Channels Sine Wave, fSAMPLE Sine Wave, fSAMPLE Sine Wave, fSAMPLE Sine Wave Applied Unselected Channels Sine Wave Applied Unselected Channels
Cycles 12.5
ISOURCE Current ISINK Current
Cycles VIN1, VIN2, VIN3, AUX0-AUX3
REV.
AD7861
Table AD7861 Timing Parameters +85°C unless otherwise noted)
Number Symbol tsucsb_rdb tsuaddr_rdb tdlyrdb_data tpwlrdb tpwhrdb thdrdb_data thdrdb_addr thdrdb_csb tperclk tpwhclk tpwlclk tpwlresetb AD7861 Timing Requirements Before Falling Edge ADDR Valid Before Falling Edge DATA Valid After Falling Edge Pulse Width, Pulse Width, High DATA Hold After Rising Edge ADDR Hold After Rising Edge Hold After Rising Edge Period Pulse Width, High Pulse Width, RESET Pulse Width, tperclk Units
ABSOLUTE MAXIMUM RATINGS*
A0-A1 DATA
Supply Voltage (VDD) -0.3 +7.0 Digital Input Voltage -0.3 Analog Input Voltage -0.3 Analog Reference Input Voltage -0.3 Digital Output Voltage Swing -0.3 Analog Reference Output Swing -0.3 Operating Temperature -40°C +85°C Lead Temperature (Soldering, sec) +280°C
Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
Figure Clock Reset Timing
ORDERING GUIDE
Model
RESET
Temperature Range -40°C +85°C
Package Option P-44A
AD7861AP
Figure Write Cycle Timing Diagram
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD7861 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
REV.
AD7861
DESCRIPTION
33-34 38-39
CONFIGURATION
REFOUT
Mnemonic Type
AUX0 REFIN AGND REFOUT DGND DGND CONVST RESET BUSY DGND SGND VIN1 VIN2 VIN3 AUX3 AUX2 AUX1
Description
AGND REFIN AUX1 AUX2
Auxiliary Input Analog Reference Input Analog Ground Internal Analog Reference Channel Select Channel Select Data (Tied Low) Data Data Data Data Data Data Data Data Data Data Data Logic Ground Logic Ground Digital Supply Conversion Mode Select Conversion Mode Select Conversion Start Chip Select Read Input Chip Reset Register Address Select Register Address Select Connect Busy, Conversion Process External Clock Input 6.25 MHz-12.5 Logic Ground Signal Ground Analog Supply Analog Input Connect Analog Input Analog Input Auxiliary Input Auxiliary Input Auxiliary Input
AUX0
AUX3
VIN3
IDENTIFIER
VIN2 VIN1 SGND DGND DGND BUSY
AD7861
VIEW (Not Scale)
DGND DGND CONNECT CONVST RESET
Types Input Output
Types Ground Supply
REV.
AD7861
ANALOG INPUT BLOCK
AD7861 11-bit resolution, successive approximation analog-to-digital (A/D) converter with twos complement output data format. analog input range with reference defined reference input (REFIN). AD7861 internal reference, which utilized connecting reference output (REFOUT) REFIN pin. conversion time determined system clock frequency, which range from 6.25 12.5 MHz. Forty clock cycles required complete each conversion. There 4-channel simultaneous sample hold amplifier (SHA) AD7861 input stage. This allows channels simultaneously held sequentially digitized. acquisition time clock cycles independent number channels sampled. minimum throughput time calculated follows: tCONV where analog acquisition time, tSHA acquisition time, channels, tCONV conversion time channel clock cycles). conversions initiated external analog sample clock (CONVST). CONVST input asynchronous AD7861 system clock. When CONVST asynchronous from CLK, falling edge subsequent CONVST high initiates conversion.
BUSY
user must select which channels convert using M0/M1, minimum clock cycles before start conversion. AD7861 provides auxiliary input channels which individually multiplexed into auxiliary channel. Pins used multiplex these auxiliary channels according following table. important note that performs series conversions based input voltage each (including pin) start CONVST conversion pulse. user must select auxiliary channel using S0/S1 minimum clock cycles before start conversion sequence. Channel Selected AUX0 AUX1 AUX2 AUX3
DIGITAL INTERFACE
AD7861 designed interface with ADSP-21xx family DSPs. 12-bit parallel interface also used with other DSPs microcontrollers. 11-bit conversion output occupies most significant bits 12-bit interface. (Data tied low.
REGISTER BASED INPUT/OUTPUT
AD7861 BUSY goes start conversion, remains clock cycles channel. When BUSY goes high, this indicates that output data buffers have been updated. Data from previous conversion read clock cycles after start conversion number channels converted). Refer Figure
CLOCK CYCLE
CLOCK CYCLES BUSY
facilitate integration into most designs, register based input/output structure provided. These registers memory mapped into user's system along with other memory mapped peripherals.
REGISTER ADDRESSING
CLOCK CYCLES CLOCK CYCLES
address lines through used conjunction with control lines (CS, select registers VIN1, VIN2, VIN3, AUX. These control lines active low. Timing logical sense ADSP-2100 family. Function Enables AD7861 Register Interface Places Internal Register Data
CONVST
REGISTER LISTING
DATA VALID DATA VALID
DATA
output each channel stored respective register. symbolic names address locations listed following table. Name
VIN1 VIN2 VIN3
Figure Busy Pulse Timing
CHANNEL SELECTION
Register Function
Conversion Result Channel VIN1 Conversion Result Channel VIN2 Conversion Result Channel VIN3 Conversion Result Channel
Determining which channels converted dependent settings available channel combinations are: Channels Converted VIN2, VIN3 VIN2, VIN3, VIN1, VIN2, VIN3 VIN1, VIN2, VIN3,
REV.
AD7861
DESCRIPTION REGISTERS DIGITAL SIGNAL PROCESSOR INTERFACING
VIN1, VIN2, VIN3
These registers contain results from conversion analog input voltages. AD7861, this register contains conversion result auxiliary channel which been selected
conversion results channels VIN1, VIN2, VIN3 stored VIN1, VIN2, VIN3 registers respectively. twos complement data left justified (Data zero. relationship between input voltage output coding shown Figure
OUTPUT CODE FULL-SCALE TRANSITION
000000000000 2048
AD7861 operate with clock frequency range 6.25 12.5 MHz. ADSP-2101/2105/2115 CLKOUT frequency system clock frequency. case ADSP-2171/2181, system clock internally scaled, system clock will result CLKOUT frequency. CLKOUT from ADSP-2171/2181 above 12.5 MHz, then external clock divide down circuit will necessary.
ADDRESS
100000000000 5V-1LSB INPUT VOLTAGE
Figure AD7861 Transfer Function
A0-A13
ADDRESS DECODE BUSY
A0-A1
nominal power supply level (VDD) positive power supply (VDD) should connected Pins SGND DGND pins should star point connected AGND point close AD7861. Power supplies should bypassed power pins using capacitor. capacitor should also connected between REFIN SGND.
Power Supply Connections Setup
ADSP2101/ ADSP2105/ ADSP2115-12MHz ADSP2171-10MHz ADSP2181-10MHz
IRQ2 FLAGOUT CLKOUT
AD7861
CONVST
D0-D23
D0-D11*
DATA
Figure Digital Signal Processor/Microcomputer Interface
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
44-Lead Plastic Leadless Chip Carrier (P-44A)
PRINTED U.S.A.
0.180 (4.57) 0.165 (4.19) 0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07)
IDENTIFIER
0.056 (1.42) 0.042 (1.07)
0.025 (0.63) 0.015 (0.38)
0.050 (1.27)
0.63 (16.00) 0.59 (14.99)
VIEW
(PINS DOWN)
0.021 (0.53) 0.013 (0.33) 0.032 (0.81) 0.026 (0.66) 0.040 (1.01) 0.025 (0.64) 0.110 (2.79) 0.085 (2.16)
0.020 (0.50)
0.656 (16.66) 0.650 (16.51) 0.695 (17.65) 0.685 (17.40)
REV.
C2073-6-10/95
Reading Results
AD7861 converter designed easily interfaced Analog Devices' family Digital Signal Processors (DSPs). Figure shows interface between AD7861 ADSP-2101/2105/2115 16-bit fixed point DSP, ADSP2171 ADSP-2181 Microcomputers. FLAGOUT from used initiate AD7861 conversion also used conjunction with BUSY signal provide conversion interrupt DSP. With tied low, AD7861 VIN2, VIN3 channel conversion mode. mapping 12-bit AD7861 data into bits data (D12-D23), full-scale outputs from AD7861 represented fixed point arithmetic.

11-Bit Resolution Simultaneous Sampling Converter AD7861 2.5V REF

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