+2.7 +5.5 kSPS 8-Bit Sampling AD7819 AGND VREF AD7819 C

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+2.7 +5.5 kSPS 8-Bit Sampling AD7819 AGND VREF AD7819 C

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FEATURES 8-Bit with Conversion Time On-Chip Track Hold Operating Supply Range: +2.7 +5.5 Specifications +2.7 8-Bit Parallel Interface 8-Bit Read Power Performance Normal Operation 10.5 Automatic Power-Down 57.75 kSPS, Analog Input Range: VREF Reference Input Range:
+2.7 +5.5 kSPS 8-Bit Sampling AD7819
AGND VREF
AD7819
CHARGE REDISTRIBUTION CLOCK THREESTATE DRIVERS
COMP
CONTROL LOGIC
BUSY
CONVST
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
AD7819 high speed, microprocessor-compatible, 8-bit analog-to-digital converter with maximum throughput kSPS. converter operates single +2.7 +5.5 supply contains successive approximation converter, track/hold circuitry, on-chip clock oscillator 8-bit wide parallel interface. parallel interface designed allow easy interfacing microprocessors DSPs. Using only address decoding logic AD7819 easily mapped into microprocessor address space. When used power-down mode, AD7819 automatically powers down conversion powers start conversion. This feature significantly reduces power consumption part lower throughput rates. AD7819 also operate high speed mode where part powered down between conversions. this mode operation part capable providing kSPS throughput. part available small, 16-pin 0.3" wide, plastic dualin-line package (DIP); 16-pin, 0.15" wide, narrow body small outline (SOIC) 16-pin, narrow body, thin shrink small outline package (TSSOP).
Power, Single Supply Operation AD7819 operates from single +2.7 +5.5 supply typically consumes only 10.5 power. power dissipation significantly reduced lower throughput rates using automatic power-down mode. Automatic Power-Down automatic power-down mode, whereby AD7819 goes into power-down mode conversion powers before next conversion, means AD7819 ideal battery powered applications; e.g., 57.75 kSPS. (See Power Throughput Rate section.) Parallel Interface easy 8-bit wide parallel interface allows interfacing most popular microprocessors DSPs with minimal external circuitry. Dynamic Specifications Users addition traditional specifications, AD7819 specified parameters, including signal-to-noise ratio distortion.
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Site: http://www.analog.com Fax: 617/326-8703 Analog Devices, Inc., 1997
AD7819-SPECIFICATIONS1 +125 unless otherwise noted.)
(GND VREF +VDD
Units Parameter DYNAMIC PERFORMANCE Signal (Noise Distortion) Ratio1 Total Harmonic Distortion (THD)1 Peak Harmonic Spurious Noise1 Intermodulation Distortion2 Order Terms Order Terms ACCURACY Resolution Minimum Resolution Which Missing Codes Guaranteed Relative Accuracy1 Differential Nonlinearity (DNL)1 Total Unadjusted Error1 Gain Error1 Offset Error1 ANALOG INPUT Input Voltage Range Input Leakage Current2 Input Capacitance2 REFERENCE INPUTS2 VREF Input Voltage Range Input Leakage Current Input Capacitance LOGIC INPUTS2 VINH, Input High Voltage VINL, Input Voltage Input Current, Input Capacitance, LOGIC OUTPUTS Output High Voltage, Output Voltage, High Impedance Leakage Current High Impedance Capacitance CONVERSION RATE Conversion Time Track/Hold Acquisition Time1 POWER SUPPLY Normal Operation Power-Down Power Dissipation Normal Operation Power-Down Auto Power-Down (Mode kSPS Throughput kSPS Throughput kSPS Throughput Version VREF 2.7-5.5 17.5 57.75 577.5 2.89
10%). specifications
Test Conditions/Comments kHz, fSAMPLE
29.1 kHz; 29.8 Bits Bits Volts
(0.8 max, Typically
ISOURCE ISINK
Acquisition Section Specified Performance Digital Inputs
NOTES Terminology section. Sample tested during initial release after redesign process change that affect this parameter. Specifications subject change without notice.
REV.
AD7819 TIMING CHARACTERISTICS1, (-40 +125 unless otherwise noted)
Parameter tPOWER-UP
t73,
Units
(max) (max) (min) (max) (min) (min) (max) (max) (min)
Conditions/Comments
Power-Up Time AD7819 after Rising Edge CONVST. Conversion Time. CONVST Pulse Width. CONVST Falling Edge BUSY Rising Edge Delay. Setup Time. Hold Time after High. Data Access Time after Low. Relinquish Time after High. Data Relinquish Falling Edge CONVST Delay.
NOTES Sample tested ensure compliance. Figures These numbers measured with load circuit Figure They defined time required cross 10%. Derived from measured time taken data outputs change when loaded with circuit Figure measured number then extrapolated back remove effects charging discharging capacitor. This means that time, quoted Timing Characteristics true relinquish time part such independent external loading capacitances.
ABSOLUTE MAXIMUM RATINGS*
DGND -0.3 Digital Input Voltage DGND (CONVST, -0.3 Digital Output Voltage DGND (BUSY, DB0-DB7) -0.3 REFIN AGND -0.3 Analog Input -0.3 Storage Temperature Range -65°C +150°C Junction Temperature +150°C Plastic Package, Power Dissipation Thermal Impedance +105°C/W Lead Temperature, (Soldering sec) +260°C SOIC Package, Power Dissipation Thermal Impedance 75°C/W Lead Temperature, Soldering Vapor Phase sec) +215°C Infrared sec) +220°C SSOP Package, Power Dissipation Thermal Impedance 115°C/W Lead Temperature, Soldering Vapor Phase sec) +215°C Infrared sec) +220°C
*Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those listed operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
200µA
OUTPUT
+1.6V 50pF 200µA
Figure Load Circuit Digital Output Timing Specifications
ORDERING GUIDE
Model
Linearity Error Package (LSB) Description
Package Option
AD7819YN AD7819YR AD7819YRU
Plastic N-16 Small Outline R-16A Thin Shrink Small Outline RU-16 (TSSOP)
REV.
AD7819
FUNCTION DESCRIPTIONS
Mnemonic VREF CONVST
Description Reference Input, VDD. Analog Input, VREF. Analog Digital Ground. Convert Start. low-to-high transition this initiates pulse internally generated CONVST signal. high-to-low transition this line initiates conversion process internal CONVST signal low. Depending signal this conversion, AD7819 automatically powers down. Chip Select. This logic input. used conjunction with enable outputs. Read Pin. This logic input. When goes low, DB7-DB0 leave their high impedance state data driven onto data bus. Busy Signal. This logic output. This signal goes logic high during conversion process. Data These outputs three-state TTL-compatible. Positive power supply voltage, +2.7 +5.5
8-15
BUSY DB0-DB7
CONFIGURATION DIP/SOIC
VREF CONVST
VIEW (Not Scale)
AD7819
BUSY
REV.
AD7819
TERMINOLOGY Signal (Noise Distortion) Ratio Relative Accuracy
This measured ratio signal (noise distortion) output converter. signal amplitude fundamental. Noise nonfundamental signals half sampling frequency (fS/2), excluding ratio dependent upon number quantization levels digitization process; more levels, smaller quantization noise. theoretical signal (noise distortion) ratio ideal N-bit converter with sine wave input given Signal (Noise Distortion) (6.02N 1.76) Thus 8-bit converter, this
Total Harmonic Distortion
Relative accuracy endpoint nonlinearity maximum deviation from straight line passing through endpoints transfer function.
Differential Nonlinearity
This difference between measured ideal change between adjacent codes ADC.
Offset Error
This deviation first code transition (0000 000) (0000 001) from ideal, i.e., AGND LSB.
Offset Error Match
This difference Offset Error between channels.
Gain Error
Total harmonic distortion (THD) ratio harmonics fundamental. AD7819 defined
This deviation last code transition (1111 110) (1111 111) from ideal, i.e., VREF LSB, after offset error been adjusted out.
Gain Error Match
(dB)
This difference Gain Error between channels.
Track/Hold Acquisition Time
where amplitude fundamental amplitudes second through sixth harmonics.
Peak Harmonic Spurious Noise
Peak harmonic spurious noise defined ratio value next largest component output spectrum fS/2 excluding value fundamental. Normally, value this specification determined largest harmonic spectrum, parts where harmonics buried noise floor, will noise peak.
Intermodulation Distortion
Track/hold acquisition time time required output track/hold amplifier reach final value, within LSB, after conversion (the point which track/hold returns track mode). also applies situations where change selected input channel takes place where there step input change input voltage applied selected input AD7819. means that user must wait duration track/hold acquisition time after conversion after step input change before starting another conversion, ensure that part operates specification.
With inputs consisting sine waves frequencies, active device with nonlinearities will create distortion products difference frequencies where etc. Intermodulation terms those which neither equal zero. example, second order terms include fb), while third order terms include (2fa fb), (2fa fb), 2fb) 2fb). AD7819 tested using CCIF standard, where input frequencies near input bandwidth used. this case, second third order terms different significance. second order terms usually distanced frequency from original sine waves, while third order terms usually frequency close input frequencies. result, second third order terms specified separately. calculation intermodulation distortion specification where ratio individual distortion products amplitude fundamental expressed dBs.
REV.
AD7819
CIRCUIT DESCRIPTION Converter Operation
SUPPLY +2.7V +5.5V VREF DB0-DB7 PARALLEL INTERFACE
AD7819 successive approximation analog-to-digital converter based around charge redistribution DAC. convert analog input signals range VDD. Figures below show simplified schematics ADC. Figure shows during acquisition phase. closed Position comparator held balanced condition sampling capacitor acquires signal VIN+.
CHARGE RESTRIBUTION ACQUISITION PHASE VDD/3 COMPARATOR CLOCK SAMPLING CAPACITOR CONTROL LOGIC
AD7819
VREF INPUT BUSY CONVST
Figure Typical Connection Diagram
Analog Input
AGND
Figure Track Phase
When starts conversion, Figure will open will move Position causing comparator become unbalanced. Control Logic Charge Redistribution used subtract fixed amounts charge from sampling capacitor bring comparator back into balanced condition. When comparator rebalanced conversion complete. Control Logic generates output code. Figure shows transfer function.
CHARGE RESTRIBUTION CONVERSION PHASE VDD/3 COMPARATOR CLOCK SAMPLING CAPACITOR CONTROL LOGIC
Figure shows equivalent circuit analog input structure AD7819. diodes, provide protection analog inputs. Care must taken ensure that analog input signal never exceeds supply rails more than This will cause these diodes become forward biased start conducting current into substrate. maximum current these diodes conduct without causing irreversible damage part. capacitor typically about primarily attributed capacitance. resistor lumped component made resistance multiplexer switch. This resistor typically about capacitor sampling capacitor capacitance
3.5pF VDD/3
CONVERT PHASE SWITCH OPEN TRACK PHASE SWITCH CLOSED
Figure Equivalent Analog Input Circuit
Acquisition Time
AGND
Figure Conversion Phase
TYPICAL CONNECTION DIAGRAM
Figure shows typical connection diagram AD7819. parallel interface implemented using 8-bit data bus, falling edge CONVST brings BUSY signal high conversion, falling edge BUSY used initiate microprocessor. (See Parallel Interface section more details.) VREF connected well decoupled provide analog input range VDD. When first connected AD7819 powers current mode, i.e., power down. rising edge CONVST input will cause part power (See Power-Up Times section.) power consumption concern, automatic power-down conversion should used improve power performance. Power Throughput Rate section data sheet.
starts acquisition phase conversion ends falling edge CONVST signal. conversion there settling time associated with sampling circuit. This settling time lasts approximately analog signal also being acquired during this settling time. minimum acquisition time needed approximately Figure shows equivalent charging circuit sampling capacitor when acquisition phase. represents source impedance buffer amplifier resistive network, internal multiplexer resistance sampling capacitor.
3.5pF
Figure Equivalent Sampling Circuit
REV.
AD7819
During acquisition phase sampling capacitor must charged within final value. time takes charge sampling capacitor (TCHARGE) given following formula: TCHARGE small values source impedance, settling time associated with sampling circuit (100 effect, acquisition time ADC. example, with source impedance (R2) charge time sampling capacitor approximately charge time becomes significant source impedances greater.
Acquisition Time
When operating Mode powered down each conversion powered again before next conversion initiated. (See Figure
MODE
POWER-UP
applications recommended always buffer analog input signals. source impedance drive circuitry must kept possible minimize acquisition time ADC. Large values source impedance will cause degrade high throughput rates.
TRANSFER FUNCTION
MODE
POWER-UP
POWER-UP
output coding AD7819 straight binary. designed code transitions occur successive integer values (i.e., LSB, LSBs, etc.). size VREF/256. ideal transfer characteristic AD7819 shown Figure below.
Figure Power-Up Times
POWER THROUGHPUT RATE
operating AD7819 Mode average power consumption AD7819 decreases lower throughput rates. Figure shows Automatic Power-Down implemented using external CONVST signal achieve optimum power performance AD7819. AD7819 operated Mode duration external CONVST pulse equal less than power-up time device. throughput rate reduced, device remains powerdown state longer average power consumption over time drops accordingly.
111.111 111.110
CODE
111.000 1LSB VREF/256 011.111
000.010 000.001 000.000 1LSB ANALOG INPUT +VREF -1LSB
Figure Transfer Characteristic
POWER-UP CONVERT
POWER-DOWN
AD7819 power-up time. When first connected, AD7819 current mode operation. order carry conversion AD7819 must first powered powered rising edge internally generated CONVST signal, which occurs result rising edge external CONVST pin. rising edge external CONVST signal initiates pulse internal CONVST signal. This pulse present ensure part enough time power-up before conversion initiated, conversion initiated falling edge gated CONVST. Timing Control section. Care must taken ensure that CONVST AD7819 logic when first applied.
POWER-UP TIMES
tCYCLE
10kSPS
Figure Automatic Power-Down
example, AD7819 operated continuous sampling mode with throughput rate kSPS, power consumption calculated follows. power dissipation during normal operation 10.5 power-up time conversion time AD7819 said dissipate 10.5 (worst case) during each conversion cycle. throughput rate kSPS, cycle time then average power dissipated during each cycle (5.5/100) (10.5 577.5
REV.
AD7819 Typical Performance Characteristics
POWER
gate. resultant signal duration longer input signals. Once conversion been initiated, BUSY signal goes high indicate conversion progress. conversion sampling circuit returns tracking mode. conversion indicated BUSY signal going low. This signal used initiate microprocessor. this point conversion result latched into output register where read. AD7819 8-bit wide parallel interface. state external CONVST signal conversion also establishes mode operation AD7819.
Mode Operation (High Speed Sampling)
0.01 THROUGHPUT kSPS
Figure Power Throughput
AD7819 2048 POINT SAMPLING 136.054kHz 29.961kHz
external CONVST logic high when BUSY goes low, part said Mode operation. While operating Mode AD7819 will power down between conversions. AD7819 should operated Mode high speed sampling applications, i.e., throughputs greater than kSPS. Figure shows timing Mode operation. From this diagram that minimum delay conversion time read time must left between successive falling edges external CONVST. This ensure that conversion initiated during read.
Mode Operation (Automatic Power-Down)
-100 FREQUENCY
Figure
TIMING CONTROL
AD7819 only input timing control, i.e., CONVST (convert start signal). rising edge this CONVST signal initiates pulse internally generated CONVST signal. This pulse present ensure part enough time power before conversion initiated. external CONVST signal low, falling edge internal CONVST signal will cause sampling circuit into hold mode initiate conversion. however, external CONVST signal high when internal CONVST goes low, upon falling edge external CONVST signal that sampling circuitry will into hold mode initiate conversion. internally generated pulse previously described likened configuration shown Figure application CONVST signal CONVST triggers generation pulse. Both external CONVST this internal CONVST input
slower throughput rates AD7819 powered down between conversion give superior power performance. This Mode Operation achieved bringing CONVST signal logic before falling edge BUSY. Figure shows timing Mode Operation. falling edge external CONVST signal occur before after falling edge internal CONVST signal, later occurring falling edge both that controls when first conversion will take place. falling edge external CONVST occurs after that internal CONVST, means that moment first conversion controlled exactly, regardless jitter associated with internal CONVST signal. parallel interface still fully operational while AD7819 powered down. AD7819 powered again rising edge CONVST signal. gated CONVST pulse will remain high long enough AD7819 fully power which takes about This ensured internal CONVST signal, which will remain high
(PIN GATED
Figure
REV.
AD7819
CONVST
tPOWER-UP
CONVST
BUSY
CS/RD
DB7-DB0
MSBs
Figure Mode Operation
CONVST
tPOWER-UP
CONVST
BUSY
CS/RD
DB7-DB0
MSBs
Figure Mode Operation
PARALLEL INTERFACE
parallel interface AD7819 eight bits wide. output data buffers activated when both logic low. this point contents data register placed 8-bit data bus. Figure shows timing diagram parallel port. Parallel Interface AD7819 reset
when BUSY goes logic high. Care must taken ensure that read operation does occur while BUSY high. Data read from AD7819 while BUSY high will invalid. optimum performance read operation should least (t10) prior falling edge next CONVST.
CONVST
BUSY
MSBs
DB7-DB0
Figure Parallel Port Timing
REV.
AD7819
MICROPROCESSOR INTERFACING
parallel port AD7819 allows device interfaced range many different microcontrollers. This section explains interface AD7819 with some more common microcontroller parallel interface protocols.
AD7819 8051
PSP0-PSP7
DB0-DB7
PIC16C6x/7x*
AD7819*
Figure shows parallel interface between AD7819 8051 microcontroller. BUSY signal AD7819 provides interrupt request 8051 when conversion begins. Port 8051 serve input output port, this case when used together, used bidirectional low-order address data bus. address latch enable output 8051 used latch byte address during accesses device, while high-order address byte supplied from Port Port latches remain stable when AD7819 addressed, they have turned around (set data input case Port
BUSY
*ADDITIONAL PINS OMITTED CLARITY
Figure Interfacing PIC16C6x/7x
AD7819 ADSP-21xx
Figure shows parallel interface between AD7819 ADSP-21xx series DSPs. before, BUSY signal AD7819 provides interrupt request when conversion begins.
8051*
AD0-AD7 LATCH DECODER A8-A15
DB0-DB7
AD7819*
D0-D7
DB0-DB7
A13-A0
AD7819*
ADDRESS DECODE LOGIC
ADSP-21xx*
BUSY
*ADDITIONAL PINS OMITTED CLARITY
BUSY
Figure Interfacing 8051
AD7819 PIC16C6x/7x
*ADDITIONAL PINS OMITTED CLARITY
Figure shows parallel interface between AD7819 PIC16C64/65/74. BUSY signal AD7819 provides interrupt request microcontroller when conversion begins. PIC16C6x/7x range microcontrollers, only PIC16C64/65/74 provide option parallel slave port. Port microcontroller will operate 8-bit wide parallel slave port when control PSPMODE TRISE register set. Setting PSPMODE enables port output output. this functionality, corresponding data direction bits TRISE register must configured outputs (reset user PIC16/17 Microcontroller User Manual.
Figure Interfacing ADSP-21xx
-10-
REV.
AD7819
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
16-Lead Plastic (N-16)
0.840 (21.33) 0.745 (18.93)
0.280 (7.11) 0.240 (6.10) 0.060 (1.52) 0.015 (0.38) 0.130 (3.30)
0.210 (5.33) 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54)
0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93)
0.070 (1.77) SEATING 0.045 (1.15) PLANE
0.015 (0.381) 0.008 (0.204)
16-Lead Small Outline Package (R-16A)
0.3937 (10.00) 0.3859 (9.80)
0.1574 (4.00) 0.1497 (3.80)
0.2440 (6.20) 0.2284 (5.80)
0.0098 (0.25) 0.0040 (0.10)
0.0688 (1.75) 0.0532 (1.35)
0.0196 (0.50) 0.0099 (0.25)
SEATING PLANE
0.0500 (1.27)
0.0192 (0.49) 0.0138 (0.35)
0.0099 (0.25) 0.0075 (0.19)
0.0500 (1.27) 0.0160 (0.41)
16-Lead Thin Shrink Small Outline Package (RU-16)
0.201 (5.10) 0.193 (4.90)
0.177 (4.50) 0.169 (4.30)
0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) 0.0256 (0.65) 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090)
0.256 (6.50) 0.246 (6.25)
SEATING PLANE
0.028 (0.70) 0.020 (0.50)
REV.
-11-
-12-
C3059-12-6/97
PRINTED U.S.A.

+2.7 +5.5 kSPS 8-Bit Sampling AD7819 AGND VREF AD7819 C

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