LC2MOS Precision Quad SPST Switches ADG431/ADG432/ADG433 ADG431

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LC2MOS Precision Quad SPST Switches ADG431/ADG432/ADG433 ADG431

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FEATURES Supply Maximum Ratings Analog Signal Range Resistance (<24 Ultralow Power Dissipation (3.9 Leakage (<0.25 Fast Switching Times <165 tOFF <130 Latch-up Proof Break-Before-Make Switching Action TTL/CMOS Compatible Plug-in Replacement DG411/DG412/DG413 APPLICATIONS Audio Video Switching Automatic Test Equipment Precision Data Acquisition Battery Powered Systems Sample Hold Systems GENERAL DESCRIPTION
LC2MOS Precision Quad SPST Switches ADG431/ADG432/ADG433
ADG431
ADG432
ADG433
ADG431, ADG432 ADG433 monolithic CMOS devices comprising four independently selectable switches. They designed enhanced LC2MOS, trench isolated process which provides power dissipation gives high switching speed resistance. Trench isolation gives benefits dielectric isolation ensures latch even under extreme overvoltage conditions. resistance profile very flat over full analog input range ensuring excellent linearity distortion when switching audio signals. Fast switching speed coupled with high signal bandwidth also make parts suitable video signal switching. CMOS construction ensures ultralow power dissipation making parts ideally suited portable battery powered instruments. ADG431, ADG432 ADG433 contain four independent SPST switches. ADG431 ADG432 differ only that digital control logic inverted. ADG431 switches turned with logic appropriate control input, while logic high required ADG432. ADG433 switches with digital control logic similar that ADG431 while logic inverted other switches. Each switch conducts equally well both directions when input signal range which extends supplies. condition, signal levels supplies blocked. switches exhibit break before make switching action multiplexer applications. Inherent design charge injection minimum transients when switching digital inputs. REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
SWITCHES SHOWN LOGIC INPUT
PRODUCT HIGHLIGHTS
Extended Signal Range ADG431, ADG432 ADG433 fabricated enhanced LC2MOS, trench isolated process giving increased signal range which extends fully supply rails. Ultralow Power Dissipation Trench Isolation Guards Against Latch-up dielectric trench separates channel transistors thereby preventing latch-up even under severe overvoltage conditions. Break Before Make Switching This prevents channel shorting when switches configured multiplexer. Single Supply Operation applications where analog signal unipolar, ADG431, ADG432 ADG433 operated from single rail power supply. parts fully specified with single power supply will remain functional with single supplies
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
Dual Supply
Parameter
10%,
10%,
10%, unless otherwise noted)
Version
Version +125
Units
Test Conditions/Comments
ANALOG SWITCH Analog Signal Range (VS) Drift Match LEAKAGE CURRENTS Source Leakage (OFF) Drain Leakage (OFF) Channel Leakage (ON) DIGITAL INPUTS Input High Voltage, VINH Input Voltage, VINL Input Current IINL IINH Digital Input Capacitance DYNAMIC CHARACTERISTICS tOFF
0.05 0.25 0.05 0.25 0.35 0.05 0.25 0.05 0.25 0.35
+13.5 -13.5 %/°C VINL VINH +16.5 -16.5 15.5 15.5 Test Circuit 15.5 15.5 Test Circuit 15.5 Test Circuit
0.005
0.02
0.005
0.02
Break-Before-Make Time Delay, (ADG433 Only) Charge Injection Isolation Channel-to-Channel Crosstalk (OFF) (OFF) (ON) POWER REQUIREMENTS Power Dissipation 0.0001 0.0001 0.0001
Test Circuit Test Circuit Test Circuit Test Circuit MHz; Test Circuit MHz; Test Circuit +16.5 -16.5 Digital Inputs
0.0001 0.0001 0.0001
NOTES Temperature ranges follows: Versions: -40°C +85°C; Versions: -55°C +125°C. Guaranteed design, subject production test. Specifications subject change without notice.
REV.
ADG431/ADG432/ADG433 Single Supply
Parameter
10%,
Version
10%, unless otherwise noted)
Version +125
Units
Test Conditions/Comments
Analog Signal Range (VS) Drift Match LEAKAGE CURRENTS Source Leakage (OFF) Drain Leakage (OFF) Channel Leakage (ON) DIGITAL INPUTS Input High Voltage, VINH Input Voltage, VINL Input Current IINL IINH Digital Input Capacitance DYNAMIC CHARACTERISTICS tOFF
0.04 0.25 0.04 0.25 0.01 0.04 0.25 0.04 0.25 0.01
+10.8 %/°C VINL VINH +13.2 12.2/1 1/12.2 Test Circuit 12.2/1 1/12.2 Test Circuit +12.2 V/+1 Test Circuit
0.005
0.01
0.005
0.01
Break-Before-Make Time Delay, (ADG433 Only) Charge Injection Isolation Channel-to-Channel Crosstalk (OFF) (OFF) (ON) POWER REQUIREMENTS Power Dissipation 0.0001 0.03 0.0001 0.03
Test Circuit Test Circuit Test Circuit Test Circuit MHz; Test Circuit MHz; Test Circuit +13.2 Digital Inputs
0.0001 0.03 0.0001 0.03
+5.25
NOTES Temperature ranges follows: Versions: -40°C +85°C; Versions: -55°C +125°C. Guaranteed design, subject production test. Specifications subject change without notice.
Truth Table (ADG431/ADG432) ADG431 ADG432 Switch Condition Logic
Truth Table (ADG433) Switch Switch
REV.
ADG431/ADG432/ADG433
ABSOLUTE MAXIMUM RATINGS
+25°C unless otherwise noted) .+44 -0.3 +0.3 -0.3 Analog, Digital Inputs2 whichever occurs first Continuous Current, Peak Current, (Pulsed Duty Cycle max) Operating Temperature Range Industrial Version) -40°C +85°C Extended Version) -55°C +125°C Storage Temperature Range -65°C +150°C Junction Temperature +150°C Cerdip Package, Power Dissipation
Thermal Impedance 76°C/W Lead Temperature, Soldering sec) +300°C Plastic Package, Power Dissipation Thermal Impedance 117°C/W Lead Temperature, Soldering sec) +260°C SOIC Package, Power Dissipation Thermal Impedance 77°C/W Lead Temperature, Soldering Vapor Phase sec) +215°C Infrared sec) +220°C
NOTES Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those listed operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Only absolute maximum rating applied time. Overvoltages will clamped internal diodes. Current should limited maximum ratings given.
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although ADG431/ADG432/ADG433 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality. CONFIGURATION (DIP/SOIC)
WARNING!
SENSITIVE DEVICE
ORDERING GUIDE Model1 Temperature Range Package Option2
ADG431 ADG432 ADG433
VIEW (Not Scale)
ADG431BN ADG431BR ADG431TQ ADG432BN ADG432BR ADG432TQ ADG433BN ADG433BR
-40°C +85°C -40°C +85°C -55°C +125°C -40°C +85°C -40°C +85°C -55°C +125°C -40°C +85°C -40°C +85°C
N-16 R-16A Q-16 N-16 R-16A Q-16 N-16 R-16A
NOTES order MIL-STD-883, Class processed parts, /883B grade part numbers Plastic DIP; 0.15" Small Outline (SOIC); Cerdip.
TERMINOLOGY
Most positive power supply potential. Most negative power supply potential dual supplies. single supply applications, connected GND. Logic power supply Ground reference. Source terminal. input output. Drain terminal. input output. Logic control input. Ohmic resistance between (VS) variation change analog input voltage with constant load current. Drift Change temperature. Match Difference between switches. (OFF) Source leakage current with switch "OFF." (OFF) Drain leakage current with switch "OFF." (ON) Channel leakage current with switch "ON." (VS) Analog voltage terminals
(OFF) (OFF) (ON) tOFF Crosstalk
Isolation Charge Injection
"OFF" switch source capacitance. "OFF" switch drain capacitance. "ON" switch capacitance. Input Capacitance ground digital input. Delay between applying digital control input output switching Delay between applying digital control input output switching off. "OFF" time "ON" time measured between points both switches, when switching from address state another. measure unwanted signal which coupled through from channel another result parasitic capacitance. measure unwanted signal coupling through "OFF" switch. measure glitch impulse transferred digital input analog output during switching. REV.
ADG431/ADG432/ADG433 Typical Performance Graphs
+25°C +25°C
+10V -10V
+12V -12V
+10V +12V +15V
+15V -15V
DRAIN SOURCE VOLTAGE DRAIN SOURCE VOLTAGE
Figure Resistance Function (VS) Dual Supplies
+15V -15V
Figure Resistance Function (VS) Single Supply
100mA +15V -15V
10mA
SUPPLY
100µA 10µA
+125°C +85°C +25°C
100nA
100k
DRAIN SOURCE VOLTAGE
FREQUENCY
Figure Resistance Function (VS) Different Temperatures
+15V -15V
LEAKAGE CURRENT
Figure Supply Current Input Switching Frequency
0.04 +15V -15V
LEAKAGE CURRENT
±15V (OFF) (OFF)
0.02
+25°C
(ON) (OFF)
0.00 (OFF)
0.01
(ON)
-0.02
0.001 TEMPERATURE
-0.04 DRAIN SOURCE VOLTAGE
Figure Leakage Currents Function Temperature
Figure Leakage Currents Function (VS)
REV.
ADG431/ADG432/ADG433
+15V -15V
ISOLATION
NMOS
PMOS
LOCOS
WELL
WELL
TRENCH
100k
BURIED OXIDE LAYER SUBSTRATE (BACKGATE)
FREQUENCY
Figure Isolation Frequency
+15V -15V
Figure Trench Isolation
APPLICATION
CROSSTALK
Figure illustrates precise, fast sample-and-hold circuit. AD845 used input buffer while output operational amplifier AD711. During track mode, closed output VOUT follows input signal VIN. hold mode, opened signal held hold capacitor switch capacitor leakage, voltage hold capacitor will decrease with time. ADG431/ADG432/ ADG433 minimizes this droop leakage specifications. droop rate further minimized polystyrene hold capacitor. droop rate circuit shown typically µV/µs. second switch SW2, which operates parallel with SW1, included this circuit reduce pedestal error. Since both switches will same potential, they will have differential effect AD711 which will minimize charge injection effects. Pedestal error also reduced compensation network This compensation network also reduces hold time glitch while optimizing acquisition time. Using illustrated amps component values, pedestal error maximum value over input range. Both acquisition settling times
+15V
100k
FREQUENCY
Figure Crosstalk Frequency
TRENCH ISOLATION
ADG431, ADG432 ADG433, insulating oxide layer (trench) placed between NMOS PMOS transistors each CMOS switch. Parasitic junctions, which occur between transistors Junction Isolated switches, eliminated, result being completely latch-up proof switch. Junction Isolation, wells PMOS NMOS transistors form diode which reverse-biased under normal operation. However, during overvoltage conditions, this diode becomes forward biased. Silicon-Controlled Rectifier (SCR) type circuit formed transistors causing significant amplification current which, turn, leads latch-up. With Trench Isolation, this diode removed, result being latch-up proof switch. Trench Isolation also leads lower leakage currents. ADG431, ADG432 ADG433 have leakage current 0.25 compared with leakage current several nanoamps non-Trench Isolated switches. Leakage current important parameter sample-and-hold circuits, this current being responsible discharge holding capacitor with time causing droop. ADG431/ADG432/ADG433's leakage current, along with fast switching speeds, make suitable fast accurate sample-and-hold circuits.
2200pF
+15V 1000pF
+15V
AD845
-15V
AD711
VOUT
2200pF
-15V
ADG431/432/
-15V
Figure Fast, Accurate Sample-and-Hold
REV.
ADG431/ADG432/ADG433 Test Circuits
(OFF)
(OFF)
(ON)
V1/IDS
Test Circuit Resistance
+15V 0.1µF
Test Circuit Leakage
Test Circuit Leakage
0.1µF
VOUT
ADG431
35pF VOUT ADG432
0.1µF -15V
tOFF
Test Circuit Switching Times
+15V 0.1µF 0.1µF IN1, VOUT2 35pF VOUT2 VOUT1 35pF VOUT1
0.1µF -15V
Test Circuit Break-Before-Make Time Delay
+15V
10nF VOUT
VOUT
QINJ VOUT
VOUT
-15V
Test Circuit Charge Injection
REV.
ADG431/ADG432/ADG433
+15V 0.1µF 0.1µF
0.1µF +15V 0.1µF
VOUT
VOUT VIN1
0.1µF -15V
VIN2
CHANNEL CHANNEL 0.1µF -15V CROSSTALK
Test Circuit Isolation
Test Circuit Channel-to-Channel Crosstalk
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
16-Pin Cerdip (Q-16)
0.840 (21.34) 0.200 (5.08) 0.060 (1.52) 0.015 (0.38) 0.320 (8.13) 0.290 (7.37) 0.310 (7.87) 0.220 (5.59)
SEATING PLANE 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) 0.070 (1.78) 0.30 (0.76)
0.150 (3.81)
0.015 (0.381) 0.008 (0.204)
16-Pin Plastic (N-16)
16-Pin SOIC (R-16A)
0.25 0.31 (6.35) (7.87)
0.2440 (6.20) 0.2284 (5.80) 0.1574 (4.00) 0.1497 (3.80)
0.87 (22.1) 0.035 (0.89) 0.18 (4.57) 0.011 (0.28) (7.62) 0.018 (0.46) 0.033 (0.84) (2.54) SEATING PLANE
0.18 (4.57)
0.125 (3.18)
0.3937 (10.00) 0.3859 (9.80) 0.0688 (1.75) 0.0532 (1.35) 0.0098 (0.25) 0.0040 (0.10) 0.0500 (1.27) 0.0192 (0.49) 0.0138 (0.35) SEATING PLANE
0.0196 (0.50) 0.0099 (0.25)
0.0099 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41)
REV.
PRINTED U.S.A.
C1826-18-7/93

LC2MOS Precision Quad SPST Switches ADG431/ADG432/ADG433 ADG431

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