4194304-BIT (524288-WORD 8-BIT) CMOS STATIC M5M5408A 4,194,304-bi

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4194304-BIT (524288-WORD 8-BIT) CMOS STATIC M5M5408A 4,194,304-bi

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M5M5408AFP,TP,RT-70L-I,-70LL-I, -10L-I,-10LL-I
4194304-BIT (524288-WORD 8-BIT) CMOS STATIC
M5M5408A 4,194,304-bit CMOS static organized 524,288-words 8-bit, fabricated using high-performance quadruple-polysilicon double metal CMOS technology. thin film transistor (TFT) load cells CMOS periphery results high density power static RAM. M5M5408A designed memory applications where high performance, high reliability, large storage, simple interfacing battery back-up important design objectives. M5M5408A offered 32-pin plastic small outline package (SOP) 32-pin thin small outline package (TSOP), providing high board level packing densities. types TSOP packages available, M5M5408ATP(normal lead bend type package) M5M5408ART (reverse lead bend type package). Using both types makes easy design printed circuit board.
CONFIGURATION (TOP VIEW)
FEATURES
Type Access time (max) M5M5408AFP,TP,RT-70L-I M5M5408AFP,TP,RT-10L-I 70ns 100ns 90mA (Vcc=5.5V) M5M5408AFP,TP,RT-70LL-I M5M5408AFP,TP,RT-10LL-I 70ns 100ns 40µA (Vcc=5.5v) Power supply current Active (max) Stand-by (max) 200µA (Vcc=5.5v)
(0V)GND
VCC(5V)
Outline 32P2M-A(FP) 32P3Y-H(TP)
M5M5408AFP,TP
(5V)VCC
Single power supply clocks, refresh inputs outputs compatible. Easy memory expansion power down Data retention supply voltage=+2.0V Three-state outputs: OR-tie capability prevents data contention Common Data Small stand-by current.0.4µA(typ.) Package M5M5408AFP M5M5408ATP TSOP(II) M5M5408ART TSOP(II)
GND(0V)
Outline 32P3Y-J(RT)
M5M5408ART
APPLICATION
Small capacity memory units, card, Battery operating system, asynchronous server system
MITSUBISHI ELECTRIC
M5M5408AFP,TP,RT-70L-I,-70LL-I, -10L-I,-10LL-I
4194304-BIT (524288-WORD 8-BIT) CMOS STATIC
FUNCTION
operation mode M5M5408A determined combination device control inputs Each mode summarized function table. write cycle executed whenever level overlaps with level address must before write cycle must stable during entire cycle. data latched into cell trailing edge whichever occurs first, requiring set-up hold time relative these edge maintained. output enable directly controls output stage. Setting high level,the output stage high-impedance state, data contention problem write cycle eliminated. read cycle executed setting high level level while active state(S=L). When setting high level, chips non-selectable mode which both reading writing disabled. this mode, output stage high-impedance state, allowing OR-tie with other chips memory expansion power supply current reduced stand-by current which specified Icc3 Icc4, memory data held power supply, enabling battery back-up operation during power failure power-down operation non-selected mode.
FUNCTION TABLE
Mode selection Write Read High-impedance High-impedance Standby Active Active Active
BLOCK DIAGRAM
ADDRESS INPUT BUFFER DECODER OUTPUT BUFFER AMP. 524288 WORDS BITS ROWS COLUMNS BLOCKS
ADDRESS INPUT BUFFER
CLOCK GENERATOR
DATA INPUT BUFFER
COLUMN DECODER
SENSE
BLOCK DECODER ADDRESS INPUT BUFFER
(3.3V)
(0V)
MITSUBISHI ELECTRIC
M5M5408AFP,TP,RT-70L-I,-70LL-I, -10L-I,-10LL-I
4194304-BIT (524288-WORD 8-BIT) CMOS STATIC
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter Supply voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature
Conditions
Ratings -0.3~ -0.3*~ Vcc+0.3 0~Vcc
Units
With respect Ta=25°C
~150
-3.0V case (Pulse width 30ns)
ELECTRICAL CHARACTERISTICS (Ta= -40~85°C, Vcc=5V±10%, unless otherwise noted)
Symbol Parameter High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Input leakage current Output leakage current Active supply current (AC,MOS level) Active supply current (AC,TTL level)
Conditions
-0.3* Vcc-0.5
Limits
Vcc+0.3
Units
=-1mA =-0.1mA =2mA =0~Vcc S=VIH,OE=VIH,VI/O=0~Vcc S0.2V Other inputs 0.2V Vcc-0.2V Output-open (duty 100%) S=VIL ,W=V Other inputs=VIH Output-open (duty 100%) Vcc-0.2V Other inputs=0 ~Vcc S=VIH,Other inputs=0 ~Vcc
Minimum cycle
1MHz
Minimum cycle
1MHz FP,VP,RT-L FP,VP,RT-LL
Stand supply current Stand supply current
-3.0V case (Pulse width 30ns)
CAPACITANCE (Ta=-40~85°C, Vcc=5V±10%, unless otherwise noted)
Symbol Parameter Input capacitance (Ta=25°C Output capacitance (Ta=25°C Conditions =GND, =25mVrms,f=1MHz O=GND, =25mVrms,f=1MHz Limits Units
Note Direction current flowing into indicated positive mark) Note Typical value Vcc=5V,Ta=25°C Note periodically sampled 100% tested.
MITSUBISHI ELECTRIC
M5M5408AFP,TP,RT-70L-I,-70LL-I, -10L-I,-10LL-I
4194304-BIT (524288-WORD 8-BIT) CMOS STATIC
SWITCHING CHARACTERISTICS (Ta=-40~85°C, Vcc=5V±10%, unless otherwise noted) READ CYCLE
Limits Symbol Parameter
M5M5408FP,TP, RT-70L-I,-70LL-I M5M5408FP,TP, RT-10L-I,-10LL-I
Units
ta(A) (OE) tdis(S) tdis(OE) (OE)
Read cycle time Address access time Chip select access time Output enable access time Output disable time after high Output disable time after high Output enable time after Output enable time after Data valid time after address
TIMING REQUIREMENTS (Ta=-40~85°C, Vcc=5V±10%, unless otherwise noted) WRITE CYCLE
Limits Symbol Parameter
M5M5408FP,TP, M5M5408FP,TP, RT-70L-I,-70LL-I RT-10L-I,-10LL-I
Units
trec tdis tdis (OE) (OE)
Write cycle time Write pulse width Address time
(A-WH) Address time with respect high
Chip select time Data time Data hold time Write recovery time Output disable time after Output disable time after high Output enable time after high Output enable time after
MITSUBISHI ELECTRIC
M5M5408AFP,TP,RT-70L-I,-70LL-I, -10L-I,-10LL-I
4194304-BIT (524288-WORD 8-BIT) CMOS STATIC
TIMING DIAGRAMS Read cycle 0~18
(Note4) (Note4)
(OE) (OE)
tdis
(Note4)
(Note4)
tdis (OE)
DQ1~8
(Dout
W="H" level Write cycle control mode)
0~18
(Note4)
(Note4)
(A-WH)
trec
DQ1~8
(Din) tdis tdis (OE)
DATA STABLE
(OE)
DQ1~8
(Dout)
MITSUBISHI ELECTRIC
M5M5408AFP,TP,RT-70L-I,-70LL-I, -10L-I,-10LL-I
4194304-BIT (524288-WORD 8-BIT) CMOS STATIC
Write cycle control mode)
0~18
trec
(Note6)
(Note4)
(Note5)
(Note4)
DQ1~8
(Din)
DATA STABLE
MEASUREMENT CONDITIONS
Input pulse VIH=2.4V, VIL=0.6V Input rise time fall time Reference level VOH=VOL=1.5V Transition measured ±500mV from steady state voltage (for ten,tdis). Output loads Fig. CL=100pF (FP,TP,RT-10L,-10LL) CL=30pF (FP,TP,RT-70L,-70LL) CL=5pF (for ten,tdis)
1.8k
Including scope
Fig.1 Output load
Note Hatching indicates state "don't care". Note Write occurs during overlap Note goes simultaneously with prior S,the output remains highimpedance state. Note Don't apply inverted phase signal externally when output mode.
MITSUBISHI ELECTRIC
M5M5408AFP,TP,RT-70L-I,-70LL-I, -10L-I,-10LL-I
4194304-BIT (524288-WORD 8-BIT) CMOS STATIC
POWER DOWN CHARACTERISTICS ELECTRICAL CHARACTERISTICS
Symbol Parameter (Ta=-40~85°C, Vcc=5V±10%, unless otherwise noted) Test conditions Vcc(PD) Power down supply voltage I(S) Chip select input 2.2V Vcc(PD) Vcc(PD) 2.2V
-40~70°C Vcc=3V, Vcc-0.2V, Other inputs=0~3V 70~85°C -40~70°C 70~85°C
Limits
Units
Vcc(PD)
cc(PD) Power down supply current
Icc(PD)=1µA Ta=25°C
TIMING REQUIREMINTS
Symbol Parameter
(Ta=-40~85°C, Vcc=5V±10%, unless otherwise noted) Test conditions Limits Units
(PD) Power down time (PD) Power down recovery time
(PD)
2.2V 3.0V 3.0V
(PD)
2.2V
Vcc-0.2V
MITSUBISHI ELECTRIC

4194304-BIT (524288-WORD 8-BIT) CMOS STATIC M5M5408A 4,194,304-bi

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