Document Title 256K 32Bit Banks Synchronous Graphic Revision History

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Document Title 256K 32Bit Banks Synchronous Graphic Revision History

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A45L9332 Series
Document Title 256K 32Bit Banks Synchronous Graphic Revision History
256K 32Bit Banks Synchronous Graphic
History
Initial issue
Issue Date
December 1998
Remark
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Features
JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Dual band Pulse cycle with address programs Latency (2,3) Burst Length (1,2,4,8 full page) Burst Type (Sequential Interleave) inputs sampled positive going edge system clock Burst Read Single-bit Write operation byte masking Auto self refresh 32ms refresh period cycle) QFP, LQFP
256K 32Bit Banks Synchronous Graphic
Graphics Features
SMRS cycle Load mask register Load color register Write (Old Mask) Block Write Columns)
General Description
A45L9332 16,777,216 bits synchronous high data rate Dynamic organized 262,144 words bits, fabricated with AMIC' high performance CMOS technology. Synchronous design allows precise cycle control with system clock. transactions possible every clock cycle. Range operating frequencies, programmable latencies allows same device useful variety high bandwidth, high performance memory system applications. Write columns block write improves performance graphics system.
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Configuration
VSSQ
DQ31
DQ30
VSSQ
VDDQ VSSQ VDDQ VSSQ VDDQ VSSQ VDDQ DQM0 DQM2 BA(A10)
DQ29
VDDQ VSSQ DQ25 VDDQ DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ DQ11 DQ10 VSSQ VDDQ DQM3 DQM1
A45L9332L
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Block Diagram
DQMi BLOCK WRITE CONTROL LOGIC
MASK REGISTER WRITE CONTROL LOGIC MASK CLOCK REGISTER
INPUT BUFFER
COLUMN MASK DQMi TIMMING REGISTER
(i=0~31)
SENSE AMPLIFIER
LATENCY BURST LENGTH
PROGRAMING REGISTER
256K CELL ARRAY
256K CELL ARRAY
DECORDER BANK SELECTION
DQMi
SERIAL COUNTER
COLUMN ADDRESS BUFFER
ADDRESS BUFFER
REFRESH COUNTER
ADDRESS REGISTER
CLOCK
ADDRESS (A0~A10)
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
INPUT BUFFER
COLUMN DECORDER
A45L9332 Series
Descriptions
Symbol
Name System Clock Chip Select
Description Active positive going edge sample inputs. Disables Enables device operation masking enabling inputs except CLK, DQMi Masks system clock freeze operation from next clock cycle.
Clock Enable
should enabled least clock prior command. Disable input buffers power down standby. Column addresses multiplexed same pins.
A0~A9
Address address RA0~RA9, Column address: CA0~CA7 Selects bank activated during address latch time.
A10(BA)
Bank Select Address Selects band read/write during column address latch time. Latches addresses positive going edge with low. Enables access precharge. Latches column addresses positive going edge with low. Enables column access.
Address Strobe
Column Address Strobe
Write Enable Data Input/Output Mask
Enables write operation precharge. Makes data output Hi-Z, after clock masks output.
DQMi VDD/VSS VDDQ/VS
Blocks data input when active. (Byte Masking) Data Input/Output Define Special Function Power Supply/Ground Data Output Power/Ground Connection Data inputs/outputs multiplexed same pins. Enables write bit, block write special mode register set. Power Supply: +3.3V±0.3V/Ground Provide isolated Power/Ground improved noise immunity.
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Absolute Maximum Ratings*
Voltage relative (Vin, Vout -1.0V +4.6V Voltage supply relative (VDD, VDDQ -1.0V +4.6V Storage Temperature (TSTG) -55° +150° Soldering Temperature Time (TSLODER) 260° 10sec Power Dissipation (PD) Short Circuit Current (Ios) 50mA
*Comments
Permanent device damage occur Absolute Maximum Ratings" exceeded. Functional operation should restricted recommended operating condition. Exposure higher than recommended voltage extended periods time could affect device reliability.
Electrical Characteristics
Recommend operating conditions (Voltage referenced Parameter Supply Voltage Input High Voltage Input Voltage Output High Voltage Output Voltage Input Leakage Current Output Leakage Current Output Loading Condition Symbol VDD,VDDQ -0.3 Figure VDD+0.3 Unit Note -2mA Note Note Note
Note: (min) -1.5V (pulse width 5ns). input 0.3V, other pins under test Dout disabled, Vout
Decoupling Capacitance Guide Line
Recommended decoupling capacitance added power line board. Parameter Decoupling Capacitance between Decoupling Capacitance between VDDQ VSSQ Symbol CDC1 CDC2 Value 0.01 0.01 Unit
Note: VDDQ pins separated each other. pins connected chip. VDDQ pins connected chip. VSSQ pins separated each other pins connected chip. VSSQ pins connected chip.
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Electrical Characteristics
(Recommended operating condition unless otherwise noted, VIH(min)/VIL(max) 2.0V/0.8V) Symbol Parameter Operating Current Icc1 Icc2 Icc2 ICC2N (One Bank Active) Precharge Standby Current powerdown mode Test Conditions Burst Length tRC(min), tCC(min), VIL(max), 15ns VIL(max), VIL(max), VIH(min), VIH(min), 15ns Precharge Standby Current power-down mode Input signals changed time during 30ns VIH(min), VIL(max), Input signals stable. ICC3 ICC3 ICC3N Active Standby Current powerdown mode Active Standby current power-down mode (One Bank Active) VIL(max), 15ns VIL(max), VIL(max) VIH(min), VIH(min), 15ns Input signals changed time during 30ns VIH(min), VIL(max), Input signals stable. Operating Current (Burst Mode) ICC5 ICC6 ICC7 Refresh Current Self Refresh Current Operating Current 0mA, Page Burst bank Activated, tCCD tCCD (min) (min) 0.2V (min), IOL=0mA, tBWC(min) Latency Speed Unit Notes
ICC2NS
ICC3NS
ICC4
Note: Measured with outputs open. Addresses changed only time during tCC(min). Refresh period 32ms. Addresses changed only time during tCC(min).
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Operating Test Conditions
(VDD 3.3V ±0.3V, +70° Parameter input levels Input timing measurement reference level Input rise time (See note3) Output timing measurement reference level Output load condition Value VIH/VIL 2.4V/0.4V 1.4V tr/tf 1ns/1ns 1.4V Fig.2
3.3V 1200 Output OUTPUT VOH(DC) 2.4V, -2mA VOL(DC) 0.4V, =1.4V ZO=50 30pF
(Fig. Output Load Circuit
(Fig. Output Load Circuit
Characteristics
operating conditions unless otherwise noted) Symbol Parameter Latency cycle time Latency valid tSAC Output delay Latency Latency 1000 1000 1000 Unit Note
Output data hold time high pulse width
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Characteristics (continued)
operating conditions unless otherwise noted) Symbol Parameter tSLZ pulse width Input setup time Input hold time output Low-Z output tSHZ Hi-Z Latency Latency Unit Note
*All parameters measured from half half. Note Parameters depend programmed latency. clock rising time longer than 1ns, (tr/2-0.5)ns should added parameter. Assumed input rise fall time 1ns. longer than 1ns, transient time compensation should considered, i.e., tf)/2-1] should added parameter.
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Operating Parameter
operating conditions unless otherwise noted) Version Symbol Parameter tRRD(min) tRCD(min) tRP(min) tRAS(min) active time tRAS(max) tRC(min) tCDL(min) tRDL(min) tBDL(min) tCCD(min) tBPL(min) tBWC(min) cycle time Last data col. Address delay Last data precharge Last data burst stop Col. Address col. Address delay Block write data-in command Block write cycle time Number valid output data latency active active delay
delay
Unit
Note
precharge time
latency
Note: minimum number clock cycles determined dividing minimum time required with clock cycle time then rounding next higher integer. Minimum delay required complete write. This parameter means minimum delay block write cycle only. case precharge interrupt, auto precharge read burst stop.
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Simplified Truth Table
Command Register Refresh Mode Register Special Mode Register Auto Refresh Self Refresh Bank Active Addr. Entry Exit Bank Selection Both Banks Clock Suspend Active Power Down Entry Exit Entry Precharge Power Down Mode Exit Operation Command Addr. Column Addr. CKEn-1 CKEn
A8~A0 Notes
CODE 1,2,7 4,5,9
Write Bite Disable Write Enable
Read Auto Precharge Disable Column Addr. Auto Precharge Enable Write Auto Precharge Disable Column Addr. Auto Precharge Enable Block Write Auto Precharge Disable Column Addr. Auto Precharge Enable Burst Stop Precharge
Column Addr. 4,5,6,9 Column Addr. 4,5,6,9
Valid, Don' Care, Logic High, Logic Low) Note Code Operand Code A0~A10 Program keys. (@MRS) Color register exists only which both banks share. dose Mask Register. Color mask loaded into chip through pin. issued only both banks precharge state. SMRS issued only idle. command issued next clock MRS/SMRS. Auto refresh functions same refresh DRAM. automatical precharge without precharge command meant Auto" Auto/Self refresh issued only both precharge state.
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Mode Register Filed Table Program Modes
Register Programmed with Address Function W.B.L
(Note
Latency
Burst Length
(Note
Test Mode Type Mode Register Vendor Only
Latency Latency Reserved Reserved Reserved Reserved Reserved
Burst Type Type Sequential Interleave
Burst Length BT=0 Reserved Reserved Reserved 256(Full) BT=1 Reserved Reserved Reserved Reserved Reserved Reserved (Note
Write Burst Length Length Burst Single
Special Mode Register Programmed with SMRS Address Function
Load Color
Load Mask Function Disable Enable (Note
Function Disable Enable
Power Sequence
Apply power start clock, Attempt maintain other pins condition inputs. Maintain stable power, stable clock input condition minimum 200µs. Issue precharge commands banks devices. Issue more auto-refresh commands. Issue mode register command initialize mode register. cf.) Sequence changed. device ready normal operation. Note RFU(Reserved Future Use) should stay during cycle. high during cycle, Burst Read Single Write" function will enabled. full column burst (256bit) available only Sequential mode burst type. both high (1), data mask color register will unknown. PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Burst Sequence (Burst Length
Initial address Sequential Interleave
Burst Sequence (Burst Length
Initial address Sequential Interleave
Pixel Mapping BLOCK WRITE)
Column address Byte I/O31 I/O24 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 Byte I/O23 I/O16 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 Byte I/O15 I/O8 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 Byte I/O7 I/O0
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Device Operations
Clock (CLK) clock input used reference SGRAM operations. operations synchronized positive going edge clock. clock transitions must monotonic between VIH. During operation with high inputs assumed valid state (low high) duration hold time around positive edge clock proper functionality specifications. Clock Enable (CLK) clock enable (CKE) gates clock onto SGRAM. goes synchronously with clock (set-up hold time same other inputs), internal clock suspended form next clock cycle state output burst address frozen long remains low. other inputs ignored from next clock cycle after goes low. When both banks idle state goes synchronously with clock, SGRAM enters power down mode form next clock cycle. SGRAM remains power down mode ignoring other inputs long remains low. power down exit synchronous internal clock suspended. When goes high least CLOCK" before high going edge clock, then SGRAM becomes active from same clock edge accepting input commands. Bank Select (A10) This SGRAM organized independent banks 262,144 words bits memory arrays. inputs latched time assertion select bank used operation. When asserted low, bank selected. When asserted high, bank selected. bank select latched bank activate, read, write mode register precharge operations. Address Input address bits required decode 262,144 word locations multiplexed into address input pins (A0~A9). address latched along with during bank activate command. column address latched along with during read write command. Device Deselect When high, SGRAM performs operation (NOP). does initiate operation, needed complete operations which require more than single clock like bank activate, burst read, auto refresh, etc. device deselect also entered asserting high. high disables command decoder that address inputs ignored. Power-Up following sequence recommended POWER Power must applied either inputs pull them high other pins condition inputs before along with (and VDDQ) supply. clock signal must also asserted same time. After reaches desired voltage, minimum pause microseconds required with inputs condition. Both banks must precharged now. Perform minimum Auto refresh cycles stabilize Internal circuitry. Perform MODE REGISTER cycle program latency, burst length burst type default value mode register undefined. clock cycle from mode register cycle, device ready operation. When above sequence used Power-up, out-puts will high impedance state. high impedance outputs guaranteed other power-up sequence. Cf.) Sequence charged. Mode Register (MRS) mode register stores data controlling various operation modes SGRAM. programs latency, addressing mode, burst length, test mode various vendor specific options make SGRM useful variety different applications. default value mode register defined, therefore mode register must written after power operate SGRAM. mode register written asserting
(The SGRAM should active mode with already high prior writing mode register). state address pins A0~A9 same cycle going data written mode register. clock cycle required complete write mode register. mode register contents changed using same command clock cycle requirements during operation long both banks idle state. mode register divided into various fields depending functionality. burst length field uses A0~A2, burst type uses addressing mode uses A4~A6, A7~A8 used vendor specific options test mode. write burst length programmed using A7~A8 must normal SGRAM operation. Refer table specific codes various burst length, addressing modes latencies.
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Device Operations (continued)
Bank Activate bank activate command used select random idle bank. asserting Burst Write burst write command similar burst read command, used write data into SRGAM consecutive clock cycles adjacent addresses depending burst length burst sequence. asserting
with desired bank addresses, access initiated. read write operation occur after time delay tRCD(min) from time bank activation. tRCD(min) internal timing parameter SGRAM, therefore dependent operating clock frequency. minimum number clock cycles required between bank activate read write command should calculated dividing tRCD(min) with cycle time clock then rounding result next higher integer. SGRAM internal banks same chip shares part internal circuitry reduce chip area, therefore restricts activation both banks immediately. Also noise generated during sensing each bank SGRAM high requiring some time power supplies recover before other bank sensed reliably. tRRD(min) specifies minimum time required between activating different banks. number clock cycles required between different bank activation must calculated similar tRCD specification. minimum time required bank active initiate sensing restoring complete dynamic cells determined tRAS(min) specification before precharge command that active bank asserted. maximum time bank active state determined tRAS(max). number cycles both tRAS(min) tRAS(max) calculated similar tRCD specification.
Burst Read burst read command used access burst data consecutive clock cycles from active active bank. burst read command issued asserting with being high positive edge clock. bank must active least tRCD(min) before burst read command issued. first output appears latency number clock cycles after issue burst read command. burst length, burst sequence latency from burst read command determined mode register which already programmed. burst read initiated column address active row. address wraps around initial address does start from boundary such that number outputs from each equal burst length programmed mode register. output goes into high-impedance burst, unless burst read initiated keep data output gapless. burst read terminated issuing another burst read burst write same bank other active bank precharge command same bank. burst stop command valid only full page burst length where output dose into high impedance burst burst wrap around. PRELIMINARY (December, 1998, Version 0.0)
with valid column address, write burst initiated. data inputs provided initial address same clock cycle burst write command. input buffer deselected burst length, even though internal writing have been completed yet. writing complete burst length. burst write terminated issuing burst read blocking data inputs burst write same other active bank. burst stop command valid only full page burst length where writing continues burst burst wrap around. write burst also terminated using blocking data precharging bank RDL" after last data input written into active row. OPERATION also.
Operation used mask input output operation. works similar during read operation inhibits writing during write operation. read latency cycles from zero cycle write, which means masking occurs cycles later read cycle occurs same cycle during write cycle. operation synchronous with clock, therefore masking occurs complete cycle. signal important during burst interrupts write with read precharge SGRAM. asynchronous nature internal write, operation critical avoid unwanted incomplete writes when complete burst write required. also used device selection, byte selection control memory system. DQM0 controls DQ7, DQM1 controls DQ15, DQM2 controls DQ16 DQ23, DQM3 controls DQ24 DQ31. masks byte regardless that corresponding state masking Pixel masking. Please refer timing diagram also. Precharge precharge operation performed active bank asserting with valid bank precharged. precharge command asserted anytime after tRAS(min) satisfied from bank activate command desired bank. defined minimum time required precharge bank. minimum number clock cycles required complete precharge calculated dividing with clock cycle time rounding next higher integer. Care should taken make sure that burst write completed
AMIC Technology, Inc.
A45L9332 Series
Device Operations (continued)
used inhibit writing before precharge command asserted. maximum time bank active specified tRAS(max). Therefore, each bank precharged within tRAS(max) from bank activate command. precharge, bank enters idle state ready activated again. Entry Power Down, Auto refresh, Self refresh Mode register etc, possible only when both banks idle state. Auto Precharge precharge operation also performed using auto precharge. SGRAM internally generates timing satisfy tRAS(min) programmed burst length latency. auto precharge command issued same time burst read burst write asserting high burst read burst write command issued with bank left active until command asserted. Once auto precharge command given, commands possible that particular bank until bank achieves idle state. Both Banks Precharge Both banks precharged same time using Precharge command. Asserting Self Refresh self refresh another refresh mode available SGRAM. self refresh preferred refresh mode data retention power operation SGRAM. self refresh mode, SGRAM disables internal clock input buffers except CKE. refresh addressing timing internally generated reduce power consumption. self refresh mode entered from banks idle state asserting with high Once self refresh mode entered, only state being matters, other inputs including clock ignored remain self refresh. self refresh exited restarting external clock then asserting high CKE. This must followed NOP' minimum time before SGRAM reaches idle state begin normal operation. system uses burst auto refresh during normal operation, recommended used burst 2048 auto refresh cycles immediately after exiting self refresh. Define Special Function (DSF) controls graphic applications SGRAM. tied low, SGRAM function 256K Bank SDRAM. SDRAM used unified memory appropriate command. graphic function mode entered only setting high when issuing commands which otherwise would normal SDRAM commands. SDRAM functions such Active, Write, WCBR change SGRAM functions such Active with WPB, Block Write SWCBR respectively. sessions below graphic functions that controls. Special Mode Register (SMRS) There kinds special mode registers SGRAM. color register other mask register. Those usage will explained WRITE BIT" BLOCK WRITE" session. When goes high same cycle going low, load mask register (LMR) process executed mask registers filled with masks associated through pins. when goes high same cycle going low, load color register (LCR) process executed color register filled with color data associated through pins. both high SMRS, data mask color cycle required complete write mask register color register respectively. next clock LCR, commands issued. SMRS, compared with MRS, issued active state under condition that idle. write operation, SMRS accepts data needed through pins. Therefore should
with high after both banks have satisfied tRAS(min) requirement, performs precharge both banks. after performing precharge all, both banks idle state.
Auto Refresh storage cells SGRAM need refreshed every 32ms maintain data. auto refresh cycle accomplishes refresh single storage cells. internal counter increments automatically every auto refresh cycle refresh rows. auto refresh command issued asserting with high auto refresh command only asserted with both banks being idle state device power down mode (CKE high previous cycle). time required complete auto refresh operation specified RC(min)" minimum number clock cycles required calculated driving with clock cycle time then rounding next higher integer. auto refresh command must followed NOP' until auto refresh operation completed. Both banks will idle state auto refresh operation. auto refresh preferred refresh mode when SGRAM being used normal data transactions. auto refresh cycle performed once 15.6us burst 2048 auto refresh cycles once 32ms.
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Device Operations (continued)
attended induce contention. more detailed materials obtained referring corresponding timing diagram. Write Write (i.e. mask mode) SGRAM function that selectively masks bits data being written devices. mask stored internal register applied each data written when enabled. Bank active command with High enabled write operations stored mask register accessed SWCBR (Special Mode Register Command). When mask associated data written when write command executed write been enabled bank being written. When mask associated data unaltered when write command executed write been enabled bank being written. additional timing conditions required write operations. Write writes either single write, burst writes block writes. masking same write non-WPB write. Block Write
byte masking during block write exactly same does during normal write operations, except that control extended consecutive columns block write. Timing Diagram Illustrate tBWC
Clock
High
Block write feature allowing simultaneous writing consecutive columns data within device during single access cycle. During block write data written comes from internal color" register pins used independent column selection. block column written aligned column boundaries defined column address with LSB' ignored. Write command with 1enables block write associated bank. write command with enables normal write associated bank. block width column where column bits part. color register same width data port chip. written SWCBR where data present coupled into internal color register. color register provides data masked column select, mask enabled), byte mask. Column data masking (Pixel masking) provided individual column basis each byte data. column mask driven pins during block write command. column mask function segmented basis (i.e. DQ[0:7] provides column mask data bits[0:7], DQ[8:15] provides column mask data bits[8:15], masks column[0] data bits[0:7], masks column data [8:15], etc). Block writes always non-burst, independent burst length that been programmed into mode register. Back back block writes allowed provided that specified block write cycle time (tBWC) satisfied. write enabled bank active command with then write masking color register data enabled. write disabled bank active command with write masking color register data disabled. masking provides independent data
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Summary Byte SGRAM Basic Features Benefits
Features 256K SGRAM Benefits Better interaction between memory system without wait-state asynchronous DRAM. Interface Synchronous High speed vertical horizontal drawing. High operation frequency allows performance gain SCROLL, FILL, BitBLT. Bank Page Depth Total Page Depth Burst Length (Read) 2048 bytes 1,2,4,8 Full Page 1,2,4,8 Full Page BRSW Burst Type Latency Block Write Color Register Mask Register Sequential Interleave Columns DQM0-3 Mask function Write Pseudo-infinite length on-chip interleaving operation. Hidden activation precharge. High speed vertical horizontal drawing. High speed vertical horizontal drawing Programmable burst 1,2,4,8 full page transfer column addresses. Programmable burst 1,2,4,8 full page transfer column addresses. Switch burst length write without Compatible with Intel Motorola based system. Programmable latency. High speed FILL, CLEAR, Text with color registers. Maximum byte data transfers (e.g. 8bpp pixels) with plane byte masking functions. bank share. Write-per-bit capability (bit plane masking). banks share. Byte masking (pixel masking 8bpp system) data-out/in Each mask register directly controls corresponding plane.
Burst Length (Write)
Pixel Mask Block Write Byte masking (pixel masking 8bpp system) color
Basic feature Function Descriptions CLOCK Suspend
Click Suspended During Write (BL=4)
Clock Suspended During Read (BL=4)
Masked Internal Masked
DQ(CL2) DQ(CL3)
Written
Suspended Dout
Note: disable/enable=1 clock
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Operation
Write Mask (BL=4)
Read Mask (BL=4)
DQMi DQ(CL2) DQ(CL3)
Masked Hi-Z Hi-Z
Masked
Data-in Mask 0CLK
Data-out Mask
Read Mask (BL=4)
DQ(CL2) DQ(CL3) Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
Note There DQMi (I=0~3).
Each DQMi masks DQi' Byte, Pixel 8bbp). makes data Hi-Z after clocks which should masked
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Interrupt
Read intreupted Read (BL=4) DQ(CL2) DQ(CL3) tCCD
Note2
Note
Write interrupted (Block) Write
Note2
Write interrupted Read
Note2
tCCD
Note4
Note2
tCCD
tCCD
Pixel
Pixel
DQ(CL2) DQ(CL3)
tCDL Note3
tCDL
Note3
tCDL
Note3
Block Write Block Write Pixel
Note4
Pixel
tBWC Note5
Note Interrupt" possible stop burst read/write external command before burst. "CAS Interrupt" stop burst read/write access; read, write block write. tCCD delay. (=1CLK) tCDL Last data column address delay. 1CLK). Pixel Pixel mask. tBWC Block write minimum cycle time.
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Interrupt (II) Read Interrupted Write
CL=2, BL=4
iii) CL=3, BL=4
Hi-Z
Hi-Z
Hi-Z
Note
iii)
Hi-Z
Hi-Z
Note
Note prevent contention, there should least between data data out. prevent contention, should issued which makes least between data data out.
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Write Interrupted Precharge
Masked Note
Note
Note inhibit invalid write, should issued. This precharge command burst write command should same bank, otherwise precharge interrupt only another bank precharge dual banks operation.
Precharge
Normal Write (BL=4) tRDL Note Read (BL=4) DQ(CL2) DQ(CL3)
Note
Block Write Pixel tBPL Note
Auto Precharge
Normal Write (BL=4)
Note Auto Precharge Starts
Block Write 2,3) Pixel tBPL
Note
Read (BL=4) DQ(CL2) DQ(CL3)
Note Auto Precharge Starts
Auto Precharge Starts
Note tBPL Block write data-in command delay. Number valid output data after Precharge Latency respectively. active command precharge bank issued after from this point. read/write command other active bank issued from this point. burst read/write with auto precharge, interrupt same/another bank illegal. PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Burst Stop Precharge Interrupt
Write Interrupted Precharge (BL=4) tRDL
Note
Write Burst Stop (Full Page Only)
STOP
tBDL
Read Interrupted Precharge (BL=4) DQ(CL2) DQ(CL3)
Note
Read Burst Stop (Full Page Only) DQ(CL2)
STOP
Note
DQ(CL3)
SMRS
Mode Register
Note
Special Mode Register
SMRS SMRS SMRS
1CLK
1CLK 1CLK 1CLK 1CLK
Note 1.tRDL 1CLK, Last Data Precharge. tBDL 1CLK, Last Data Burst Stop Delay. Number valid output data after precharge burst stop latency=2,3 respectively. Both banks precharge necessary. issued only bank precharge state.
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Clock Suspend Exit Power Down Exit
Clock Suspend (=Active Power Down) Exit Internal
Note
Power Down (=Precharge Power Down) Exit
Internal
Note
Auto Refresh Self Refresh
Note
Auto Refresh
Internal
Note
Note
Note
Self Refresh
Note
Note Active power down more bank active state. Precharge power down both bank precharge state. auto refresh same refresh conventional DRAM. precharge commands required after Auto Refresh command. During from auto refresh command, other command accepted. Before executing auto/self refresh command, both banks must idle state. (S)MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry. During self refresh mode, refresh interval refresh operation performed internally. After self refresh entry, self refresh mode kept while LOW. During self refresh mode, inputs expect will don' cared, outputs will Hi-Z state. During from self refresh exit command, other command accepted. Before/After self refresh mode, burst auto refresh cycle cycles recommended.
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
About Burst Type Control
Basic MODE Sequential counting Interleave counting A3=" BURST SEQUENCE TABE.(BL=4,8) BL=1,2,4,8 full page wrap around. A3=" BURST SEQUENCE TABE.(BL=4,8) BL=4,8 BL=1,2 Interleave Counting Sequential Counting (See Interleave Counting Mode) Starting Address bits A0-2 should 000" 111" .@BL=8. 000" Increment Counting. LSB= 111" Decrement Counting. Example, (Assume Addresses except bits BL=8) write, LSB=" 000" Accessed Column order 0-1-2-3-4-5-6-7 read, LSB=" 111" Accessed Column order 7-6-5-4-3-2-1-0 BL=4, same applications possible. above example, Interleave Counting mode, confining starting address some values, PseudoDecrement Counting Mode realized. BURST SEQUENCE TABLE carefully. (See Sequential Counting Mode) A0-2 111" (See Full Page Mode) Using Full Page Mode Burst Stop Command, Binary Counting Mode realized. Sequential Counting Accessed Column order 3-4-5-6-7-1-2-3 (BL=8) Pseudo-Binary Counting, Accessed Column order 3-4-5-6-7-8-9-10 (Burst Stop command) Note. next column address Every cycle Read/Write Command with random column address realize Random Column Access. That similar Extended Data (EDO) Operation convention DRAM.
PseudoDecrement Sequential Counting
PseudoMODE
Pseudo-Binary Counting
Random MODE
Random column Access tCCD
About Burst Length Control
A2,1,0 000" auto precharge, tRAS should violated. A2,1,0 001" auto precharge, tRAS should violated. A2,1,0 010" A2,1,0 011" A2,1,0 111" Full Page Wrap around mode (Infinite burst length) should stopped burst stop, interrupt interrupt. A9=" BRSW Read burst 1,2,4,8, full page/write Burst auto precharge write, tRAS should violated. Column Block Write. A0-2 ignored. Burst length=1. Block Write tBWC should violated. auto precharge, tRAS should violated. tBDL=1, Valid after burst stop CL=2,3 respectively Burst Stop Using burst stop command, possible only full page burst length. Before burst, precharge command same bank Interrupt Stops read/write burst with precharge. (Interrupted Precharge) tRDL=1 with DQM, valid after burst stop CL=2,3 respectively During read/write burst with auto precharge, interrupt cannot issued. Before burst, read/write stops read/write burst starts read/write burst block write. Interrupt During read/write burst with auto precharge, interrupt issued.
Basic MODE
Special MODE
Random MODE
Interrupt MODE
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Mask Functions
Normal Write masking Mask Write Mode, selected planes keep original data. plane 0,3,7,9,15,22,24, keep original value. STEP SMRS (LMR) Load mask [31-0]=" Active with Writ Mode Enable Perform Normal Write ILLUSTRATION I/O(=DQ) External Data-in DQMi Mask Register Before Write After Write 11111111 DQM3=0 01111110 00000000 01111110 11111111 DQM2=0 10111111 00000000 10111111 0000000 DQM1=0 0111101 1111111 1000010 00000000 DQM0=1 01110110 11111111 11111111 Note
Block Write Pixel masking Pixel Data issued through pin, selected pixels keep original data. PIXEL MAPPING TABLE. Pixel 0,4,9,13,18, keep original white color. Assume 8bpp, White 0000,0000" 1010,0011" Green 1110,0001" Yellow 0000,1111" Blue 1100,0011" STEP SMRS(LCR) Load color (for 8bbp, through color loaded into color registers) Load(color3, color2, color1, color0) (Blue, Green, Yellow, Red) Active with Mask Write Mode Disable Block write with DQ[31-0] ILLUSTRATION I/O(=DQ) DQMi DQM3=0 DQM2=0 DQM1=0 DQM0=1 Color Register Color3=Blue Color2=Green Color1=Yellow Color0=Red White DQ24=H White DQ16=H White DQ8=H White DQ0=L Before White DQ25=H White DQ17=H White DQ9=L White DQ1=H Block White DQ26=H White DQ18=L White DQ10=H White DQ2=H Write White DQ27=L White DQ19=H White DQ11=H White DQ3=H White DQ28=H White DQ20=H White DQ12=H White DQ4=L White DQ29=H White DQ21=H White DQ13=L White DQ5=H (Pixel White DQ30=H White DQ22=L White DQ14=H White DQ6=H data) White DQ31=L White DQ23=H White DQ15=H White DQ7=H Blue Green Yellow White Blue Green White White Blue White Yellow White After White Green Yellow White Block Blue Green Yellow White Write Blue Green White White Blue White Yellow White White Green Yellow White Note Note byte masking. normal write, column selected among columns decoded A2-0 (000-111) block write, instead ignored address A2-0, DQ0-31 control each pixel.
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
(Continued)
Pixel masking Mask Write Mode, selected planes keep original data. Pixel Data issued through pin, selected pixels keep original data. PIXEL MAPPING TANLE. Assume 8bpp, White 0000,0000" 1010,0011" Green 1110,0001" Yellow 0000,1111" Blue 1100,0011" STEP SMRS (LCR) Load color (for 8bpp, through color0-3 loaded into color registers) Load (color3, color2, color1, color0) (Blue, Green, Yellow, Red) (LMR) Load mask, Mask[31-0] Byte 3:No Masking; Byte 2:I/O Masking; Byte 1:I/O Pixel Masking; Byte 0:DQM Byte Masking Active with Mask Write Mode Enable Block Write with DQ[31-0] (Pixel Mask) ILLUSTRATUON I/O(=DQ) Color Register DQMi Mask Register Before Write After Write Blue 11000011 DQM3=0 11111111 Yellow 00001111 Blue 11000011 Green 11100001 DQM2=0 11011101 Yellow 00001111 Blue 11000011 Yellow 00001111 DQM1=0 01000010 Green 11100001 10100011 10100011 DQM0=1 01110110 White 00000000 White 00000000 Note I/O(=DQ) DQMi DQM3=0 Color Register Color3=Blue Yellow DQ24=H Before Yellow DQ25=H Block Yellow DQ26=H Write Yellow DQ27=L Yellow DQ28=H Yellow DQ29=H (Pixel Yellow DQ30=H data) Yellow DQ31=L Blue Blue Blue After Yellow Block Blue Write Blue Blue Yellow Note PIXEL MASK DQM2=0 Color2=Green Yellow DQ16=H Yellow DQ17=H Yellow DQ18=H Yellow DQ19=H Yellow DQ20=H Yellow DQ21=H Yellow DQ22=H Yellow DQ23=H Blue Blue Blue Blue Blue Blue Blue Blue DQM1=0 Color1=Yellow Green DQ8=H Green DQ9=L Green DQ10=H Green DQ11=H Green DQ12=H Green DQ13=L Green DQ14=H Green DQ15=L Green Green Green Green DQM0=1 Color0=Red White DQ0=L White DQ1=H White DQ2=H White DQ3=H White DQ4=L White DQ5=H White DQ6=H White DQ7=H White White White White White White White White Note BYTE MASK
MASK
PIXEL MASK
Note byte masking. normal write, column selected among columns decoded A2-0 (000-111) block write, instead ignored address A2-0, DQ0-31 control each pixel.
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Power Sequence Auto Refresh
CLOCK
High level necessary
High level necessary
Precharge (All Bands)
Auto Refresh
Auto Refresh
High-Z
A9/AP
A10/BA
ADDR
PRELIMINARY (December, 1998, Version 0.0)
Mode Regiser Active (Write Enable Disable) Don't care
AMIC Technology, Inc.
A45L9332 Series
Single Read-Write-Read Cycles (Same Page) @CAS Latency=3, Burst Length=1
CLOCK tRAS
*Note
High
tRCD ADDR
*Note *Note
tCCD
*Note *Note *Note *Note
*Note
*Note
*Note
*Note
*Note *Note *Note *Note
tRAC tSAC tSLZ tSHZ
Active (Write Enable Disable)
Read
Write Block Write
Read Precharge
Active (Write Enable Disable Don't care
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Note inputs don' care when high high going edge. Bank active read/write controlled A10.
Active Read/Write Bank Bank
Enable disable auto precharge function controlled read/write command. Operation Disable auto precharge, leave bank active burst. Disable auto precharge, leave bank active burst. Enable auto precharge, precharge bank burst. Enable auto precharge, precharge bank burst.
control bank precharge when precharge command asserted. Precharge Bank Bank Both Bank
Enable disable Write-per function controlled Active command. Operation Bank active, disable write function bank Bank active, enable write function bank Bank active, disable write function bank Bank active, enable write function bank
Block write/normal write controlled Operation Normal write Block write Minimum cycle time tCCD tBWC
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Read Write Cycle Same Bank @Burst Length=4
CLOCK
tRCD *Note
High
*Note
ADDR
tRAC *Note tSAC tRAC *Note tSAC *Note tRDL *Note tRDL
tSHZ
tSHZ
Active (A-Bank)
Read (A-Bank)
Precharge (A-Bank)
Active (A-Bank)
Write (A-Bank)
Precharge (A-Bank) Don't care
*Note Minimum cycle times required complete internal DRAM operation. precharge interrupt burst cycle. [CAS latency-1] valid output data available after enters precharge. Last valid output will Hi-Z after tSHZ from clock. Access time from address. tCC*(tRCD latency-1) tSAC Output will Hi-Z after burst. (1,2,4 Full page burst, burst wrap-around.
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Page Read Write Cycle Same Bank @Burst Length=4
CLOCK
High
tRCD
*Note
ADDR
tCDL tRDL
*Note
*Note1 *Note3
(CL=2)
(CL=3)
Active (A-Bank)
Read (A-Bank)
Read (A-Bank)
Write (A-Bank)
Write (A-Bank)
Precharge (A-Bank)
Don't care
*Note write data before burst read ends, should asserted three cycle prior write command avoid contention. precharge will interrupt writing. Last data input, tRDL before precharge, will written. should mask invalid input data precharge command cycle when asserting precharge before burst. Input data after precharge cycle will masked internally.
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Block Write Cycle (with Auto Precharge)
CLOCK
High
*Note ADDR
tBWC
*Note
Pixel Mask Pixel Mask Pixel Mask Pixel Mask
Active with Write-per-Bit Enable (A-Bank)
Masked Block Write (A-Bank) Masked Block Write with Auto Precharge (A-Bank)
Active (B-Bank)
Block Write with Auto Precharge (B-Bank) Block Write (B-Bank) Don't care
*Note Column Mask (DQi=L Mask, DQi=H Mask) Block Write, CA0-2 ignored.
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
SMRS Block/Normal Write Burst Length=4
CLOCK
High
*Note1 A0-2
A3,4,7,8
Color
Mask
Pixel Mask
Mask
Color
DBa0 DBa1
DBa2
DBa3
Load Color Register
Load Color Register Masked Bolck Write (A-Bank)
Active with WPB* Enable (A-Bank)
Active with WPB* Enable (B-Bank)
Load Color Register Masked Write with Auto Precharge (B-Bank)
WPB* Write-Per-Bit
Load Mask Register
Don't care
Note next clock special mode command, command possible.
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Page Read Cycle Different Bank @Burst Length
CLOCK
*Note
High
*Note
ADDR
(CL=2)
QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1
(CL=3)
QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1
Active (A-Bank)
Active (B-Bank) Read (A-Bank)
Read (B-Bank)
Read (A-Bank)
Read (B-Bank)
Read (A-Bank)
Precharge (A-Bank)
Don't care
Note don' care when RAS,
high clock high going edge.
interrupt burst read precharge, both read precharge banks must same.
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Page Write Cycle Different Bank @Burst Length=4
CLOCK
High
ADDR
tCDL
Mask
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DAc2 DAc3 DBd0 DBd1 DBd2 DBd3
Load Mask Register Active with Write-Per-Bit enable (A-Bank)
Active (B-Bank) Masked Write (A-Bank)
Write (B-Bank)
Masked Write with auto precharge (A-Bank)
Write with auto Precharge (B-Bank)
Don't care
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Read Write Cycle Different Bank @Burst Length=4
CLOCK
High
ADDR
tCDL *Note
(CL=2)
QAa0 QAa1 QAa2 QAa3
DBb0 DBb1 DBb2 DBb3
QAc0 QAc1 QAc2
(CL=3)
QAa0 QAa1 QAa2 QAa3
DBb0 DBb1 DBb2 DBb3
QAc0 QAc1
Active (A-Bank)
Read (A-Bank)
Precharge (A-Bank)
Write (B-Bank)
Read (A-Bank)
Active (B-Bank)
Active (A-Bank) Don't care
Note tCDL should complete write.
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Read Write Cycle with Auto Precharge @Burst Length=4
CLOCK
High
ADDR
DQMi
(CL=2)
QAa0
QAa1
QAa2 QAa3
DBb0
DBb1
DBb2
DBb3
(CL=3)
QAa0
QAa1 QAa2 QAa3
DBb0 DBb1
DBb2
DBb3
Active (A-Bank)
Read with Auto Precharge (A-Bank) Active (B-Bank)
Auto Precharge Start Point (A-Bank)
Write with Auto Precharge (B-Bank)
Auto Precharge Start Point (B-Bank)
Don't care
*Note tRCD should controlled meet minimum tRAS before internal precharge start. case Burst Length=1 BRSW mode Block write)
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Read Write Cycle with Auto Precharge @Burst Length=4
CLOCK
High
ADDR
(CL=2)
(CL=3)
Active (A-Bank)
Read with Auto Charge (A-Bank)
Read without Auto Precharge (B-Bank) Auto Precharge Strart Point (A-Bank) *Note
Precharge (B-Bank)
Active (A-Bank)
Write with Auto Precharge (A-Bank)
Active (B-Bank) Don't care
Note When Read(Write) command with auto precharge issued A-Bank after Bank activation. read(Write) command without auto precharge issued B-Bank before Bank auto precharge starts, Bank auto precharge will start Bank read command input point. command issued Bank during after Bank auto precharge starts.
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Read Write Cycle with Auto Precharge @Burst Length=4
CLOCK
High
ADDR
(CL=2)
(CL=3)
Note
Active (A-Bank)
Read with Auto Preharge (A-Bank)
Auto Precharge Read with Start Point Auto Precharge (B-Bank) (A-Bank) Active (B-Bank)
Auto Precharge Start Point (B-Bank)
Don't care
Note command A-bank allowed this period. determined from auto precharge start point
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Read Interrupted Precharge Command Read Burst Stop Cycle (@Full Page Only)
CLOCK
High
ADDR
Note Note
Note
(CL=2)
QAa0 QAa1 QAa2 QAa3 QAa4
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
(CL=3)
QAa0
QAa1 QAa2 QAa3 QAa4
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
Active (A-Bank)
Read (A-Bank)
Burst Stop
Read (A-Bank)
Precharge (A-Bank)
Don't care
Note full page mode, burst wrap-around burst. auto precharge impossible. About valid after burst stop, same case interrupt.
Both cases illustrated above timing diagram. label them. burst write, burst stop interrupt should compared carefully. Refer timing diagram Full page write burst stop cycle"
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Write Interrupted Precharge Command Write Burst Stop Cycle Full Page Only)
CLOCK
High
ADDR
Note Note
tBDL tRDL
Note
Note
DAa0 DAa1 DAa2 DAa3 DAa4
DAb0 DAb1 DAb2 DAb3 DAb4 DAb5
Active (A-Bank)
Write (A-Bank)
Burst Stop
Write (A-Bank)
Precharge (A-Bank)
Don't care
Note full page mode, burst wrap-around burst. auto precharge impossible. Data-in cycle burst stop command cannot written into corresponding memory cell. defined parameter tBDL(=1CLK). Data-in cycle interrupted precharge cannot written into corresponding memory cell. defined parameter tRDL(1=CLK). write interrupted precharge command needed ensure tRDL 1CLK. should mask invalid input data precharge command cycle when asserting precharge before burst. Input data after precharge cycle will masked internally. Burst stop valid only full page burst length.
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Burst Read Single Write Cycle @Burst Length=2, BRSW
CLOCK
High
Note
ADDR
(CL=2)
DAa0
QAb0
QAb1
DBc0
QAd0
QAd1
(CL=3)
DAa0
QAb0 QAb1
DBc0
QAd0
QAd1
Active (A-Bank)
Active (B-Bank)
Active (A-Bank)
Read (A-Bank)
Precharge (A-Bank)
Write (A-Bank)
Read with Auto Precharge (A-Bank)
Write with Auto Precharge (B-Bank) Don't care
Note BRSW mode enabled setting High"at (Mode Register Set). BRSW Mode, burst length write fixed regardless programed burst length. When BRSW write command with auto precharge executed, keep mind that tRAS should violated. Auto precharge executed burst-end cycle, case BRSW write command, next cycle starts precharge. function also possible BRSW mode.
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Clock Suspension Operation Cycle @CAS Latency Burst Length=4
CLOCK
ADDR
Note
tSHZ
tSHZ
Active
Read
Clock Suspension
Read
Read Write
Write Clock Suspension
Don't care
Note needed prevent contention.
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Active/Precharge Power Down Mode @CAS Lantency=2, Burst Length=4
CLOCK
Note
Note
*Note
ADDR
Precharge Power-down Entry Precharge Power-down Exit Active Active Power-down Entry
Read
Precharge
Active Power-down Exit Don't care
Note banks should idle state prior entering precharge power down mode. should high least 1CLK tSS"prior active command. Cannot violate minimum refresh specification. (32ms)
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Self Refresh Entry Exit Cycle
CLOCK
Note
Note
Note
Note
Note
Note
min.
Note
Note
Hi-Z
Hi-Z
Self Refresh Entry
Self Refresh Exit
ADDR
Note ENTER SELF REFRESH MODE with should same clock cycle. After clock cycle, inputs including system clock don' care except CKE. device remains self refresh mode long stays Low" (cf.) Once device enters self refresh mode, minimum tRAS required before exit from self refresh. EXIT SELF REFRESH MODE System clock restart stable before returning high. starts from high. Minimum required after going high complete self refresh exit. cycle burst auto refresh required before self refresh entry after self refresh exit. system uses burst refresh.
PRELIMINARY (December, 1998, Version 0.0)
Auto Refresh Don't care
AMIC Technology, Inc.
A45L9332 Series
Mode Register Cycle
CLOCK
Auto Refresh Cycle
*Note
High
High
Note
Note
Command
Auto Refresh
Hi-Z
Hi-Z
ADDR
Command Don't care
Both banks precharge should completed before Mode Register cycle auto refresh cycle.
MODE REGISTER CYCLE Note mode register. Minimum clock cycles should before activation.
activation same clock cycle with address will internal
Please refer Mode Register table.
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Function Truth Table (Table
Current State
Address (A10) Code Code CA,AP CA,AP CA,AP Code CA,AP CA,AP CA,AP ILLEGAL ILLEGAL
Action
Note
Active; Latch Address; Non-IO Mask Active; latch Address; Mask ILLEGAL Auto Refresh Self Refresh ILLEGAL Mode Register Access Special Mode Register Access ILLEGAL Begin Read; Latch Determine ILLEGAL Begin Write; Latch Determine Block Write; Latch Determine ILLEGAL Precharge ILLEGAL ILLEGAL ILLEGAL Special Mode Register Access NOP(Continue Burst Active) NOP(Continue Burst Active) Term burst Active ILLEGAL Term burst; Begin Read; Latch Determine ILLEGAL Term burst; Begin Write; Latch Determine Term burst; Block Write; Latch Determine ILLEGAL Term Burst; Precharge timing Reads ILLEGAL ILLEGAL
IDLE
Active
Read
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Function Truth Table (Table Continued)
Current State
Address (A10) CA,AP CA,AP CA,AP CA,AP CA,AP RA,PA CA,AP CA,AP RA,PA CA,AP
Action NOP(Continue Burst Active) NOP(Continue Burst Active) Term burst Active) ILLEGAL Term burst; Begin Read; Latch Determine ILLEGAL Term burst; Begin Write; Latch Determine Term burst; Block Write; Latch Determine ILLEGAL Term Burst; Precharge timing Writes ILLEGAL ILLEGAL NOP(Continue Burst Precharge) NOP(Continue Burst Precharge) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP(Continue Burst Precharge) NOP(Continue Burst Precharge) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Idle after Idle after ILLEGAL ILLEGAL ILLEGAL Idle after ILLEGAL
Note
Write Read with Auto Precharge Write with Auto Precharge Precharge
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Function Truth Table (Table Continued)
Current State
Address (A10)
Action Active after tBWC Active after tBWC ILLEGAL
Note
Block Write Recovering
CA,AP ILLEGAL ILLEGAL Term Block Write: Precharge timing Block Write ILLEGAL Active after tRCD Active after tRCD ILLEGAL
Activating
CA,AP ILLEGAL ILLEGAL ILLEGAL ILLEGAL Idle after Idle after ILLEGAL ILLEGAL ILLEGAL
Refreshing
Abbreviations Address (A0~A9) Operation Command
Bank Address (A10) Column Address (A0~A7)
Precharge (A9) Auto Precharge (A9)
Note: entries assume that active (High) during preceding clock cycle current clock cycle. Illegal bank specified state Function legal bank indicated depending state that bank. Must satisfy contention, turn around, and/or write recovery requirements. bank precharging idle state. precharge bank indicated (and PA). Illegal banks idle. Legal only banks idle active state.
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Function Truth Table (Table
Current State Self Refresh Both Bank Precharge Power Down Banks Idle State Other than Listed Above
Address INVALID
Action
Note
Exit Self Refresh after Exit Self Refresh after ILLEGAL ILLEGAL ILLEGAL NOP(Maintain Self Refresh) INVALID Exit Power Down Exit Power Down ILLEGAL ILLEGAL ILLEGAL NOP(Maintain Power Down Mode) Refer Table Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Enter Self Refresh ILLEGAL Refer Operations Table Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain clock Suspend
Abbreviations Banks Idle Note: After CKE' high transition exit self refresh mode. time tRC(min) elapse after CKE' high transition issue command. high transition asynchronous restarts internal clock. minimum setup time clock" must satisfied before command other than exit. Power-down self refresh entered only from banks idle state. Must legal command.
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Ordering Information
Part A45L9332F-7 A45L9332E-7 A45L9332F-8 A45L9332E-8 A45L9332F-10 A45L9332E-10 (Height 3.0mm Max) LQFP (Height 1.4mm Max) Cycle Time (ns) Clock Frequency (MHz) Access Time Package LQFP LQFP LQFP
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Package Information 100L Outline Dimensions
unit: inches/mm
Symbol
Dimensions inches Min. 0.004 0.107 0.010 0.0057 0.903 0.783 0.667 0.547 0.020 0.025 0.057 Nom. 0.112 0.006 0.913 0.787 0.677 0.551 0.026 0.031 0.063 Max. 0.117 0.014 0.0063 0.923 0.791 0.681 0.555 0.032 0.037 0.069 0.004
Dimensions Min. 0.100 2.723 0.26 0.142 22.950 19.900 16.950 13.900 0.500 0.650 1.450 Nom. 2.85 0.150 23.200 20.000 17.200 14.000 0.650 0.800 1.600 Max. 2.977 0.36 0.158 23.450 20.100 17.450 14.100 0.800 0.950 1.750 0.100
Notes: Dimensions include mold protrusion. Dimensions does include dambar protrusion. Total excess dimension maximum material condition. Dambar cannot located lower radius foot.
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.
A45L9332 Series
Package Information LQFP 100L Outline Dimensions
unit: inches/mm
Symbol
Dimensions inches Min. 0.002 0.053 0.011 0.005 0.860 0.783 0.624 0.547 Nom. 0.055 0.013 0.866 0.787 0.630 0.551 0.026 0.018 0.024 0.039 3.5° 0.004 0.030 Max. 0.057 0.015 0.008 0.872 0.791 0.636 0.555
Dimensions Min. 0.05 1.35 0.27 0.12 21.85 19.90 15.85 13.90 Nom. 1.40 0.32 22.00 20.00 16.00 14.00 0.65 0.45 0.60 1.00 3.5° 0.75 Max. 1.45 0.37 0.20 22.15 20.10 16.15 14.10
Notes: Dimensions include mold protrusion. Dimensions does include dambar protrusion. Total excess dimension maximum material condition. Dambar cannot located lower radius foot.
PRELIMINARY (December, 1998, Version 0.0)
AMIC Technology, Inc.

Document Title 256K 32Bit Banks Synchronous Graphic Revision History

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