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PowerPC 405GPr Embedded Processor Data Sheet

PowerPC 405GPr Embedded Processor Data Sheet

Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Features
· IBM PowerPC 405 32-bit RISC processor core operating up to 333MHz with larger 16KB D-cache · PC-133 synchronous DRAM (SDRAM) interface - 32-bit interface for non-ECC applications - 40-bit interface serves 32 bits of data plus 8 check bits for ECC applications · 4KB on-chip memory (OCM) · Programmable timers · External peripheral bus - Flash ROM / Boot ROM interface - Direct support for 8-, 16-, or 32-bit SRAM and external peripherals - Up to eight devices - External Mastering supported · DMA support for external peripherals, internal UART and memory - Scatter-gather chaining supported - Four channels · PCI Revision 2.2 compliant interface (32-bit, up to 66MHz) · Two serial ports (16550 compatible UART) · One IIC interface · General purpose I / O (GPIO) available · Supports JTAG for board level testing · Internal processor local Bus (PLB) runs at SDRAM interface frequency · Supports PowerPC processor boot from PCI memory · Unique software-accessible 64-bit chip ID number (ECID). - Synchronous or asynchronous PCI Bus interface - Use internal or external PCI Bus Arbiter · Ethernet 10 / 100Mbps (full-duplex) support with media independent interface (MII) · Programmable interrupt controller supports 13 external and 19 internal edge triggered or levelsensitive interrupts
Description
Designed specifically to address embedded applications, the PowerPC 405GPr (PPC405GPr) provides a high-performance, low-power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation requirements. This chip contains a high-performance RISC processor core, SDRAM controller, PCI bus interface, Ethernet interface, control for external ROM and peripherals, DMA with scatter-gather support, serial ports, IIC interface, and general purpose I / O. Technology: IBM CMOS SA-27E, 0.18 µm (0.11 µm Leff) Package: 456-ball (35mm or 27mm) enhanced plastic ball grid array (E-PBGA) Power (typical): 1.1W at 266MHz
While the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made.
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Contents
Tables
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Figures
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Ordering, PVR, and JTAG Information
Processor Frequency 266MHz 266MHz 266MHz 266MHz 333MHz 333MHz 333MHz 333MHz Rev Level A A A A A A A A
Product Name PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr
Order Part Number1 IBM25PPC405GPr-3BA266C IBM25PPC405GPr-3BA266CZ IBM25PPC405GPr-3DA266C IBM25PPC405GPr-3DA266CZ IBM25PPC405GPr-3BA333C IBM25PPC405GPr-3BA333CZ IBM25PPC405GPr-3DA333C IBM25PPC405GPr-3DA333CZ
Package 35mm, 456 E-PBGA 35mm, 456 E-PBGA 27mm, 456 E-PBGA 27mm, 456 E-PBGA 35mm, 456 E-PBGA 35mm, 456 E-PBGA 27mm, 456 E-PBGA 27mm, 456 E-PBGA
PVR Value 0x50910950 0x50910950 0x50910950 0x50910950 0x50910950 0x50910950 0x50910950 0x50910950
JTAG ID 0x14088049 0x14088049 0x14088049 0x14088049 0x14088049 0x14088049 0x14088049 0x14088049
Note 1: Z at the end of the Order Part Number indicates a tape and reel shipping package. Otherwise, the chips are shipped in a tray.
IBM25PPC405GPr-3BA266Cx
Package B: 35mm, 456 E-PBGA D: 27mm, 456 E-PBGA
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
PPC405GPr Embedded Controller Functional Block Diagram
Universal Interrupt Controller Clock Control Reset Timers MMU Power Mgmt DOCM IOCM OCM SRAM DCRs OCM Control GPIO IIC UART UART
PPC405 Processor Core JTAG 16KB D-Cache DCU Trace ICU
DCR Bus
16KB I-Cache
On-chip Peripheral Bus (OPB)
DMA Controller (4-Channel)
OPB Bridge
Ethernet
Arb Code Decompression (CodePack)
Processor Local Bus (PLB)
SDRAM Controller
External Bus Controller
External Bus Master Controller
PCI Bridge
13-bit addr 32-bit data
32-bit addr 32-bit data
66 MHz max (async) 33 MHz max (sync)
The PPC405GPr is designed using the IBM Microelectronics Blue Logic methodology in which major functional blocks are integrated together to create an application-specific ASIC product. This approach provides a consistent way to create complex ASICs using IBM CoreConnect Bus Architecture.
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Address Map Support
The PPC405GPr incorporates two simple and separate address maps. The first address map defines the possible use of address regions that the processor can access. The second address map is for Device Configuration Registers (DCRs). The DCRs are accessed by software running on the PPC405GPr processor through the use of mtdcr and mfdcr instructions.
System Memory Address Map 4GB System Memory
Function Subfunction SDRAM, External Peripherals, and PCI Memory Note: Any of the address ranges listed at right may be use for any of the above functions.
Start Address 0x00000000 0xE8010000 0xEC000000 0xEEE00000 0xEF500000 0xEF900000 0xFFE00000 0xFFFE0000 0xE8000000 0xE8800000 0xEEC00000 0xEED00000 0xEF400000 0xEF600300 0xEF600400 0xEF600500 0xEF600600 0xEF600700 0xEF600800
End Address 0xE7FFFFFF 0xE87FFFFF 0xEEBFFFFF 0xEF3FFFFF 0xEF5FFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xE800FFFF 0xEBFFFFFF 0xEEC00007 0xEED00003 0xEF40003F 0xEF600307 0xEF600407 0xEF60051F 0xEF60063F 0xEF60077F 0xEF6008FF
Size 3712MB 8MB 44MB 6MB 1MB 263MB 2MB 128KB 64KB 56MB 8B 4B 64B 8B 8B 32B 64B 128B 256B
General Use
Boot-up
Peripheral Bus Boot PCI Boot PCI I / O PCI I / O
Configuration Registers Interrupt Acknowledge and Special Cycle Local Configuration Registers UART0 UART1 IIC0 OPB Arbiter GPIO Controller Registers Ethernet Controller Registers
Internal Peripherals
Notes: 1. When peripheral bus boot is selected, peripheral bank 0 is automatically configured at reset to the address range listed above. 2. If PCI boot is selected, a PLB-to-PCI mapping is automatically configured at reset to the address range listed above. 3. After the boot process, software may reassign the boot memory regions for other uses. 4. All address ranges not listed above are reserved.
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
DCR Address Map 4KB Device Configuration Registers
Function Total DCR Address Space By function: Reserved Memory Controller Registers External Bus Controller Registers Decompression Controller Registers Reserved On-Chip Memory Controller Registers Reserved PLB Registers Reserved OPB Bridge Out Registers Electronic Chip ID (ECID) Reserved Clock, Control, Interrupt Routing, and Reset Power Management Interrupt Controller Reserved DMA Controller Registers Reserved Ethernet MAL Registers Reserved Notes: 1. DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit (word) register, or 1 kiloword (KW) (which equals 4 KB). 0x000 0x010 0x012 0x014 0x016 0x018 0x020 0x080 0x090 0x0A0 0x0A8 0x0AA 0x0B0 0x0B8 0x0C0 0x0D0 0x100 0x140 0x180 0x200 0x00F 0x011 0x013 0x015 0x017 0x01F 0x07F 0x08F 0x09F 0x0A7 0x0A9 0x0AF 0x0B7 0x0BF 0x0CF 0x0FF 0x13F 0x17F 0x1FF 0x3FF 16W 2W 2W 2W 2W 8W 96W 16W 16W 8W 2W 6W 8W 8W 16W 48W 64W 64W 128W 512W
Start Address 0x000
End Address 0x3FF
Size 1KW (4KB)1
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
On-Chip Memory (OCM)
The OCM feature comprises a memory controller and a one-port 4KB static RAM (SRAM) accessed by the processor core. Features include: · Low-latency access to critical instructions and data · Performance identical to cache hits without misses · Contents change only under program control
PLB to PCI Interface
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
- PCI interrupt acknowledge - PCI special cycle · Supports PCI target access to all PLB address spaces · Supports PowerPC processor boot from PCI memory
SDRAM Memory Controller
The PPC405GPr Memory Controller core provides a low latency access path to SDRAM memory. A variety of system memory configurations are supported. The memory controller supports up to four physical banks. Up to 256MB per bank are supported, up to a maximum of 1GB. Memory timings, address and bank sizes, and memory addressing modes are programmable. Features include: · 11x8 to 13x11 addressing for SDRAM (2- and 4-bank) · 32-bit memory interface support · Programmable address compare for each bank of memory · Industry standard 168-pin DIMMS are supported (some configurations) · Both 266 and 333 MHz PPC405GPrs support up to 133 MHz memory with PC-133 support · 4MB to 256MB per bank · Programmable address mapping and timing · Auto refresh · Page mode accesses with up to 4 open pages · Power management (self-refresh) · Error checking and correction (ECC) support - Standard single-error correct, double-error detect coverage - Aligned nibble error detect - Address error logging
External Peripheral Bus Controller (EBC)
· Supports eight banks of ROM, EPROM, SRAM, Flash memory, or slave peripherals · Up to 66MHz operation · Burst and non-burst devices · 8-, 16-, 32-bit byte-addressable data bus width support · Latch data on Ready, synchronous or asynchronous
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
· Programmable 2K clock time-out counter with disable for Ready · Programmable access timing per device - 0-255 wait states for non-bursting devices - 0-31 burst wait states for first access and up to 7 wait states for subsequent accesses - Programmable CSon, CSoff relative to address - Programmable OEon, WEon, WEoff (0 to 3 clock cycles) relative to CS · Programmable address mapping · Peripheral Device pacing with external "Ready" · External master interface - Write posting from external master - Read prefetching on PLB for external master reads - Bursting capable from external master - Allows external master access to all non-EBC PLB slaves - External master can control EBC slaves for own access and control
DMA Controller
· Supports the following transfers: - Memory-to-memory transfers - Buffered peripheral to memory transfers - Buffered memory to peripheral transfers · Four channels · Scatter / gather capability for programming multiple DMA operations · 8-, 16-, 32-bit peripheral support (OPB and external) · 32-bit addressing · Address increment or decrement · Internal 32-byte data buffering capability · Supports internal and external peripherals · Support for memory mapped peripherals · Support for peripherals running on slower frequency buses
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Serial Interface
· One 8-pin UART and one 4-pin UART interface provided · Selectable internal or external serial clock to allow a wide range of baud rates · Register compatibility with NS16550 register set · Complete status reporting capability · Transmitter and receiver are each buffered with 16-byte FIFOs when in FIFO mode · Fully programmable serial-interface characteristics · Supports DMA using internal DMA engine
IIC Bus Interface
· Compliant with Phillips® Semiconductors I2C Specification, dated 1995 · Operation at 100kHz or 400kHz · 8-bit data · 10- or 7-bit address · Slave transmitter and receiver · Master transmitter and receiver · Multiple bus masters · Supports fixed VDD IIC interface · Two independent 4 x 1 byte data buffers · Fifteen memory-mapped, fully programmable configuration registers · One programmable interrupt request signal · Provides full management of all IIC bus protocol · Programmable error recovery
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
General Purpose IO (GPIO) Controller
· Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus master accesses · 23 of 24 GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO capabilities acts as a GPIO or is used for another purpose. The 23 GPIOs are multiplexed with: - 7 of 8 chip selects - All 13 external interrupts - All nine instruction trace pins · Each GPIO output is separately programmable to emulate an open-drain driver (i.e., drives to zero, threestated if output bit is 1)
Universal Interrupt Controller (UIC)
The Universal Interrupt Controller (UIC) provides the control, status, and communications necessary between the various sources of interrupts and the local PowerPC processor. Features include: · Supports 13 external and 19 internal interrupts · Seven of the 13 interrupts are mapped to the same GPIOs as the PPC405GP. · The other six interrupts can be mapped to any of the GPIOs. · Edge triggered or level-sensitive · Positive or negative active · Non-critical or critical interrupt to processor core · Programmable critical interrupt priority ordering · Programmable critical interrupt vector for faster vector processing
10 / 100 Mbps Ethernet MAC
· Capable of handling full / half duplex 100Mbps and 10Mbps operation · Uses the medium independent interface (MII) to the physical layer (PHY not included on chip)
· IEEE 1149.1 test access port · IBM RISCWatch debugger support · JTAG Boundary Scan Description Language (BSDL)
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
27mm, 456-Ball E-PBGA Package
Top View
Ejector Mark 1.80 x 0.10
Small Radius Corner Corresponds to A1 Ball Location Index Mark 1.10 16.00 24.0 REF
Bottom View
Note: All dimensions are in mm.
27.0 25.0 0.35 C
Thermal Balls
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
35mm, 456-Ball E-PBGA Package
Top View
Reserved Area for Ejector Pin Mark x 4 TYP Corner Shape is Chamferred or Rounded
Gold Gate Release Corresponds to A1 Ball Location
33.5 REF
17.5 TYP
Note: All dimensions are in mm.
0.20 35.0 31.75 A
0.20 C 0.25 C 0.35 C
Bottom View
1.27 TYP
Mold Compound
PCB Substrate
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Pin Lists
The PPC405GPr embedded controller is available as a 456-ball E-PBGA package. The 456-ball package is available in two sizes-35 millimeters and 27 millimeters. In this section there are two tables that correlate the external signals to the physical package pin (ball) on which they appear. The following table lists all the external signals in alphabetical order and shows the ball number on which the signal appears. Multiplexed signals are shown with the default signal (following reset) not in brackets and the alternate signal in brackets. Multiplexed signals appear alphabetically multiple times in the list-once for each signal name on the ball. The page number listed gives the page in "Signal Functional Description" on page 30 where the signals in the indicated interface group begin.
Signals Listed Alphabetically
Signal Name AGND AVDD BA0 BA1 BankSel0 BankSel1 BankSel2 BankSel3 BE0PCIC0 BE1PCIC1 BE2PCIC2 BE3PCIC3 BusReq CAS ClkEn0 ClkEn1 DMAAck0 DMAAck1 DMAAck2 DMAAck3 DMAReq0 DMAReq1 DMAReq2 DMAReq3 DQM0 DQM1 DQM2 DQM3 DQMCB ECC0 ECC1 ECC2 ECC3 ECC4 ECC5 ECC6 ECC7 EMCMDClk EMCMDIOPHYMDIO Ball E22 D25 AB24 AC24 AD17 AF17 AE15 AC14 D19 F24 K24 R26 R3 AB23 AB25 AC25 D16 B15 B14 C12 C16 D14 C11 A7 AC12 AC10 AC6 AA3 AC15 AE14 AF15 AF14 AD13 AF13 AF12 AE13 AD12 H24 AD26
(Part 1 of 10)
Interface Group Page 35 35 32
System System SDRAM
SDRAM
PCI External MASTER Peripheral SDRAM SDRAM
External SLAVE Peripheral
SDRAM SDRAM
SDRAM
Ethernet Ethernet
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name EMCTxD0 EMCTxD1 EMCTxD2 EMCTxD3 EMCTxEn EMCTxErr EOT0 / TC0 EOT1 / TC1 EOT2 / TC2 EOT3 / TC3 ExtAck ExtReq ExtReset Ball J26 L25 L24 P25 K23 K25 F3 G2 V2 Y1 Y3 Y4 T3 Ethernet Ethernet Ethernet External SLAVE Peripheral External MASTER Peripheral External MASTER Peripheral External MASTER Peripheral
(Part 2 of 10)
Interface Group Page 31 31 31 32 34 34 34
A1 A2 A6 A11 A16 A19 A21 A26 B2 B25 B26 C3 C24 D4 D23 E5 E9 E13 E14 E18 Ground F1 Notes: F26 H1 1. L11-L16, M11-M16, N11-N16, P11-P16, R11-R16, and T11-T16 are also J5 thermal balls. J22 L1 L11-L16 L26 M11-M16 N5 N11-N16 N22 P5 P11-P16 P22 R11-R16 T1 T11-T16 T26 V5 V22 W26 AA1 AA26 AB5
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name Ball AB9 AB13 AB14 AB18 AB22 AC4 AC23 AD3 AD24 AE1 AE2 AE25 AF1 AF6 AF8 AF11 AF16 AF21 AF25 AF26 C19 D18 C20 A22 AF18 AC9 AE8 AF5 AC7 AB3 C4 C5 A4 B9 B10 A9 B11 V25 V23 W24 W25 Y24 Y25 AA24 D20 AB26 U2 T2 V1 AD6 AE7 V25 V23 W24 W25 Y24 Y25 AA24
(Part 3 of 10)
Interface Group Page
Ground Notes: 1. L11-L16, M11-M16, N11-N16, P11-P16, R11-R16, and T11-T16 are also thermal balls. 37
GntPCIReq0 GPIO1TS1E GPIO2TS2E GPIO3TS1O GPIO4TS2O GPIO5TS3 GPIO6TS4 GPIO7TS5 GPIO8TS6 GPIO9TrcClk GPIO10PerCS1 GPIO11PerCS2 GPIO12PerCS3 GPIO13PerCS4 GPIO14PerCS5 GPIO15PerCS6 GPIO16PerCS7 GPIO17IRQ0 GPIO18IRQ1 GPIO19IRQ2 GPIO20IRQ3 GPIO21IRQ4 GPIO22IRQ5 GPIO23IRQ6 GPIO24 Halt HoldAck HoldPri HoldReq IICSCL IICSDA IRQ0GPIO17 IRQ1GPIO18 IRQ2GPIO19 IRQ3GPIO20 IRQ4GPIO21 IRQ5GPIO22 IRQ6GPIO23
System
System External MASTER Peripheral External MASTER Peripheral External MASTER Peripheral Internal Peripheral Internal Peripheral
Interrupts
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name MemAddr0 MemAddr1 MemAddr2 MemAddr3 MemAddr4 MemAddr5 MemAddr6 MemAddr7 MemAddr8 MemAddr9 MemAddr10 MemAddr11 MemAddr12 MemClkOut0 MemClkOut1 MemData0 MemData1 MemData2 MemData3 MemData4 MemData5 MemData6 MemData7 MemData8 MemData9 MemData10 MemData11 MemData12 MemData13 MemData14 MemData15 MemData16 MemData17 MemData18 MemData19 MemData20 MemData21 MemData22 MemData23 MemData24 MemData25 MemData26 MemData27 MemData28 MemData29 MemData30 MemData31 Ball AE22 AC21 AE21 AD21 AF22 AE20 AC19 AE19 AD19 AC18 AF19 AD18 AC17 AC26 AA23 AC13 AE12 AD11 AC11 AF10 AE11 AD10 AF9 AD9 AE9 AD8 AF7 AC8 AD7 AE6 AE5 AE4 AD5 AD4 AC5 AD1 AB2 AA4 AA2 AB1 Y2 W4 W2 W3 V4 W1 V3
(Part 4 of 10)
Interface Group Page
SDRAM Note: During a CAS cycle MemAddr0 is the least significant bit (lsb) on this bus.
SDRAM
SDRAM Note: MemData0 is the most significant bit (msb) on this bus.
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name Ball B17 C13 E6 E7 E8 E19 E20 E21 F5 F22 G5 G22 H5 H22 K2 N24 P3 U25 W5 W22 Y5 Y22 AA5 AA22 AB6 AB7 AB8 AB19 AB20 AB21 AD14 AE10 A17 B16 C17 A18 D17 C18 B18 A20 B21 A23 D21 B22 B23 C22 C26 F25 K26 L23 M25 M23 N25 M26 N26 P24 R24 R23 P23 R25 T24 U26 T25 V26
(Part 5 of 10)
Interface Group Page
Output driver voltage
PCIAD0 PCIAD1 PCIAD2 PCIAD3 PCIAD4 PCIAD5 PCIAD6 PCIAD7 PCIAD8 PCIAD9 PCIAD10 PCIAD11 PCIAD12 PCIAD13 PCIAD14 PCIAD15 PCIAD16 PCIAD17 PCIAD18 PCIAD19 PCIAD20 PCIAD21 PCIAD22 PCIAD23 PCIAD24 PCIAD25 PCIAD26 PCIAD27 PCIAD28 PCIAD29 PCIAD30 PCIAD31
PCI Note: PCIAD31 is the most significant bit (msb) on this bus.
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name PCIC0BE0 PCIC1BE1 PCIC2BE2 PCIC3BE3 PCIClk PCIDevSel PCIFrame PCIGnt0Req PCIGnt1 PCIGnt2 PCIGnt3 PCIGnt4 PCIGnt5 PCIIDSel PCIINTPerWE PCIIRDY PCIParity PCIPErr PCIReq0Gnt PCIReq1 PCIReq2 PCIReq3 PCIReq4 PCIReq5 PCIReset PCISErr PCIStop PCITRDY Ball D19 F24 K24 R26 B20 H25 J24 U23 T23 F23 H26 N23 M24 P26 C23 J23 E26 G25 C19 C21 B19 A24 G23 J25 B24 G24 H23 G26 PCI PCI PCI PCI
(Part 6 of 10)
Interface Group Page 30 30 30 30
PCI PCI PCI PCI PCI
PCI PCI PCI PCI
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name PerAddr0 PerAddr1 PerAddr2 PerAddr3 PerAddr4 PerAddr5 PerAddr6 PerAddr7 PerAddr8 PerAddr9 PerAddr10 PerAddr11 PerAddr12 PerAddr13 PerAddr14 PerAddr15 PerAddr16 PerAddr17 PerAddr18 PerAddr19 PerAddr20 PerAddr21 PerAddr22 PerAddr23 PerAddr24 PerAddr25 PerAddr26 PerAddr27 PerAddr28 PerAddr29 PerAddr30 PerAddr31 PerBLast PerClk PerCS0 PerCS1GPIO10 PerCS2GPIO11 PerCS3GPIO12 PerCS4GPIO13 PerCS5GPIO14 PerCS6GPIO15 PerCS7GPIO16 Ball D5 A3 B4 B5 D6 B6 C6 D7 A5 B7 C7 D8 B8 C8 D9 A8 C9 D10 C10 A10 D11 B12 D13 D12 B13 A12 A13 C14 A14 A15 C15 D15 F2 E4 B3 C4 C5 A4 B9 B10 A9 B11
(Part 7 of 10)
Interface Group Page
External SLAVE Peripheral
External SLAVE Peripheral External MASTER Peripheral
External SLAVE Peripheral
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name PerData0 PerData1 PerData2 PerData3 PerData4 PerData5 PerData6 PerData7 PerData8 PerData9 PerData10 PerData11 PerData12 PerData13 PerData14 PerData15 PerData16 PerData17 PerData18 PerData19 PerData20 PerData21 PerData22 PerData23 PerData24 PerData25 PerData26 PerData27 PerData28 PerData29 PerData30 PerData31 PerErr PerOE PerPar0 PerPar1 PerPar2 PerPar3 PerReady PerR / W PerWBE0 PerWBE1 PerWBE2 PerWBE3 PerWEPCIINT PHYCol PHYCrS PHYRxClk PHYMDIOEMCMDIO PHYRxD0 PHYRxD1 PHYRxD2 PHYRxD3 PHYRxDV PHYRxErr PHYTxClk RAS Ball U4 U3 U1 T4 R2 P4 R4 P2 R1 P1 N3 N1 M1 N2 M3 M4 N4 M2 L3 L4 K1 L2 K3 J1 K4 J3 J2 J4 H3 G1 H2 H4 B1 C2 D3 G4 G3 E1 E3 C1 D2 E2 F4 D1 C23 AA25 W23 AF20 AD26 AE23 AF23 AC20 AD20 V24 U24 E25 AF24
(Part 8 of 10)
Interface Group Page
External SLAVE Peripheral
External MASTER Peripheral External SLAVE Peripheral External SLAVE Peripheral External SLAVE Peripheral External SLAVE Peripheral External SLAVE Peripheral External SLAVE Peripheral Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet SDRAM
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name Ball C25 E23 E24 Y23 Y26 AF41 U23 A25 AD25 D22 AD22 AE24 AD23 D26 D24 AC22 AE26 D18 C20 A22 AF18 AC9 AE8 AF5 AC7 AB3 AB4 AE18 AE3 AF2 AD15 AD16 AE16 AF3 AC3 AC3 AD2 AD2 AC1 AC2 AE17 Other Notes: 1. AF4 must be tied to OVDD or GND. All other reserved pins should be left unconnected. PCI System System System JTAG JTAG JTAG System System JTAG JTAG
(Part 9 of 10)
Interface Group Page
Reserved
System
Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name Ball E10 E11 E12 E15 E16 E17 K5 K22 L5 L22 M5 M22 R5 R22 T5 T22 U5 U22 AB10 AB11 AB12 AB15 AB16 AB17 AC16
(Part 10 of 10)
Interface Group Page
Logic voltage
SDRAM
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Signals Listed by Ball Assignment
Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 Signal Name GND GND PerAddr1 PerCS3GPIO12 PerAddr8 GND DMAReq3 PerAddr15 PerCS6GPIO15 PerAddr19 GND PerAddr25 PerAddr26 PerAddr28 PerAddr29 GND PCIAD0 PCIAD3 GND PCIAD7 GND GPIO3TS1O PCIAD9 PCIReq3 SysClk GND PerErr GND PerCS0 PerAddr2 PerAddr3 PerAddr5 PerAddr9 PerAddr12 PerCS4GPIO13 PerCS5GPIO14 PerCS7GPIO16 PerAddr21 PerAddr24 Ball B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26
(Part 1 of 3)
Ball D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 Signal Name PerWBE3 PerWBE0 PerPar0 GND PerAddr0 PerAddr4 PerAddr7 PerAddr11 PerAddr14 PerAddr17 PerAddr20 PerAddr23 PerAddr22 DMAReq1 PerAddr31 DMAAck0 PCIAD4 GPIO1TS1E PCIC0BE0 GPIO24 PCIAD10 SysReset GND TmrClk AVDD TestEn PerPar3 PerWBE1 PerReady PerClk GND OVDD OVDD OVDD GND VDD VDD VDD GND Ball E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 F1 F2 F3 F4 F5 F22 F23 F24 F25 F26 G1 G2 G3 G4 G5 G22 G23 G24 G25 G26 H1 H2 H3 H4 H5 H22 Signal Name GND VDD VDD VDD GND OVDD OVDD OVDD AGND Reserved Reserved PHYTxClk PCIParity GND PerBLast EOT0 / TC0 PerWBE2 OVDD OVDD PCIGnt2 PCIC1BE1 PCIAD15 GND PerData29 EOT1 / TC1 PerPar2 PerPar1 OVDD OVDD PCIReq4 PCISErr PCIPErr PCITRDY GND PerData30 PerData28 PerData31 OVDD OVDD
Signal Name DMAAck2 DMAAck1 PCIAD1 OVDD PCIAD6 PCIReq2 PCIClk PCIAD8 PCIAD11 PCIAD12 PCIReset GND GND PerR / W PerOE GND PerCS1GPIO10 PerCS2GPIO11 PerAddr6 PerAddr10 PerAddr13 PerAddr16 PerAddr18 DMAReq2 DMAAck3 OVDD PerAddr27 PerAddr30 DMAReq0 PCIAD2 PCIAD5 PCIReq0Gnt GPIO2TS2E PCIReq1 PCIAD13 PCIINTPerWE GND Reserved PCIAD14
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Signals Listed by Ball Assignment
Ball H23 H24 H25 H26 J1 J2 J3 J4 J5 J22 J23 J24 J25 J26 K1 K2 K3 K4 K5 K22 K23 K24 K25 K26 L1 L2 L3 L4 L5 L11 L12 L13 L14 L15 L16 L22 L23 L24 L25 L26 Signal Name PCIStop EMCMDClk PCIDevSel PCIGnt3 PerData23 PerData26 PerData25 PerData27 GND GND PCIIRDY PCIFrame PCIReq5 EMCTxD0 PerData20 OVDD PerData22 PerData24 VDD VDD EMCTxEn PCIC2BE2 EMCTxErr PCIAD16 GND PerData21 PerData18 PerData19 VDD GND GND GND GND GND GND VDD PCIAD17 EMCTxD2 EMCTxD1 GND Ball M1 M2 M3 M4 M5 M11 M12 M13 M14 M15 M16 M22 M23 M24 M25 M26 N1 N2 N3 N4 N5 N11 N12 N13 N14 N15 N16 N22 N23 N24 N25 N26 P1 P2 P3 P4 P5 P11 P12 P13
(Part 2 of 3)
Ball P14 P15 P16 P22 P23 P24 P25 P26 R1 R2 R3 R4 R5 R11 R12 R13 R14 R15 R16 R22 R23 R24 R25 R26 T1 T2 T3 T4 T5 T11 T12 T13 T14 T15 T16 T22 T23 T24 T25 T26 Signal Name GND GND GND GND PCIAD26 PCIAD23 EMCTxD3 PCIIDSel PerData8 PerData4 BusReq PerData6 VDD GND GND GND GND GND GND VDD PCIAD25 PCIAD24 PCIAD27 PCIC3BE3 GND HoldPri ExtReset PerData3 VDD GND GND GND GND GND GND VDD PCIGnt1 PCIAD28 PCIAD30 GND Ball U1 U2 U3 U4 U5 U22 U23 U24 U25 U26 V1 V2 V3 V4 V5 V22 V23 V24 V25 V26 W1 W2 W3 W4 W5 W22 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y5 Y22 Y23 Y24 Y25 Y26 Signal Name PerData2 HoldAck PerData1 PerData0 VDD VDD PCIGnt0Req PHYRxErr OVDD PCIAD29 HoldReq EOT2 / TC2 MemData31 MemData29 GND GND IRQ1GPIO18 PHYRxDV IRQ0GPIO17 PCIAD31 MemData30 MemData27 MemData28 MemData26 OVDD OVDD PHYCrS IRQ2GPIO19 IRQ3GPIO20 GND EOT3 / TC3 MemData25 ExtAck ExtReq OVDD OVDD Reserved IRQ4GPIO21 IRQ5GPIO22 Reserved
Signal Name PerData12 PerData17 PerData14 PerData15 VDD GND GND GND GND GND GND VDD PCIAD19 PCIGnt5 PCIAD18 PCIAD21 PerData11 PerData13 PerData10 PerData16 GND GND GND GND GND GND GND GND PCIGnt4 OVDD PCIAD20 PCIAD22 PerData9 PerData7 OVDD PerData5 GND GND GND GND
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Signals Listed by Ball Assignment
(Part 3 of 3)
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Signal List
The table following table provides a summary of the number of package pins associated with each functional interface group.
Pin Summary
Group
PCI Ethernet SDRAM External peripheral External master Internal peripheral Interrupts JTAG System Total Signal Pins OVDD VDD Gnd Thermal (and Gnd) Reserved Total Pins
No. of Pins
Multiplexed Pins In the table "Signal Functional Description" on page 30, each external signal is listed along with a short description of the signal function. Some signals are multiplexed on the same package pin (ball) so that the pin can be used for different functions. Multiplexed signals are shown as a default signal with a secondary signal in square brackets (for example, GPIO1TS1E). Active-low signals (for example, RAS) are marked with an overline. It is expected that in any single application a particular pin will always be programmed to serve the same function. The flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible. In addition to multiplexing, many pins are also multi-purpose. For example, the EBC peripheral controller address pins are used as outputs by the PPC405GPr to broadcast an address to external slave devices when the PPC405GPr has control of the external bus. When, during the course of normal chip operation, an external master gains ownership of the external bus, these same pins are used as inputs which are driven by the external master and received by the EBC in the PPC405GPr. In this example, the pins are also bidirectional, serving as both inputs and outputs. Intialization Strapping One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only during reset and are used for other functions during normal operation (see "Strapping" on page 51). Note that the use of these pins for strapping is not considered multiplexing since the strapping function is not programmable.
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Signal Functional Description
(Part 1 of 8) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 29 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 29 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset pull up or pull down as required. 7. Pull-up may be required. See "External Bus Control Signals" on page 29.
Signal Name Description I / O Type
Notes
PCI Interface
PCIAD31:0 PCIC3:0BE3:0 PCI Address / Data Bus. Multiplexed address and data bus. PCI bus command and byte enables. PCI parity. Parity is even across PCIAD0:31 and PCIC0:3BE0:3. PCIParity is valid one cycle after either an address or data phase. The PCI device that drove PCIAD0:31 is responsible for driving PCIParity on the next PCI bus clock. PCIFrame is driven by the current PCI bus master to indicate the beginning and duration of a PCI access. PCIIRDY is driven by the current PCI bus master. Assertion of PCIIRDY indicates that the PCI initiator is ready to transfer data. The target of the current PCI transaction drives PCITRDY. Assertion of PCITRDY indicates that the PCI target is ready to transfer data. The target of the current PCI transaction can assert PCIStop to indicate to the requesting PCI master that it wants to end the current transaction. PCIDevSel is driven by the target of the current PCI transaction. A PCI target asserts PCIDevSel when it has decoded an address and command encoding and claims the transaction. PCIIDSel is used during configuration cycles to select the PCI slave interface for configuration. PCISErr is used for reporting address parity errors or catastrophic failures detected by a PCI target. PCIPErr is used for reporting data parity errors on PCI transactions. PCIPErr is driven active by the device receiving PCIAD0:31, PCIC0:3BE0:3, and PCIParity, two PCI clocks following the data in which bad parity is detected. PCIClk is used as the asynchronous PCI clock when in asynch mode. It is unused when the PCI interface is operated synchronously with the PLB bus. PCI specific reset. PCI interrupt. Open-drain output (two states 0 or open circuit) or Peripheral write enable. Low when any of the four PerWBE0:3 write byte enables are low. Multipurpose signal, used as PCIReq0 when internal arbiter is used, and as Gnt when external arbiter is used. I / O I / O 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 2
PCIParity
PCIFrame PCIIRDY
PCITRDY
PCIStop
PCIDevSel
PCIIDSel PCISErr
PCIPErr
PCIClk
5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI
PCIReset
PCIINTPerWE
PCIReq0Gnt
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Signal Functional Description
(Part 2 of 8) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 29 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 29 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset pull up or pull down as required. 7. Pull-up may be required. See "External Bus Control Signals" on page 29.
Signal Name PCIReq1:5 Description Used as PCIReq1:5 input when internal arbiter is used. Gnt0 when internal arbiter is used or Req when external arbiter is used. Used as PCIGnt1:5 output when internal arbiter is used. I / O I Type 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI
Notes
PCIGnt0Req
PCIGnt1:5
Ethernet Interface
PHYRxDV
PHYCrS
EMCTxErr
EMCTxEn
5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL
PHYTxClk PHYCol
EMCMDClk
EMCMDIOPHYMDIO
5V tolerant 3.3V LVTTL
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Signal Functional Description
(Part 3 of 8) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 29 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 29 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset pull up or pull down as required. 7. Pull-up may be required. See "External Bus Control Signals" on page 29.
Signal Name Description I / O Type
Notes
SDRAM Interface
Memory data bus. Notes: 1. MemData0 is the most significant bit (msb). 2. MemData31 is the least significant bit (lsb). Memory address bus. Notes: 1. MemAddr12 is the most significant bit (msb). 2. MemAddr0 is the least significant bit (lsb). Bank Address supporting up to 4 internal banks. Row Address Strobe. Column Address Strobe. DQM for byte lane: 0 (MemData0:7), 1 (MemData8:15), 2 (MemData16:23), and 3 (MemData24:31) DQM for ECC check bits. ECC check bits 0:7. Select up to four external SDRAM banks. Write Enable. SDRAM Clock Enable. Two copies of an SDRAM clock allows, in some cases, glueless SDRAM attach without requiring this signal to be repowered by a PLL or zero-delay buffer.
MemData0:31
3.3V LVTTL
MemAddr12:0
3.3V LVTTL
BA1:0 RAS CAS
3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
DQM0:3
3.3V LVTTL
DQMCB ECC0:7 BankSel0:3 WE ClkEn0:1 MemClkOut0:1
3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
External Slave Peripheral Interface
PerData0:31 Peripheral data bus used by PPC405GPr when not in external master mode, otherwise used by external master. Note: PerData0 is the most significant bit (msb) on this bus. Peripheral address bus used by PPC405GPr when not in external master mode, otherwise used by external master. Note: PerAddr0 is the most significant bit (msb) on this bus. Peripheral byte parity signals. As outputs, these pins can act as byte-enables which are valid for an entire cycle or as write-byte-enables which are valid for each byte on each data transfer, allowing partial word transactions. As outputs, pins are used by either the pripheral controller or the DMA controller depending upon the type of transfer involved. Used as inputs when an external bus master owns the external interface. I / O 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 1
PerAddr0:31
PerPar0:3
PerWBE0:3
5V tolerant 3.3V LVTTL
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Signal Functional Description
(Part 4 of 8) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 29 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 29 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset pull up or pull down as required. 7. Pull-up may be required. See "External Bus Control Signals" on page 29.
Signal Name Description Peripheral write enable. Low when any of the four PerWBE0:3 write byte enables are low. or PCI interrupt. Open-drain output (two states 0 or open circuit) Peripheral chip select bank 0. Seven additional peripheral chip selects or General Purpose I / O - To access this function, software must toggle a DCR bit. Used by either peripheral controller or DMA controller depending upon the type of transfer involved. When the PPC405GPr is the bus master, it enables the selected device to drive the bus. Used by the PPC405GPr when not in external master mode, as output by either the peripheral controller or DMA controller depending upon the type of transfer involved. High indicates a read from memory, low indicates a write to memory. Otherwise it used by the external master as an input to indicate the direction of transfer. Used by a peripheral slave to indicate it is ready to transfer data. Used by the PPC405GPr when not in external master mode, otherwise used by external master. Indicates the last transfer of a memory access. DMAReq0:3 are used by slave peripherals to indicate they are prepared to transfer data. DMAAck0:3 are used by the PPC405GPr to cause the DMA peripheral to transfer data. End Of Transfer / Terminal Count. I / O Type 5V tolerant 3.3V PCI 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL
Notes
PerWEPCIINT
PerCS0
PerCS1:7GPIO10:16
PerOE
5V tolerant 3.3V LVTTL
PerReady
5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL
PerBLast
DMAReq0:3 DMAAck0:3 EOT0:3 / TC0:3
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Signal Functional Description
(Part 5 of 8) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 29 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 29 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset pull up or pull down as required. 7. Pull-up may be required. See "External Bus Control Signals" on page 29.
Signal Name Description I / O Type
Notes
External Master Peripheral Interface
PerClk ExtReset HoldReq HoldAck ExtReq ExtAck HoldPri BusReq PerErr Peripheral clock to be used by an external master and by synchronous peripheral slaves. Peripheral reset to be used by an external master and by synchronous peripheral slaves. Hold Request, used by an external master to request ownership of the peripheral bus. Hold Acknowledge, used by the PPC405GPr to transfer ownership of peripheral bus to an external master. ExtReq is used by an external master to indicate it is prepared to transfer data. ExtAck is used by the PPC405GPr to indicate a data transfer cycle. Used by an external master to indicate the priority of a given external master tenure. Used when the PPC405GPr needs to regain control of peripheral interface from an external Master. An input used to indicate to the PPC405GPr that an external slave peripheral error occurred. O O I O I O I O I 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 1, 5 1, 5 6 1 6 1
Internal Peripheral Interface
UARTSerClk Serial Clock used to provide an alternate clock to the internally generated serial clock. Used in cases where the allowable internally generated baud rates are not satisfactory. This input can be individually connected to either UART. UART0 Serial Data In. UART0 Serial Data Out. UART0 Data Carrier Detect. UART0 Data Set Ready. UART0 Clear To Send. UART0 Data Terminal Ready. UART0 Request To Send. UART0 Ring Indicator. I 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 1
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Signal Functional Description
(Part 6 of 8) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 29 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 29 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset pull up or pull down as required. 7. Pull-up may be required. See "External Bus Control Signals" on page 29.
Notes
5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL
IICSCL IICSDA
Interrupts Interface
Interrupt requests or General Purpose I / O. To access this function, software must toggle a DCR bit. 5V tolerant 3.3V LVTTL
IRQ0:6GPIO17:23
JTAG Interface
TDI TMS TDO TCK TRST Test data in. JTAG test mode select. Test data out. JTAG test clock. The frequency of this input can range from DC to 25MHz. JTAG reset. TRST must be low at power-on to initialize the JTAG controller and for normal operation of the PPC405GPr. I I O I I 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 1, 4 5 1, 4 1, 4
System Interface
SysClk Main system clock input. Main system reset. External logic can drive this bidirectional pin low (minimum of 16 cycles) to initiate a system reset. A system reset can also be initiated by software. Implemented as an opendrain output (two states 0 or open circuit). Clean voltage input for the PLL. I 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL
SysReset
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Signal Functional Description
(Part 7 of 8) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 29 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 29 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset pull up or pull down as required. 7. Pull-up may be required. See "External Bus Control Signals" on page 29.
Signal Name AGND SysErr Halt Description Clean Ground input for the PLL. Set to 1 when a Machine Check is generated. Halt from external debugger. General Purpose I / O or Even Trace execution status. To access this function, software must toggle a DCR bit. General Purpose I / O or Odd Trace execution status. To access this function, software must toggle a DCR bit. General Purpose I / O or Odd Trace execution status. To access this function, software must toggle a DCR bit. General Purpose I / O or Trace status. To access this function, software must toggle a DCR bit. General Purpose I / O or Trace interface clock. A toggling signal that is always half of the CPU core frequency. To access this function, software must toggle a DCR bit. Note: Initialization strapping must hold this pin low (0) during reset. General Purpose I / O. Note: The pull-up initialization strapping resistor must be 1k rather than 3k in order to overcome the internal pull-down resistor. Test Enable. Used only for manufacturing tests. Pull down for normal operation. An external clock input that can be used to clock the timers in the CPU core. I / O I O I 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 1, 2 Type
Notes
GPIO1TS1E GPIO2TS2E
GPIO3TS1O
5V tolerant 3.3V LVTTL
GPIO4TS2O
5V tolerant 3.3V LVTTL
GPIO5:8TS3:6
5V tolerant 3.3V LVTTL
GPIO9TrcClk
5V tolerant 3.3V LVTTL
GPIO24
3.3V LVTTL w / pull-down 1.8V CMOS w / pull-down 5V tolerant 3.3V LVTTL
TestEn TmrClk
Trace Interface
TS1EGPIO1 TS2EGPIO2 Even Trace execution status. To access this function, software must toggle a DCR bit or General Purpose I / O. 5V tolerant 3.3V LVTTL
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Signal Functional Description
(Part 8 of 8) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 29 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 29 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset pull up or pull down as required. 7. Pull-up may be required. See "External Bus Control Signals" on page 29.
Signal Name Description Odd Trace execution status. To access this function, software must toggle a DCR bit or General Purpose I / O. Odd Trace execution status. To access this function, software must toggle a DCR bit or General Purpose I / O. Trace status. To access this function, software must toggle a DCR bit or General Purpose I / O. Trace interface clock. A toggling signal that is always half of the CPU core frequency. To access this function, software must toggle a DCR bit or General Purpose I / O. Note: Initialization strapping must hold this pin low (0) during reset. I / O Type 5V tolerant 3.3V LVTTL
Notes
TS1OGPIO3
TS2OGPIO4
5V tolerant 3.3V LVTTL
TS3:6GPIO5:8
5V tolerant 3.3V LVTTL
TrcClkGPIO9
5V tolerant 3.3V LVTTL
Ground pins
GND Ground Note: L11-L16, M11-M16, N11-N16, P11-P16, R11-R16, and T11-T16 are also thermal balls.
OVDD pins
OVDD Output driver voltage-3.3V.
VDD pins
VDD Logic voltage-1.8V.
Other pins
Reserved Reserved-Except for AF4, do not connect signals, voltage, or ground to these pins. AF4 must be tied to OVDD or GND.
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device
Characteristic Supply Voltage (Internal Logic) Supply Voltage (I / O Interface) PLL Supply Voltage Input Voltage (1.8V CMOS receivers) Input Voltage (3.3V LVTTL receivers) Input Voltage (5.0V LVTTL receivers) Storage Temperature Range Case temperature under bias Note: All specified voltages are with respect to GND. Symbol VDD OVDD AVDD VIN VIN VIN TSTG TC Value 0 to +1.95 0 to +3.6 0 to +1.95 -0.6 to VDD + 0.45 -0.6 to OVDD + 0.6 -0.6 to OVDD + 2.4 -55 to +150 -40 to +120 Unit V V V V V V
Package Thermal Specifications
The PPC405GPr is designed to operate within a case temperature range of -40°C to +85°C. Thermal resistance values for the E-PBGA packages in a convection environment are as follows: Airflow ft / min (m / sec) Symbol Package-Thermal Resistance Unit
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Recommended DC Operating Conditions
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended conditions can affect device reliability. Notes: 1. PCI drivers meet PCI specifications.
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
5V-Tolerant Input Current
0 -50 Input Current (µA)
-350 0.0 1.0 2.0 3.0 4.0 5.0 Input Voltage (V)
Input Capacitance
Parameter 3.3V LVTTL I / O 5V tolerant LVTTL I / O PCI I / O Rx only pins Symbol CIN1 CIN2 CIN3 CIN4 Maximum 8.8 8 9.3 4.5 Unit pF pF pF pF Notes
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
DC Electrical Characteristics
Parameter Active Operating Current (VDD)-266MHz Active Operating Current (VDD)-333MHz Active Operating Current (OVDD)-266MHz Active Operating Current (OVDD)-333MHz PLL VDD Input current Active Operating Power-266MHz Active Operating Power-333MHz Note: 1. Active operating currents and power values are design estimates. 2. AVDD should be derived from VDD using the following circuit: Symbol IDD IDD IODD IODD IPLL PDD PDD Minimum Typical 520 620 50 60 16 1.1 1.3 Maximum 570 740 60 70 23 1.3 1.7 Unit mA mA mA mA mA W W
VDD L1
AGND GND
L1 - 2.2 µH SMT inductor (equivalent to MuRata LQH3C2R2M34) or SMT chip ferrite bead (equivalent to MuRata BLM31A700S) C1 - 3.3 µF SMT tantalum C2 - 0.1 µF SMT monolithic ceramic capacitor with X7R dielectric or equivalent C3 - 0.01 µF SMT monolithic ceramic capacitor with X7R dielectric or equivalent
Output Pin
All signals other than PCI
Output Pin
PCI Rising edge
Output Pin
25 10pF
PCI Falling edge
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Clocking Specifications
Clocking Waveform
2.0V 1.5V 0.8V TCH TC TCL
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Spread Spectrum Clocking
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Peripheral Interface Clock Timings
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Input Setup and Hold Waveform
SysClk 1.5 V TIS MIN Inputs 1.5V
TIH MIN
Valid
Output Delay and Float Timing Waveform
SysClk
1.5V TOV MAX TOH MIN
Outputs
1.5V Valid MAX MIN
Outputs
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
I / O Specifications-Group 1 (Part 1 of 3) Notes: 1. PCI timings are for asynchronous operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns for 33.33MHz. 2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 3. For PCI, I / O H is specified at 0.9OVDD and I / O L is specified at 0.1OVDD. For all other interfaces, I / O H is specified at 2.4 V and I / O L is specified at 0.4 V.
Input (ns) Signal Setup Time (TIS min) 3 3 dc 3 3 na 3 na 3 3 3 5 na na 3 3 na 100 na na na Hold Time (TIH min) 0 0 dc 0 0 na 0 na 0 0 0 0 na na 0 0 na 0 na na na 6 6 6 6 dc 6 6 6 na na na 6 6 settable Output (ns) Valid Delay (TOV max) 6 6 Hold Time (TOH min) 1 1 na 1 1 1 1 dc 1 1 1 na na na 1 1 2 Output Current (mA) I / O H (min) 0.5 0.5 na 0.5 0.5 0.5 na 0.5 0.5 0.5 0.5 na 0.5 0.5 0.5 0.5 10.3 10.3 10.3 10.3 10.3 10.3 10.3 na 4 4 4 1 1 1 na na na na na na 10.3 10.3 10.3 na I / O L (min) 1.5 1.5 na 1.5 1.5 1.5 na 1.5 1.5 1.5 1.5 na 1.5 1.5 1.5 1.5 7.1 7.1 7.1 7.1 7.1 7.1 7.1 na 7.1 7.1 7.1 na PHYRX PHYRX PHYRX EMCMDClk PHYTX PHYTX PHYTX PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk 1 1 2, async 2 2 2 2 2, async 2, async 2, async 2 2 2 2, async Clock Notes
PCI Interface
PCIAD31:0 PCIC3:0BE3:0 PCIClk PCIDevSel PCIFrame PCIGnt0Req PCIGnt1:5 PCIIDSel PCIINTPerWE PCIIRDY PCIParity PCIPErr PCIReq0Gnt PCIReq1:5 PCIReset PCISErr PCIStop PCITRDY PCIClk PCIClk 1 1 async 1 1 1 1 async 1 1 1 1
Ethernet Interface
EMCMDClk EMCMDIOPHYMDIO EMCTxD3:0 EMCTxEn EMCTxErr PHYCol PHYCrS PHYRxClk PHYRxD3:0 PHYRxDV PHYRxErr PHYTxClk 1 OPB clock 1 OPB clock period + 10ns period 20 20 20 2 2 2
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
I / O Specifications-Group 1 (Part 2 of 3) Notes: 1. PCI timings are for asynchronous operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns for 33.33MHz. 2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 3. For PCI, I / O H is specified at 0.9OVDD and I / O L is specified at 0.1OVDD. For all other interfaces, I / O H is specified at 2.4 V and I / O L is specified at 0.4 V.
Input (ns) Signal Setup Time (TIS min) na na na na na na na Hold Time (TIH min) na na na na na na na na na na na na na na na na na na na na na Output (ns) Valid Delay (TOV max) na na Hold Time (TOH min) na na Output Current (mA) I / O H (min) 15.3 15.3 10.3 10.3 10.3 10.3 10.3 10.3 10.3 10.3 10.3 na na 10.3 na 10.3 na na 10.3 na na I / O L (min) 10.2 10.2 7.1 7.1 7.1 7.1 7.1 7.1 7.1 7.1 7.1 na na 7.1 na 7.1 na na 7.1 na na async async async async async Clock Notes
Internal Peripheral Interface
Interrupts Interface
IRQ0:6GPIO17:23
JTAG Interface
TCK TDI TDO TMS TRST
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
I / O Specifications-Group 1 (Part 3 of 3) Notes: 1. PCI timings are for asynchronous operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns for 33.33MHz. 2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 3. For PCI, I / O H is specified at 0.9OVDD and I / O L is specified at 0.1OVDD. For all other interfaces, I / O H is specified at 2.4 V and I / O L is specified at 0.4 V.
Input (ns) Signal Setup Time (TIS min) dc Hold Time (TIH min) dc Output (ns) Valid Delay (TOV max) na Hold Time (TOH min) na Output Current (mA) I / O H (min) na I / O L (min) na Clock Notes
System Interface
DrvrInh1:2 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO24 Halt SysClk SysErr SysReset TestEn TmrClk Trace TS1E TS2E TS1O TS2O TS3 TS4 TS5 TS6 dc dc dc dc dc dc na na na 10 na na na na na 1 na na
na na 10.3 10.3 na na
na na 7.1 7.1 na na
async async async async async
PTC / 2+0.7
PTC / 2-0.5
TrcClk
10pF load on clk / data
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PowerPC 405GPr Embedded Processor Data Sheet
Input (ns) Signal Setup Time (TIS min) na na na na na na 1.4 na 1.4 na na na 3.2 dc 2.2 3.3 na 4.7 na 2.3 3.3 5.5 2.3 Hold Time (TIH min) na na na na na na 0 na 0 na na na 0 dc 0 0 na 0.9 na 0 0 0 0 Output (ns) Valid Delay (TOV max) 4.5 4.5 4.4 3.9 4.5 4.3 4.5 4.6 5.1 4.4 4.4 6.1 na 6.4 7.1 6.5 6.5 7.2 6.5 7.2 6.6 na 6.1 Hold Time (TOH min) 1.6 1.5 1.5 1.4 1.4 1.4 1.5 1.5 1.4 1.5 1.5 2.2 na 2 2 2.3 2.1 1.9 2.1 2.1 2.1 na 2.2 Output Current (mA) I / O H (minimum) 15.3 15.3 15.3 23 15.3 15.3 15.3 15.3 15.3 15.3 15.3 10.3 na 10.3 15.3 10.3 10.3 15.3 10.3 15.3 10.3 na 10.3 I / O L (minimum) 10.2 10.2 10.2 19.3 10.2 10.2 10.2 10.2 10.2 10.2 10.2 7.1 na 7.1 10.2 7.1 7.1 10.2 7.1 10.2 7.1 na 7.1 Clock Notes
SDRAM Interface
BA1:0 BankSel3:0 CAS ClkEn0:1 DQM0:3 DQMCB ECC0:7 MemAddr12:0 MemData0:31 RAS WE DMAAck0:3 DMAReq0:3 EOT0:3 / TC0:3 PerAddr0:31 PerBLast PerCS0 PerCS1:7GPIO10:16 PerData0:31 PerOE PerPar0:3 PerR / W PerReady PerWBE0:3 MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk 1, 2, 5 2, 5 1, 2, 5 2, 5 2, 5 2, 5 2, 5 1, 2, 5 2, 5 1, 2, 5 1, 2, 5 5 5 5 5 5 5 5 5 5 5 5 5
External Slave Peripheral Interface
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Input (ns) Signal Setup Time (TIS min) na na 4.1 na na 2.1 3.1 na 2.4 Hold Time (TIH min) na na 0 na na 0 0 na 0 Output (ns) Valid Delay (TOV max) 6.1 5.9 na 6 6.1 na na 0.6 na Hold Time (TOH min) 2.2 2.1 na 1 2 na na -0.8 na Output Current (mA) I / O H (minimum) 10.3 10.3 na 15.3 10.3 na na 15.3 na I / O L (minimum) 7.1 7.1 na 10.2 7.1 na na 10.2 na Clock Notes
External Master Peripheral Interface
BusReq ExtAck ExtReq ExtReset HoldAck HoldPri HoldReq PerClk PerErr PerClk PerClk PerClk PerClk PerClk PerClk PerClk SysClk PerClk 5 5 5 5 5 5 5 4, 5 5
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Strapping
When the SysReset input is driven low by an external device (system reset), the state of certain I / O pins is read to enable default initial conditions prior to PPC405GPr start-up. The actual capture instant is the nearest SysClk edge before the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0) resistors to select the desired default conditions. The recommended pull-up is 3k to +3.3V or 10k to +5V. The recommended pull-down is 1K to GND. These pins are use for strap functions only during reset. They are used for other signals during normal operation. The following tables list the strapping pins along with their functions and strapping options. The PPC405GPr can be used as a drop-in replacement for the PPC405GP. When the PPC405GPr is used for this purpose, it should be strapped to operate in the PPC405GPr Legacy mode. This option is selected by strapping ball D20 (GPIO24) low (0). If Legacy mode is selected, the "PPC405GPr Legacy Mode Strapping Pin Assignments" table should be used to determine the strapping options. To operate the chip as a PPC405GPr, strap D20 (GPIO24) high (1) and use "PPC405GPr New Mode Strapping Pin Assignments" on page 53 to determine the strapping options.
PPC405GPr Legacy Mode Strapping Pin Assignments
(Part 1 of 2)
Option
for 6 M 7 use choice 3
PLL Forward Divider 2 Bypass mode Divide by 3 Divide by 4 Divide by 6 PLL Feedback Divider 2 Divide by 1 Divide by 2 Divide by 3 Divide by 4 PLB Divider from CPU
0 0 1 1 B14 (DMAAck2) 0 0 1 1 P25 (EMCTxD3)
Divide by 1 Divide by 2 Divide by 3 Divide by 4
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PowerPC 405GPr Embedded Processor Data Sheet
PPC405GPr Legacy Mode Strapping Pin Assignments
Function OPB Divider from PLB 2 Divide by 1 Divide by 2 Divide by 3 Divide by 4 PCI Divider from PLB
(Part 2 of 2)
Ball Strapping L25 (EMCTxD1) 0 0 1 1 J26 (EMCTxD0) 0 1 0 1
Option
External Bus Divider from PLB
ROM Width
ROM Location
PCI Asynchronous Mode Enable
PCI Arbiter Enable
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PowerPC 405GPr Embedded Processor Data Sheet
PPC405GPr New Mode Strapping Pin Assignments
(Part 1 of 3)
Divide by 8 Divide by 7 Divide by 6 Divide by 5 Divide by 4 Divide by 3 Divide by 2 Divide by 1 PLL Forward Divider B
Divide by 8 Divide by 7 Divide by 6 Divide by 5 Divide by 4 Divide by 3 Divide by 2 Divide by 1
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PowerPC 405GPr Embedded Processor Data Sheet
PPC405GPr New Mode Strapping Pin Assignments
Function PLL Feedback Divider 2, 3 Divide by 16 Divide by 1 Divide by 2 Divide by 3 Divide by 4 Divide by 5 Divide by 6 Divide by 7 Divide by 8 Divide by 9 Divide by 10 Divide by 11 Divide by 12 Divide by 13 Divide by 14 Divide by 15 OPB Divider from PLB
(Part 2 of 3)
PCI Divider from PLB
External Bus Divider from PLB 2
ROM Width
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
PPC405GPr New Mode Strapping Pin Assignments
Function ROM Location PPC405GPr Peripheral Attach PPC405GPr PCI Attach PCI Asynchronous Mode Enable Synchronous PCI Mode Asynchronous Mode External Bus Synchronous Mode Enable 3 Synchronous Mode Asynchronous Mode PCI Arbiter Enable
(Part 3 of 3)
Ball Strapping
Option U2 (HoldAck) 0 1 Y3 (ExtAck) 0 1 A22 (GPIO3TS1O) 0 1 AF18 (GPIO4TS2O) Internal Arbiter Disabled Internal Arbiter Enabled 0 1 D20 (GPIO24) Legacy (PPC405GP) mode New (PPC405GPr) mode4 0 1 AB3 (GPIO9TrcClk) Normal operation 0
New Mode Enable In Legacy mode the PPC405GPr functions like the PPC405GP. If not strapped, the PPC405GPr defaults to Legacy mode. Manufacturing Test Disable (must be strapped low (0) during initilization). Note:
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PowerPC 405GPr Embedded Processor Data Sheet
(c) Copyright International Business Machines Corporation 1999, 2002
All Rights Reserved Printed in the United States of America, March 2002 The following are trademarks of International Business Machines Corporation in the United States, or other countries, or both: Blue Logic CoreConnect IBM Logo CodePack IBM PowerPC
Other company, product, and service names may be trademarks or service marks of others. Preliminary Edition (3 / 8 / 02) This document contains information on a new product under development by IBM. IBM reserves the right to change or discontinue this product without notice. This document is a preliminary edition of the PowerPC 405GPr data sheet. Make sure you are using the correct edition for the level of the product. While the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made. All information contained in this document is subject to change without notice. The products described in this document are NOT intended for use in implantation or other life support applications where malfunction may result in injury or death to persons. The information contained in this document does not affect or change IBM product specifications or warranties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. All information contained in this document was obtained in specific environments, and is presented as an illustration. The results obtained in other operating environments may vary. THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN "AS IS" BASIS. In no event will IBM be liable for damages arising directly or indirectly from any use of the information contained in this document. IBM Microelectronics Division 1580 Route 52 Hopewell Junction, NY 12533-6351 The IBM home page is www. ibm.com. The IBM Microelectronics Division home is www.chips.ibm.com. SA14-2609-00