PowerPC processor core operating 400MHz with 32KB D-caches Selectable

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PowerPC processor core operating 400MHz with 32KB D-caches Selectable

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PowerPC 440GP Embedded Processor Data Sheet
PowerPC processor core operating 400MHz with 32KB D-caches Selectable processor:bus clock ratios 3:1, 4:1, 5:2, Double Data Rate (DDR) Synchronous DRAM (SDRAM) interface operating 133MHz On-chip SRAM External Peripheral eight devices with external mastering support external peripherals, internal UART memory PCI-X V1.0 Interface bits, 133MHz) with support conventional V2.2 Ethernet 10/100Mbps half- full-duplex with support RMII SMII interfaces Programmable Interrupt Controller supports interrupts from variety sources Programmable Timers serial ports (16750 compatible UART) interfaces General Purpose (GPIO) interface available JTAG interface board level testing Internal Processor Local (PLB) runs SDRAM interface frequency PowerPC processor boot from memory
Description
Designed specifically address high-end embedded applications, PowerPC 440GP (PPC440GP) provides high-performance, power solution that interfaces wide range peripherals incorporating on-chip power management features lower power dissipation. This chip contains high-performance RISC processor core, SDRAM controller, PCI-X interface, Ethernet interface, control external peripherals, with scatter-gather support, serial ports, interface, general purpose I/O. Technology: CMOS SA-27E, 0.18 (0.11 Leff), 5-layer metal Package: 25mm, 552-ball Ceramic Ball Grid Array (CBGA) Power (estimated): Less than 4.0W. Less than 1.0W sleep mode Voltages: 3.3V (except memory), 2.5V memory interface, 1.8V core logic analog circuits
While information contained herein believed accurate, such information preliminary, should relied upon accuracy completeness, representations warranties accuracy completeness made.
PowerPC 440GP Embedded Processor Data Sheet
Contents
Ordering Information Address Support PowerPC Processor Core Internal Buses PCI-X Interface SDRAM Memory Controller On-chip SRAM External Peripheral Controller (EBC) Ethernet Controller Interface Controller Serial Port Interface General Purpose Timers General Purpose (GPIO) Controller Universal Interrupt Controller JTAG Signal Lists Signal Description Test Conditions Spread Spectrum Clocking SDRAM Timing Initialization
Figures
PPC440GP Embedded Controller Functional Block Diagram 25mm, 552-Ball CBGA Package Timing Waveform Input Setup Hold Waveform Output Delay Float Timing Waveform
PowerPC 440GP Embedded Processor Data Sheet
Tables
System Memory Address Address Signals Listed Alphabetically Signals Listed Ball Assignment Summary Signal Functional Description Absolute Maximum Ratings Package Thermal Specifications Recommended Operating Conditions Input Capacitance Power Supply Loads Clocking Specifications Peripheral Interface Clock Timings Specifications-400MHz Strapping Assignments EEPROM
PowerPC 440GP Embedded Processor Data Sheet
Ordering Information
information availability following parts, contact your local sales office.
Product Name PPC440GP PPC440GP Notes:
Order Part Number1 IBM25PPC440GP-3CC400C IBM25PPC440GP-3CC400CZ
Processor Frequency 400MHz 400MHz
Package 25mm, CBGA 25mm, CBGA
Level
Value 0x40120400 0x40120400
JTAG 0x02052049 0x02052049
Order Part Number indicates tape-and-reel shipping package. Otherwise, chips shipped tray.
Each part number contains revision code. This mask revision number included part number identification purposes only. (Processor Version Register) software accessible contains additional information about revision level part. Refer PPC440GP User's Manual details register content.
Order Part Number
IBM25PPC440GP-3CC400Cx
Shipping Package: Blank Tray Tape reel Part Number Grade Reliability Package (CBGA) Case Temperature Range -40°C +85°C Processor Speed Revision Level
PowerPC 440GP Embedded Processor Data Sheet
PPC440GP Embedded Controller Functional Block Diagram
Universal Interrupt Controller Clock Control Reset Timers PPC440 Processor Core JTAG 32KB D-Cache Trace 32KB I-Cache On-chip Peripheral (OPB) Timer GPIO UART Power Mgmt DCRs
internal external
SRAM
Controller (4-Channel)
Bridge
Processor Local (PLB) Ethernet External External Master Controller Controller 32-bit addr 32-bit data
SDRAM Controller 133MHz 13-bit addr 32/64-bit data
PCI-X Bridge
RMII SMII
PPC440GP designed using Microelectronics Blue Logic methodology which major functional blocks integrated together create application-specific product (ASIC). This approach provides consistent create complex ASICs using CoreConnect Architecture. Note: CoreConnect busses provide: 128-bit interfaces 133.33MHz, 2.1GB/s 32-bit interfaces 66.66MHz, 266MB/s
Address Support
PPC440GP incorporates address maps. first fixed processor system memory address that serves PowerPC family processors. This address defines possible contents various address regions which processor access. second address Device Configuration Registers (DCRs). DCRs accessed software running PPC440GP processor through mtdcr mfdcr instructions.
PowerPC 440GP Embedded Processor Data Sheet
System Memory Address
Function Local Memory1 SRAM Reserve Reserved UART0 Reserved UART1 Reserved IIC0 Reserved IIC1 Internal Peripherals Reserved Arbiter Reserved GPIO Controller Ethernet ZMII Reserved Ethernet MAC0 Controller Ethernet MAC1 Controller General Purpose Timer Reserved Expansion ROM2 Boot
Function SDRAM
Start Address 0000 0000 8000 0000 8000 2000 0000 0000 4000 0000 4000 0200 4000 0208 4000 0300 4000 0308 4000 0400 4000 0420 4000 0500 4000 0520 4000 0600 4000 0640 4000 0700 4000 0780 4000 0790 4000 0800 4000 0900 4000 0A00 4000 0B00 F000 0000 FFE0 0000
Address 7FFF FFFF 8000 1FFF FFFF FFFF 3FFF FFFF 4000 01FF 4000 0207 4000 02FF 4000 0307 4000 03FF 4000 041F 4000 04FF 4000 051F 4000 05FF 4000 063F 4000 06FF 4000 077F 4000 078F 4000 07FF 4000 08FF 4000 09FF 4000 0AFF EFFF FFFF FFDF FFFF FFFF FFFF 07FF FFFF 0800 FFFF 0EBF FFFF 0EC0 0007 0EC7 FFFF 0EC8 00FF 0EC8 00FF 0EDF FFFF FFFF FFFF
Size 128B 256B 256B 254MB 64KB 256B 55.76
Reserved Reserved External Configuration Registers Reserved Bridge Core Configuration Registers Reserved Special Cycle Memory
0000 0000 0800 0000 0801 0000 0EC0 0000 0EC0 0008 0EC8 0000 0EC8 0100 0ED0 0000 0EE0 0000
Notes: Local Memory area memory configured SDRAM on-chip SRAM. Boot Expansion areas memory intended Flash-type devices. While locating volatile SDRAM SRAM this region supported controller, recommended that these regions used this purpose. When optional boot from memory selected, Boot address space begins FFFE 0000
(128 KB).
PowerPC 440GP Embedded Processor Data Sheet
Address Device Configuration Register
Function Address Space1 Reserved Memory Controller External Controller External Master Performance Monitor SRAM Reserved Bridge Reserved Bridge Power Management Reserved Interrupt Controller Interrupt Controller Clock, Control, Reset Reserved Controller Reserved Ethernet Reserved Notes: address space addressable with bits (1024 unique addresses). Each unique address represents single 32-bit (word) register, kiloword (KW) (which equals KB). Base Address Strap/Parameter Start Address(0:9) Address(0:9) Size (4KB)1 128W 512W
PowerPC 440GP Embedded Processor Data Sheet
PowerPC Processor Core
PowerPC processor core designed high-end applications: RAID controllers, routers, switches, printers, set-top boxes, etc. first processor core implement Book PowerPC embedded architecture first 128-bit version IBM's on-chip CoreConnect Architecture. Features include: 400MHz operation performance 32KB I-cache, 32KB D-cache Three logical regions D-cache: locked, transient, normal 41-bit virtual address, 36-bit (64GB) physical address Superscalar, out-of-order execution 7-stage pipeline Three execution pipelines Dynamic branch prediction Memory management unit 64-entry, full associative, unified Separate instruction data micro-TLBs Storage attributes write-through, cache-inhibited, guarded, little endian Debug facilities Multiple instruction data range breakpoints Data value compare Single step, branch, trap events Non-invasive real-time trace interface PowerPC Book architecture instructions Single cycle multiply multiply-accumulate integer multiply 32-bit
Internal Buses
PowerPC 440GP features three standard on-chip buses: Processor Local (PLB), OnChip Peripheral (OPB), Device Control Register (DCR). high performance, high bandwidth cores such PowerPC processor core, SDRAM memory controller, PCI-X bridge connect PLB. hosts lower data rate peripherals. daisy-chained provides lower bandwidth path passing status control information between processor core other on-chip cores. Features include: 128-bit implementation architecture Separate simultaneous read write data paths 36-bit address Simultaneous control, address, data phases Four levels pipelining Byte enable capability supporting unaligned transfers 64-byte burst transfers 133MHz, maximum 4.2GB/s (simultaneous read write) Processor:bus clock ratios 3:1, 4:1, 5:2,
PowerPC 440GP Embedded Processor Data Sheet
Dynamic sizing 32-, 16-, 8-bit data path Separate simultaneous read write data paths 36-bit address 66.66MHz, maximum 266MB/s 32-bit data path address
PCI-X Interface
PCI-X interface allows connection PCI-X devices PowerPC processor local memory. This interface designed Version PCI-X Specification supports 64-bit PCIX buses. 32/64-bit legacy mode, compatible with Version 2.2, also supported. Reference Specifications: PowerPC CoreConnect (PLB) Specification Version Specification Version Power Management Interface Specification Version Features include: PCI-X Split transactions Frequency 133MHz 64-bit backward compatibility Frequency 66MHz 64-bit Host Bridge Adapter Device's interface Optional internal arbitration function five external devices) that disabled with external arbiter Support external Support Message Signaled Interrupts Simple message passing capability Asynchronous Power Management register addressable both from on-chip processor device sides Ability boot from PCI-X memory Error tracking/status Supports initiation transfer following address spaces: Single beat reads writes Single beat burst memory reads writes Single beat configuration reads writes (type type Single beat special cycles
SDRAM Memory Controller
Double Data Rate (DDR) SDRAM memory controller supports industry standard 184-pin DIMMS. four 512MB logical banks supported limited configurations. Global memory timings, address bank sizes, memory addressing modes programmable.
PowerPC 440GP Embedded Processor Data Sheet
Features include: Registered non-registered industry standard DIMMs 64-bit memory interface with optional 8-bit (SEC/DED) Sustainable 2.1GB/s peak bandwidth 133MHz SSTL_2 logic chip selects latencies supported PC200/266 support Page mode accesses eight open pages) with configurable paging policy Programmable address mapping timing Hardware software initiated self-refresh Power management (self-refresh, suspend, sleep)
On-chip SRAM
physical bank Memory cycles supported Single beat read write, bytes byte burst transfers Guarded memory accesses Sustainable 2.1GB/s peak bandwidth 133MHz
External Peripheral Controller (EBC)
eight ROM, EPROM, SRAM, Flash memory, slave peripheral banks supported 66MHz operation (266MB/s) Burst non-burst devices 16-, 32-bit byte-addressable data 32-bit address, address space Latch data Ready, Synchronous Asynchronous Programmable access timing device Wait States non-burst Burst Wait States first access Wait States subsequent accesses Programmable CSon, CSoff relative address Programmable OEon, WEon, WEoff clock cycles) relative Programmable address mapping Peripheral Device pacing with external "Ready" External master interface Write posting from external master Read prefetching external master reads Bursting capable from external master Allows external master access non-EBC slaves External master control slaves access control
Ethernet Controller Interface
ethernet interfaces provided physical layer (PHY included chip) full Media Independent Interface (MII) with 4-bit parallel data transfer Reduced Media Independent Interfaces (RMII) with 2-bit parallel data transfer Serial Media Independent Interfaces (SMII) Each interface full half duplex 10Mb/s 100Mb/s
PowerPC 440GP Embedded Processor Data Sheet
Controller
Supports following transfers: Memory-to-memory transfers Buffered peripheral memory transfers Buffered memory peripheral transfers Four channels Scatter/Gather capability programming multiple operations 16-, 32-bit peripheral support (OPB external) 64-bit addressing Address increment decrement Supports internal external peripherals Support memory mapped peripherals Support peripherals running slower frequency buses
Serial Port
8-pin UART 4-pin UART interface provided Selectable internal external serial clock allow wide range baud rates Register compatibility with NS16750 register Complete status reporting capability Fully programmable serial-interface characteristics Supports using internal engine
Interface
interfaces provided Support Phillips® Semiconductors Specification, dated 1995 Operation 100kHz 400kHz 8-bit data 7-bit address Slave transmitter receiver Master transmitter receiver Multiple masters Supports fixed interface independent byte data buffers Twelve memory-mapped, fully programmable configuration registers programmable interrupt request signal Provides full management protocols Programmable error recovery
General Purpose Timers
Provides separate time base counter additional system timers addition those defined processor core. 32-bit Time Base Counter driven Clock Five 32-bit compare timers
PowerPC 440GP Embedded Processor Data Sheet
General Purpose (GPIO) Controller
Controller functions GPIO registers programmed accessed memory-mapped master accesses. GPIOs pin-shared with other functions. DCRs control whether particular that GPIO capabilities acts GPIO used another purpose. Each GPIO output separately programmable emulate open drain driver (that drives zero, tri-stated output
Universal Interrupt Controller
Universal Interrupt Controllers (UIC) available. They provide control, status, communications necessary between external internal sources interrupts on-chip PowerPC processor. Note: Processor specific interrupts (for example, page faults) resources. Features include: external interrupts internal interrupts Edge triggered level-sensitive Positive negative active Non-critical critical interrupt on-chip processor core Programmable interrupt priority ordering Programmable critical interrupt vector faster vector processing
JTAG
IEEE 1149.1 Test Access Port RISCWatch Debugger support JTAG Boundary Scan Description Language (BSDL)
PowerPC 440GP Embedded Processor Data Sheet
25mm, 552-Ball CBGA Package
View
Corner
Chip
Capacitor Note: dimensions
Bottom View
25.0 23.0 25.0 0.04 SOLDERBALL 1.00
8.04
3.80
PowerPC 440GP Embedded Processor Data Sheet
Signal Lists
following table lists external signals alphabetical order shows ball number which signal appears. Multiplexed signals shown with default signal (following reset) brackets alternate signal brackets. Multiplexed signals appear alphabetically multiple times list-once each signal name ball. page number listed gives page "Signal Functional Description" page where signals indicated interface group begin.
Signals Listed Alphabetically
Signal Name AGND Ball AA11 AB11 AA16 AD09 AB15 AD11 AD05 AA24 AB05 AD17 AB10 AA18 AB14 AA09 AA07 AC05
(Part
Interface Group Power Power MemClkOut analog voltage Power analog voltage Power SysClk analog voltage SDRAM Page
AMVDD APVDD ASVDD BankSel0 BankSel1 BankSel2 BankSel3 [BE0]PCIXC0 [BE1]PCIXC1 [BE2]PCIXC2 [BE3]PCIXC3 [BE4]PCIXC4 [BE5]PCIXC5 [BE6]PCIXC6 [BE7]PCIXC7 BusReq ClkEn0 ClkEn1 ClkEn2 ClkEn3 DMAAck0 DMAAck1 DMAAck2 DMAAck3
SDRAM
External Master Peripheral SDRAM
SDRAM
SDRAM
External Slave Peripheral
PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name DMAReq0 DMAReq1 DMAReq2 DMAReq3 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 DrvrInh1 DrvrInh2 ECC0 ECC1 ECC2 ECC3 ECC4 ECC5 ECC6 ECC7 EMCCD[EMC1RxErr] EMCCRS[EMC0CRSDV] EMCMDClk EMCMDIO EMCRxClk EMCRxD0[EMC0RxD0][EMC0RxD] EMCRxD1[EMC0RxD1][EMC1RxD] EMCRxD2[EMC1RxD0] EMCRxD3[EMC1RxD1] EMCRxDV[EMC1CRSDV] EMCRxErr[EMC0RxErr] EMCTxClk[EMCRefClk] EMCTxD0[EMC0TxD0][EMC0TxD] EMCTxD1[EMC0TxD1][EMC1TxD] EMCTxD2[EMC1TxD0] EMCTxD3[EMC1TxD1] EMCTxEn[EMC0TxEn][EMCSync] EMCTxErr[EMC1TxEn] EOT0/TC0 EOT1/TC1 EOT2/TC2 EOT3/TC3 ExtAck ExtReq ExtReset Ball AC20 AC16 AC14 AB13 AC11 AC09 AA05 AB07 AB06 AD06 AC03 AB04 AD04 AA22 AB23
(Part
Interface Group Page
External Slave Peripheral
SDRAM
System
SDRAM
Ethernet Ethernet Ethernet Ethernet Ethernet
Ethernet
Ethernet Ethernet Ethernet
Ethernet
Ethernet Ethernet
External Slave Peripheral
External Master Peripheral External Master Peripheral External Master Peripheral
PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name Ball U21\
(Part
Interface Group Page
Power
PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name Ball AA02 AA06 AA10 AA13 AA17 AA21 AC04 AC08 AC12 AC15 AC19
(Part
Interface Group Page
Power
[GPIO0]IRQ0 [GPIO1]IRQ1 [GPIO2]IRQ2 [GPIO3]IRQ3 [GPIO4]IRQ4 [GPIO5]IRQ5 [GPIO6]IRQ6 [GPIO7]IRQ7 [GPIO8]IRQ8 [GPIO9]IRQ9 [GPIO10]IRQ10 GPIO11 [GPIO12]UART1_Rx [GPIO13]UART1_Tx [GPIO14]UART1_DSR/CTS [GPIO15]UART1_RTS/DTR [GPIO16]IIC1SClk [GPIO17]IIC1SDA [GPIO18]TrcBS0 [GPIO19]TrcBS1 [GPIO20]TrcBS2 [GPIO21]TrcES0 [GPIO22]TrcES1 [GPIO23]TrcES2 [GPIO24]TrcES3 [GPIO25]TrcES4 [GPIO26]TrcTS0 [GPIO27]TrcTS1 [GPIO28]TrcTS2 [GPIO29]TrcTS3 [GPIO30]TrcTS4 [GPIO31]TrcTS5 Halt HoldAck HoldReq
System
System External Master Peripheral External Master Peripheral
PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name IIC0SClk IIC0SDA IIC1SClk[GPIO16] IIC1SDA[GPIO17] IRQ0[GPIO0] IRQ1[GPIO1] IRQ2[GPIO2] IRQ3[GPIO3 IRQ4[GPIO4] IRQ5[GPIO5] IRQ6[GPIO6] IRQ7[GPIO7] IRQ8[GPIO8] IRQ9[GPIO9] IRQ10[GPIO10] [IRQ11]PCIReq1 [IRQ12]PCIGnt1 MemAddr0 MemAddr1 MemAddr2 MemAddr3 MemAddr4 MemAddr5 MemAddr6 MemAddr7 MemAddr8 MemAddr9 MemAddr10 MemAddr11 MemAddr12 MemClkOut0 MemClkOut0 Ball AD20 AB20 AD18 AD16 AB18 Peripheral Peripheral Peripheral Peripheral
(Part
Interface Group Page
Interrupts
SDRAM
SDRAM
PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name MemData0 MemData1 MemData2 MemData3 MemData4 MemData5 MemData6 MemData7 MemData8 MemData9 MemData10 MemData11 MemData12 MemData13 MemData14 MemData15 MemData16 MemData17 MemData18 MemData19 MemData20 MemData21 MemData22 MemData23 MemData24 MemData25 MemData26 MemData27 MemData28 MemData29 MemData30 MemData31 Ball AD21 AB21 AC22 AA20 AD19 AB19 AB16 AC18 AB17 AA14 AD15 AD13 AD14 AB12
(Part
Interface Group Page
SDRAM
PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name MemData32 MemData33 MemData34 MemData35 MemData36 MemData37 MemData38 MemData39 MemData40 MemData41 MemData42 MemData43 MemData44 MemData45 MemData46 MemData47 MemData48 MemData49 MemData50 MemData51 MemData52 MemData53 MemData54 MemData55 MemData56 MemData57 MemData58 MemData59 MemData60 MemData61 MemData62 MemData63 MemVRef1 MemVRef2 Ball AD12 AD10 AB08 AD08 AC07 AB09 AA01 AA03 AB02 AB03
(Part
Interface Group Page
SDRAM
SDRAM
PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name Ball AB01 AB24 AC01 AC02 AC23 AC24 AD01 AD02 AD03 AD22 AD23 AD24 AA23
(Part
Interface Group Page
ball
physical ball does exist these ball coordinates.
OVDD
Power
PCIXAck64
PCI-X
PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name PCIXAD0 PCIXAD1 PCIXAD2 PCIXAD3 PCIXAD4 PCIXAD5 PCIXAD6 PCIXAD7 PCIXAD8 PCIXAD9 PCIXAD10 PCIXAD11 PCIXAD12 PCIXAD13 PCIXAD14 PCIXAD15 PCIXAD16 PCIXAD17 PCIXAD18 PCIXAD19 PCIXAD20 PCIXAD21 PCIXAD22 PCIXAD23 PCIXAD24 PCIXAD25 PCIXAD26 PCIXAD27 PCIXAD28 PCIXAD29 PCIXAD30 PCIXAD31 Ball
(Part
Interface Group Page
PCI-X
PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name PCIXAD32 PCIXAD33 PCIXAD34 PCIXAD35 PCIXAD36 PCIXAD37 PCIXAD38 PCIXAD39 PCIXAD40 PCIXAD41 PCIXAD42 PCIXAD43 PCIXAD44 PCIXAD45 PCIXAD46 PCIXAD47 PCIXAD48 PCIXAD49 PCIXAD50 PCIXAD51 PCIXAD52 PCIXAD53 PCIXAD54 PCIXAD55 PCIXAD56 PCIXAD57 PCIXAD58 PCIXAD59 PCIXAD60 PCIXAD61 PCIXAD62 PCIXAD63 PCIXC0[BE0] PCIXC1[BE1] PCIXC2[BE2] PCIXC3[BE3] PCIXC4[BE4] PCIXC5[BE5] PCIXC6[BE6] PCIXC7[BE7] PCIXClk PCIXDevSel PCIXFrame PCIXGnt0 PCIXGnt1[IRQ12] PCIXGnt2 PCIXGnt3 PCIXGnt4 PCIXGnt5 PCIXIDSel PCIXINT PCIXIRDY Ball
(Part
Interface Group Page
PCI-X
PCI-X
PCI-X PCI-X PCI-X
PCI-X
PCI-X PCI-X PCI-X
PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name PCIXM66En PCIXParHigh PCIXParLow PCIXPErr PCIXReq0 PCIXReq1[IRQ11] PCIXReq2 PCIXReq3 PCIXReq4 PCIXReq5 PCIXReq64 PCIXReset PCIXSErr PCIXStop PCIXTRDY PCIX133Cap PCIXCap PerAddr0 PerAddr1 PerAddr2 PerAddr3 PerAddr4 PerAddr5 PerAddr6 PerAddr7 PerAddr8 PerAddr9 PerAddr10 PerAddr11 PerAddr12 PerAddr13 PerAddr14 PerAddr15 PerAddr16 PerAddr17 PerAddr18 PerAddr19 PerAddr20 PerAddr21 PerAddr22 PerAddr23 PerAddr24 PerAddr25 PerAddr26 PerAddr27 PerAddr28 PerAddr29 PerAddr30 PerAddr31 Ball PCI-X PCI-X PCI-X PCI-X
(Part
Interface Group Page
PCI-X
PCI-X PCI-X PCI-X PCI-X PCI-X PCI-X PCI-X
External Slave Peripheral Note: PerAddr0 most significant (msb) this bus.
PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name PerBE0 PerBE1 PerBE2 PerBE3 PerBLast PerClk PerCS0 PerCS1 PerCS2 PerCS3 PerCS4 PerCS5 PerCS6 PerCS7 PerData0 PerData1 PerData2 PerData3 PerData4 PerData5 PerData6 PerData7 PerData8 PerData9 PerData10 PerData11 PerData12 PerData13 PerData14 PerData15 PerData16 PerData17 PerData18 PerData19 PerData20 PerData21 PerData22 PerData23 PerData24 PerData25 PerData26 PerData27 PerData28 PerData29 PerData30 PerData31 PerErr PerOE PerPar0 PerPar1 PerPar2 PerPar3 Ball
(Part
Interface Group Page
External Slave Peripheral
External Slave Peripheral External Master Peripheral
External Slave Peripheral
External Slave Peripheral Note: PerData0 most significant (msb) this bus.
External Master Peripheral External Slave Peripheral
External Slave Peripheral
PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name PerR/W PerReady[RcvrInh] PerWE [RcvrInh]PerReady RefVEn Reserved Ball AD07 AA08 AA15 AC06 AC13 AC21 AB22
(Part
Interface Group External Slave Peripheral External Slave Peripheral External Slave Peripheral SDRAM System System Reserved Page
SVDD
Power
SysClk SysErr SysReset TestEn TmrClk TrcBS0[GPIO18] TrcBS1[GPIO19] TrcBS2[GPIO20] TrcClk TrcES0[GPIO21] TrcES1[GPIO22] TrcES2[GPIO23] TrcES3[GPIO24] TrcES4[GPIO25] TrcTS0[GPIO26] TrcTS1[GPIO27] TrcTS2[GPIO28] TrcTS3[GPIO29] TrcTS4[GPIO30] TrcTS5[GPIO31] TrcTS6 TRST UART0_CTS UART0_DCD UART0_DSR UART0_DTR
System System System JTAG JTAG JTAG System System JTAG Trace Trace
Trace
Trace
JTAG UART Peripheral UART Peripheral Note: Used initialization strapping input. UART Peripheral Note: Used initialization strapping input. UART Peripheral
PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name UART0_RI UART0_RTS UART0_Rx UART0_Tx UART1_DSR/CTS[GPIO14] UART1_RTS/DTR[GPIO15] UART1_Rx[GPIO12] UART1_Tx[GPIO13] UARTSerClk Ball AA04 AA12 AA19 AC10 AC17 UART Peripheral UART Peripheral UART Peripheral UART Peripheral UART Peripheral UART Peripheral UART Peripheral UART Peripheral UART Peripheral
(Part
Interface Group Page
Power
SDRAM
PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Ball Assignment
Ball Signal Name ball ball ball PCIXAD51 DrvrInh2 PCIXAD58 EMCRxD2 [EMC1RxD0] PCIXAD42 UARTSerClk PCIXAD5 PCIXFrame PerAddr3 PerAddr12 PCIXM66En PCIXAD9 PerAddr11 PCIXPErr PCIXSErr PerAddr4 PCIXAD21 PCIXAD22 ball ball ball Ball ball ball PCIXAD46 OVDD PCIXAD54 PCIXAD62 PCIXAD1 PerAddr2 OVDD PerAddr13 PCIXAD13 UART0_DTR OVDD PerAddr16 PCIXAD25 ball ball
(Part
Ball Signal Name ball PCIXAD41 PCIXC5[BE5] PCIXAD50 EMCTxErr [EMC1TxEn] PCIXAD57 PerBLast PCIXC4[BE4] PCIXAD55 PCIXAD4 PerAddr1 PCIXTRDY UART0_CTS PerAddr14 PCIXAD10 PCIXAD14 PCIXAD0 UART1_Rx[GPIO12] PCIXC2[BE2] PerAddr10 PCIXAD23 PCIXGnt1[IRQ12] PCIXAD28 ball Ball Signal Name PCIXAD36 OVDD PCIXAD45 PCIXAD53 PCIXAD61 PCIXAck64 OVDD PerAddr0 PerAddr15 PCIXAD15 OVDD PerAddr5 PCIXAD20 PCIXAD30 PCIXAD31
Signal Name
PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Ball Assignment
Ball Signal Name EMCRxD1 [EMC0RxD1] [EMC1RxD] PCIXAD40 Ball
(Part
Ball Signal Name Ball Signal Name
Signal Name
PCIXAD35
APVDD
PCIXAD33
PCIXAD39 EMCRxD0 [EMC0RxD0] [EMC0RxD] PCIXAD48 PCIXAD43 UART1_DSR/CTS [GPIO14] PCIXIDSel PCIX133Cap PCIXC6[BE6] PCIXAD2 IIC0SClk PCIXAD7 IIC0SDA PCIXAD8 PCIXAD12 UART0_RTS UART0_Rx PCIXAD19 PerData4 PerData3 PCIXAD26 SysClk PCIXReq4 ASVDD SysClk
PCIXClk
PCIXAD44
PCIXAD32
PCIXAD49 UART1_RTS/DTR [GPIO15] PCIXAD56 PCIXAD60 PCIXAD63 PCIXReq64 PCIXAD3 PerAddr6 PCIXIRDY PCIXDevSel PerAddr9 PCIXAD11 PCIXC1[BE1] PerCS0 PCIXAD16 PCIXAD17 PCIXReq2 PCIXReq1[IRQ11] PCIXGnt0 PCIXAD27 PCIXReq0
PCIXAD52
PCIXAD38
PCIXAD59 OVDD PCIXC7[BE7] PCIXAD6 PCIXC0[BE0] OVDD PCIXParLow PCIXAD18 PCIXC3[BE3] PCIXAD24 OVDD PCIXAD29
OVDD PCIXAD47 EMCRxD3 [EMC1RxD1] OVDD IIC1SClk[GPIO16] OVDD IIC1SDA[GPIO17] UART0_RI PerData5 PerData2 OVDD PerData1 PerData0
PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Ball Assignment
Ball Signal Name AGND EMCRxClk EMCTxD3 [EMC1TxD1] EMCTxD2 [EMC1TxD0] Ball
(Part
Ball Signal Name Reserved RefVEn PerCS4 Ball Signal Name PerAddr21 OVDD PerAddr7
Signal Name EMCRxDV [EMC1CRSDV] EMCRxErr [EMC0RxErr] OVDD EMCTxD1 [EMC0TxD1] [EMC1TxD]
PCIXParHigh
PCIXAD37
EMCMDIO
TestEn
EMCTxClk [EMCRefClk]
EMCTxEn [EMC0TxEn] [EMCSync] DrvrInh1 PCIXAD34 EMCTxD0 [EMC0TxD0] [EMC0TxD] PerCS1 UART0_Tx PCIXStop PerCS6 PerData20 PerAddr17 PerData31 PerData30 IRQ3[GPIO3] PerData29 IRQ1[GPIO1] PerAddr18 PerAddr19 PCIXCap PerAddr22
EMCCD[EMC1RxErr] EMCMDClk
EMCCRS [EMC0CRSDV] OVDD
PCIXINT
PerData19
PerData28
PerOE
PerData18 PerData17 PerData16 PerData15 PerData14 PerData13 UART1_Tx[GPIO13] PerData12 PerData11 PerData10 PerData9 PerData8 PerData7 PerData6 AGND
PerData27 PerData26 PerData25 PerData24 OVDD PerData23 PerData22 PerData21
DMAReq1 IRQ6[GPIO6] EOT3/TC3 OVDD PCIXGnt3 IRQ5[GPIO5] PerAddr20 PCIXReset
PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Ball Assignment
Ball Signal Name PerAddr8 PerAddr28 DMAAck0 PerReady[RcvrInh] OVDD TrcES2[GPIO23] DMAReq2 IRQ4[GPIO4] TrcBS0[GPIO18] IRQ0[GPIO0] IRQ8[GPIO8] PCIXGnt2 OVDD TRST Ball DMAReq3 PerWE TrcTS1[GPIO27] Reserved PerR/W DMAAck2 DMAAck1 TrcES3[GPIO24] TrcTS3[GPIO29] SysReset DMAAck3 MemData28 GPIO11 EOT1/TC1 EOT2/TC2 TrcBS1[GPIO19] IRQ7[GPIO7] PCIXGnt5 IRQ2[GPIO2] PerErr IRQ9[GPIO9] TrcES1[GPIO22] PerAddr23
(Part
Ball Signal Name TrcTS6 DMAReq0 TrcClk OVDD TrcTS2[GPIO28] TrcTS4[GPIO30] MemData42 MemData14 EOT0/TC0 OVDD PCIXReq5 PCIXReq3 OVDD PCIXGnt4 PerAddr25 Ball Signal Name DQS7 SysErr PerCS5 TrcTS0[GPIO26] TrcES4[GPIO25] TrcTS5[GPIO31] MemData61 MemData56 MemVRef2 MemData38 MemData37 MemData35 MemData22 MemVRef1 MemData18 ExtReset PerBE0 PerAddr24 TrcBS2[GPIO20] TrcES0[GPIO21] PerPar1 PerPar0 PerCS3
Signal Name
PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Ball Assignment
Ball Signal Name TmrClk PerCS7 OVDD MemData63 MemData57 ECC4 MemData36 SVDD MemData21 SVDD MemData4 PerClk OVDD PerPar3 PerAddr26 PerAddr27 Ball MemData55 UART0_DSR PerCS2 Halt MemData60 MemData54 MemClkOut0 MemClkOut0 MemAddr12 MemAddr9 MemData31 MemAddr8 MemData26 MemData19 MemData9 MemData5 IRQ10[GPIO10] PerBE1 PerAddr29 PerAddr31 PerAddr30 UART0_DCD
(Part
Ball Signal Name MemData58 OVDD MemData59 MemData62 ECC3 ClkEn3 SVDD MemData32 BankSel1 MemAddr10 SVDD MemData8 PerPar2 PerBE2 PerBE3 Ball Signal Name MemData51 MemData53 DQS6 MemData46 MemData43 MemData47 ClkEn2 MemData34 MemAddr11 MemData30 MemData27 MemAddr7 MemData23 MemData20 MemData10 MemData13 MemAddr0 MemAddr2 HoldAck HoldReq
Signal Name
PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Ball Assignment
Ball AA01 AA02 AA03 AA04 AA05 AA06 AA07 AA08 AA09 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 Signal Name MemData48 MemData49 DQS8 SVDD AGND MemData16 SVDD MemData3 ExtAck OVDD BusReq Ball AB01 AB02 AB03 AB04 AB05 AB06 AB07 AB08 AB09 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 ball MemData50 MemData52 ECC6 ECC1 ECC0 MemData40 MemData45 ClkEn1 AMVDD MemClk MemData29 DQS3 BankSel0 MemData11 MemData15 MemAddr6 MemData7 MemAddr3 MemData1 ExtReq ball
(Part
Ball AC01 AC02 AC03 AC04 AC05 AC06 AC07 AC08 AC09 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 Signal Name ball ball ECC5 SVDD MemData44 DQS5 DQS4 SVDD DQS2 DQS1 MemData12 DQS0 SVDD MemData2 ball ball Ball AD01 AD02 AD03 AD04 AD05 AD06 AD07 AD08 AD09 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 Signal Name ball ball ball ECC7 BankSel3 ECC2 MemData41 MemData39 BankSel2 MemData33 MemData24 MemData25 MemData17 MemAddr5 ClkEn0 MemAddr4 MemData6 MemAddr1 MemData0 ball ball ball
Signal Name
PowerPC 440GP Embedded Processor Data Sheet
Signal Description
PPC440GP embedded controller packaged 552-ball enhanced ceramic ball grid array (CBGA). following tables describe package level pinout.
Summary
Group
Signal pins, non-multiplexed Signal pins, multiplexed Total Signal Pins AxVDD AGnd OVDD SVDD Total Power Pins Reserved Total Pins
Pins
table "Signal Functional Description" page each signal listed along with short description function. Some signals multiplexed onto same that used different functions. most cases, signal name shown this table unaccompanied multiplexed signal names that associated with Multiplexed signals shown square brackets following default signal (for example, PCIXC0:7[BE0:3]). Active-low signals such BE0:3 marked with overline. expected that single application particular will always programmed serve same function. flexibility multiplexing allows single chip offer richer selection than would otherwise possible. addition multiplexing, some pins also multi-purpose. example, peripheral controller address pins (PerAddr0:31) used outputs PPC440GP broadcast address external slave devices when PPC440GP control external bus. When during course normal chip operation external master gains ownership external bus, these same pins used inputs which driven external master received PPC440GP. this example, pins also bidirectional, serving both inputs outputs. group pins used strapped inputs during system reset. These pins function strapped inputs only during reset used other functions during normal operation (see "Strapping" page 54). Note that these multiplexed pins since function pins programmable. following table lists signals provided PPC440GP. Please refer "Signals Listed Alphabetically" page number which each signal assigned. cases where multiplexed signal (indicated square brackets) shown without other signals that assigned that pin, what other signals referring same table.
PowerPC 440GP Embedded Processor Data Sheet
(Part Notes: Receiver input hysteresis Must pull (recommended value 3.3V, Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name PCI-X Interface PCIXAD0:63 PCIXC0:7[BE0:7] PCIXClk PCIXDevSel PCIXFrame PCIXGnt0 PCIXGnt1 PCIXGnt2:5 PCIXIDSel PCIXINT PCIXIRDY PCIXM66En PCIXParHigh PCIXParLow PCIXPErr PCIXReq0:5 PCIXReq64 PCIXAck64 PCIXReset Address/Data (bidirectional). PCI-X Command[Byte Enables]. Provides timing interface transactions. Indicates driving device decoded address target current access. Driven current master indicate beginning duration access. Indicates that specified agent granted access bus. Indicates that specified agent granted access bus. Indicates that specified agent granted access bus. Used chip select during configuration read write transactions. Level sensitive interrupt. Indicates initiating agent's ability complete current data phase transaction. Capable 66MHz operation. Even parity across PCIAD32:63 PCIXC0:3[BE4:7]. Even parity across PCIAD0:31 PCIXC0:3[BE0:3]. Reports data parity errors during transactions except Special Cycle. indication PCI-X arbiter that specified agent wishes bus. Asserted current master, indicating 64-bit transfer. Indicates target transfer data using bits. Brings device registers logic consistent state. Reports address parity errors, data parity errors Special Cycle command, other catastrophic system errors. Indicates current target requesting master stop current transaction. 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V tolerant 3.3V LVTTL 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V Description Type
Signal Functional Description
Notes
PCIXSErr
3.3V
PCIXStop PCIXTRDY
3.3V 3.3V
Indicates target agent's ability complete
current data phase transaction.
PowerPC 440GP Embedded Processor Data Sheet
(Part Notes: Receiver input hysteresis Must pull (recommended value 3.3V, Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name PCIXCap PCIX133Cap SDRAM Interface BA0:1 BankSel0:3 ClkEn0:3 DM0:8 DQS0:8 ECC0:7 MemAddr0:12 MemClkOut0 MemClkOut0 MemData0:63 MemVRef1 MemVRef2 Ethernet Interface EMCCD[EMC1RxErr] EMCCRS[EMC0CRSDV] EMCMDClk EMCMDIO EMCRxClk Collision Detection[Receive error] (MII[RMII 1]). Carrier Sense[Receive data valid] (MII[RMII 0]). Management Data Clock (MII Transfer command status information between (MII RMII Receive Clock (MII). tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL Bank Address supporting four internal banks. Selects four external SDRAM banks. Column Address Strobe. Clock Enable. each bank. Memory write data byte lane masks. MEMDM8 byte lane mask byte lane. Byte lane data strobe. DQS8 data strobe byte lane. check bits 0:7. Memory address bus. Subsystem clock. Memory data bus. Memory reference voltages (SVREF). Address Strobe. Write Enable. 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 Voltage Receiver 2.5V SSTL_2 2.5V SSTL_2 Description Capable PCI-X operation. PCI-X devices capable. Type tolerant 3.3V LVTTL 3.3V
Signal Functional Description
Notes
EMCRxD0[EMC0RxD0][EMC0RxD] EMCRxD1[EMC0RxD1][EMC1RxD] Received Data (MII[RMII 1][SMII 1]). EMCRxD2[EMC1RxD0] EMCRxD3[EMC1RxD1] EMCRxDV[EMC1CRSDV] Receive Data Valid (MII[RMII 1]).
PowerPC 440GP Embedded Processor Data Sheet
(Part Notes: Receiver input hysteresis Must pull (recommended value 3.3V, Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name EMCRxErr[EMC0RxErr] EMCTxClk[EMCRefClk] Description Receive Error (MII[RMII 0]). Transmit Clock (MII[RMI SMII]). Type tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
Signal Functional Description
Notes
EMCTxD0[EMC0TxD0][EMC0TxD] EMCTxD1[EMC0TxD1][EMC1TxD] Transmitted Data (MII[RMII 1][SMII 1]). EMCTxD2[EMC1TxD0] EMCTxD3[EMC1TxD1] EMCTxEn[EMC0TxEn][EMCSync] Transmit data Enabled (MII[RMII 0][SMII]). Transmit Error (MII) Transmit data Enabled (RMII1).
EMCTxErr[EMC1TxEn]
External Slave Peripheral Interface
DMAAck0:3 DMAReq0:3 EOT0:3/TC0:3 Used PPC440GP indicate that data transfers have occurred. Used slave peripherals indicate they prepared transfer data. Transfer/Terminal Count. Peripheral address used PPC440GP when external master mode, otherwise used external master. Note: PerAddr0 most significant (msb) this bus. External peripheral data byte enables. Used either peripheral controller, controller, external master indicates last transfer memory access. External peripheral device select. Peripheral data used PPC440GP when external master mode, otherwise used external master. Note: PerData0 most significant (msb) this bus. Used either peripheral controller controller depending upon type transfer involved. When PPC440GP master, enables selected SDRAMs drive bus. External peripheral data byte parity. tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
PerAddr0:31
tolerant 3.3V LVTTL
PerBE0:3
tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
PerBLast
PerCS0:7
PerData0:31
tolerant 3.3V LVTTL
PerOE
tolerant 3.3V LVTTL tolerant 3.3V LVTTL
PerPar0:3
PowerPC 440GP Embedded Processor Data Sheet
(Part Notes: Receiver input hysteresis Must pull (recommended value 3.3V, Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name PerReady[RcvrInh] Description Used peripheral slave indicate ready transfer data. Used PPC440GP when external master mode, output either peripheral controller controller depending upon type transfer involved. High indicates read from memory, indicates write memory. Otherwise, used external master input indicate direction transfer. Write Enable. when four PerBE0:3 signals low. Type tolerant 3.3V LVTTL
Signal Functional Description
Notes
PerR/W
tolerant 3.3V LVTTL
PerWE
tolerant 3.3V LVTTL
External Master Peripheral Interface BusReq Request. Used when PPC440GP needs regain control peripheral interface from external master. External Acknowledgement. Used PPC440GP indicate that data transfer occurred. External Request. Used external master indicate prepared transfer data. Peripheral Reset. Used external master synchronous peripheral slaves. Hold Acknowledge. Used PPC440GP transfer ownership peripheral external master. Hold Request. Used external master request ownership peripheral bus. Peripheral Clock. Used external master synchronous peripheral slaves. External Error. Used input used record external master errors external slave peripheral errors. tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
ExtAck ExtReq ExtReset HoldAck HoldReq PerClk PerErr
UART Peripheral Interface
Serial Clock used provide alternative clock internally generated serial clock. Used cases where allowable internally generated baud rates satisfactory. This input individually connected either both UART0 UART1. UART0 Receive data. UART0 Transmit data. UART0 Data Carrier Detect. UART0 Data Ready. tolerant 3.3V LVTTL
UARTSerClk
UART0_Rx UART0_Tx UART0_DCD UART0_DSR
tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
PowerPC 440GP Embedded Processor Data Sheet
(Part Notes: Receiver input hysteresis Must pull (recommended value 3.3V, Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name UART0_CTS UART0_DTR UART0_RTS UART0_RI UART1_Rx UART1_Tx UART1_DSR/CTS UART1_RTS/DTR Description UART0 Clear Send. UART0 Data Terminal Ready. UART0 Request Send. UART0 Ring Indicator. UART1 Receive data. UART1 Transmit data. UART1 Data Ready Clear Send. choice determined register setting. UART1 Request Send Data Terminal Ready. choice determined register setting. Type tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
Signal Functional Description
Notes
Peripheral Interface
IIC0SClk IIC0SDA IIC1SClk IIC1SDA IIC0 Serial Clock. IIC0 Serial Data. IIC1 Serial Clock. IIC1 Serial Data. tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
Interrupts Interface
IRQ0:10 [IRQ11] [IRQ12] Interrupt Requests through Interrupt Request Interrupt Request tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
PowerPC 440GP Embedded Processor Data Sheet
(Part Notes: Receiver input hysteresis Must pull (recommended value 3.3V, Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name Description Type
Signal Functional Description
Notes
JTAG Interface
TRST Test Clock. Test Data Test Data Out. Test Mode Select. Test Reset. 3.3V CMOS w/pull-up 3.3V CMOS w/pull-up 3.3V LVTTL 3.3V CMOS w/pull-up 3.3V CMOS w/pull-up
System Interface
ExtReset SysClk SysErr SysReset TmrClk Halt [GPIO0:10] GPIO11 [GPIO12:31] TestEn [RcvrInh] RefVEn DrvrInh1:2 External reset Main system clock input. when machine check generated. Main system reset. Processor timer external input clock. Halt from external debugger. General purpose through access these functions, software must toggle register bits. General purpose access this function, software must toggle register bit. General purpose through access these functions, software must toggle register bit. Test Enable. Receiver Inhibit. Active only when TestEn active. Reference Voltage Enable. Used wafer testing. connect normal operation. Driver Inhibit. Used test purposes only. normal operation Clock tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL 1.8V CMOS w/pull-down tolerant 3.3V LVTTL 1.8V CMOS w/pull-down tolerant 3.3V LVTTL
PowerPC 440GP Embedded Processor Data Sheet
(Part Notes: Receiver input hysteresis Must pull (recommended value 3.3V, Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name Trace Interface TrcBS0:2 TrcClk TrcES0:4 TrcTS0:6 Power Pins AGND AxVDD OVDD SVDD (analog) voltage ground. Ground. Filtered voltages input PLLs (analog circuits) Note: separate filter each three voltages recommended. (except SDRAM) voltage-3.3V. SDRAM voltage-2.5V. Logic voltage-1.8V. Branch execution status. Trace data capture clock, runs frequency processor. Trace Execution Status presented every fourth processor clock cycle. Additional information trace execution branch status. tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL Description Type
Signal Functional Description
Notes
Reserved Pins
Reserved connect signals, voltage, ground these balls.
PowerPC 440GP Embedded Processor Data Sheet
Absolute Maximum Ratings
absolute maximum ratings below stress ratings only. Operation beyond these maximum ratings cause permanent damage device
Characteristic Supply Voltage (Internal Logic) Supply Voltage (I/O Interface, except SDRAM) Supply Voltages Supply Voltage (DDR SDRAM Logic) Input Voltage (3.3V LVTTL receivers) Input Voltage (5.0V LVTTL receivers) Storage Temperature Range Case temperature under bias Note: OVDD 0.4V required that 0.4V. Supply excursions meeting this criteria must limited less than 25ms duration during each power power down event. Symbol OVDD AxVDD SVDD TSTG Value +1.95 +3.6 +1.95 +2.7 +3.6 +5.5 +150 +120 Unit Notes
Package Thermal Specifications
PPC440GP designed operate within case temperature range -40°C 120°C. Thermal resistance values CBGA package convection environment follows: Airflow ft/min (m/sec) Symbol Unit Parameter
Junction-to-case thermal resistance Case-to-ambient thermal resistance (without heat sink) Notes: Case temperature, measured center case surface with device soldered circuit board. where ambient temperature power consumption. TCMax TJMax where TJMax maximum junction temperature power consumption. above assumes that chip mounted card with least signal power planes. (0.51) <0.1 17.7 (1.02) <0.1 16.3 °C/W °C/W
<0.1 18.9
PowerPC 440GP Embedded Processor Data Sheet
Recommended Operating Conditions
Device operation beyond conditions specified recommended. Extended operation beyond recommended conditions affect device reliability.
Parameter Logic Supply Voltage Supply Voltage SDRAM Supply Voltage Supply Voltages SDRAM Reference Voltage Input Logic High (2.5V SSTL receiver) Input Logic High (3.3V PCI-X receiver) Input Logic High (3.3V LVTTL, tolerant receiver) Input Logic (2.5V SSTL receiver) Input Logic (3.3V PCI-X receiver) Input Logic (3.3V LVTTL, tolerant receiver) Output Logic High (2.5V SSTL receiver) Output Logic High (3.3V PCI-X receiver) Output Logic High (3.3V LVTTL, tolerant receiver) Output Logic (2.5V SSTL receiver) Output Logic (3.3V PCI-X receiver) Output Logic (3.3V LVTTL, tolerant receiver) Input Leakage Current pull-up pull-down) Input Leakage Current Pull-Down Input Leakage Current Pull-Up Input Allowable Overshoot (3.3V LVTTL, tolerant receiver) Input Allowable Undershoot (3.3V LVTTL, tolerant receiver) Output Allowable Overshoot (3.3V LVTTL, tolerant receiver) Output Allowable Undershoot (3.3V LVTTL, tolerant receiver) Case Temperature Notes: PCI-X drivers meet PCI-X specifications. Power supply sequencing required. SVREF SVDD/2 analog voltage used on-chip PLLs derived from logic voltage, must filtered before entering PPC440GP. separate filter each voltage recommended. IIL1 IIL2 IIL3 VIMAO VIMAU VOMAO VOMAU3 Symbol OVDD SVDD AxVDD SVREF Minimum 1.65 1.15 SVREF 0.18 0.5OVDD 1.95 0.9OVDD (LPDL) Typical 1.25 Maximum 1.95 1.35 SVDD OVDD SVREF 0.18 0.35OVDD SVDD OVDD OVDD 0.55 0.35OVDD (MPUL) (MPUL) Unit Notes
-150 (LPDL)
PowerPC 440GP Embedded Processor Data Sheet
Input Capacitance
Parameter Group (2.5V SSTL I/O) Group tolerant LVTTL I/O) Group (PCI I/O) Group only pins) Symbol CIN1 CIN2 CIN3 CIN4 Maximum Unit Notes
Power Supply Loads
Parameter (1.8V) active operating current OVDD (3.3V) active operating current SVDD (2.5V) active operating current AxVDD (1.8V) input current Symbol IODD ISDD IADD Minimum Typical Maximum Unit
Test Conditions
Clock timing switching characteristics specified accordance with operating conditions shown table "Recommended Operating Conditions." specifications characterized with 1.8V, 50pF test load shown figure right.
Output 50pF
Each analog voltages internal circuits individually filtered using following circuit:
AxVDD chip ferrite bead for: APVDD (PCI) Murata BLM31A700S ASVDD (SysClk) Murata BLM31A700S AMVDD (MemClkOut) Murata BLM32A06 ceramic
PowerPC 440GP Embedded Processor Data Sheet
Clocking Specifications
Symbol SysClk Input MemClkOut Frequency Period 1000 Frequency Period Output high time nominal period 133.33 nominal period SysClk clock input frequency SysClk clock period Clock edge stability Clock input high time Clock input time 33.33 nominal period nominal period 66.66 0.15 nominal period nominal period Parameter Units
Note: Input slew rate 1V/ns
Timing Waveform
2.0V 1.5V 0.8V
PowerPC 440GP Embedded Processor Data Sheet
Spread Spectrum Clocking
Care must taken when using spread spectrum clock generator (SSCG) with PPC440GP. This controller uses clock generation inside chip. accuracy with which follows SSCG referred tracking skew. bandwidth phase angle determine much tracking skew there between SSCG given frequency deviation modulation frequency. When using SSCG with PPC440GP following conditions must met: frequency deviation must violate minimum clock cycle time. Therefore, when operating PPC440GP with more internal clocks their maximum supported frequency, SSCG only lower frequency. maximum frequency deviation cannot exceed -3%, modulation frequency cannot exceed 40kHz. some cases, on-board PPC440GP peripherals impose more stringent requirements. Peripheral Clock logic that synchronous peripheral since this clock tracks modulation. SDRAM MemClkOut since also tracks modulation. Notes: serial port baud rates synchronous modulated clock. serial port tolerance approximately 1.5% baud rate before framing errors begin occur. 1.5% tolerance assumes that connected device running precise baud rates. Ethernet operation unaffected. operation unaffected. Caution: system designer ensure that SSCG used with PPC440GP meets above requirements does adversely affect other aspects system.
PowerPC 440GP Embedded Processor Data Sheet
Peripheral Interface Clock Timings
Parameter PCIXClk input frequency (asynchronous mode) PCIXClk period (asynchronous mode) PCIXClk input high time PCIXClk input time EMCMDClk output frequency EMCMDClk period EMCMDClk output high time EMCMDClk output time EMCTxClk input frequency MII(RMII) EMCTxClk period MII(RMII) EMCTxClk input high time EMCTxClk input time EMCRxClk input frequency MII(RMII) EMCRxClk period MII(RMII) EMCRxClk input high time EMCRxClk input time PerClk output frequency (for ext. master sync. slaves) PerClk period PerClk output high time PerClk output time UARTSerClk input frequency) UARTSerClk period UARTSerClk input high time UARTSerClk input time TmrClk input frequency TmrClk period TmrClk input high time TmrClk input time Notes: TOPB period clock. internal clock runs frequency clock. maximum clock frequency 66.66 MHz. When PCI-X interface used support legacy interface, maximum PCIXClk 66.66MHz.
nominal period nominal period 2.5(5) 40(20) nominal period nominal period 2.5(5) 40(20) nominal period nominal period nominal period nominal period 2TOPB+2 TOPB+1 TOPB+1 nominal period nominal period
133.33 nominal period nominal period 25(50) 400(200) 25(50) 400(200) 66.66 nominal period nominal period 1000/(2TOPB1+2ns) nominal period nominal period
Units
Notes
PowerPC 440GP Embedded Processor Data Sheet
Input Setup Hold Waveform
SysClk Inputs 1.5V
Valid
Output Delay Float Timing Waveform
SysClk
1.5V
Outputs
1.5V Valid
Outputs
1.5V
PowerPC 440GP Embedded Processor Data Sheet
Specifications-400MHz
(Part Notes: Ethernet interface meets timing requirements defined IEEE 802.3 standard. PerClk rising edge package with 10pF load trails internal clock approximately 1.3ns. PCI-X timings asynchronous operation 133MHz. PCI-X input setup time requirement 1.2ns 133MHz 1.7ns 66MHz. timings parentheses) asynchronous operation 66MHz. output hold time requirement 66MHz 33MHz.
Input (ns) Signal PCI-X Interface PCIXAD31:0 PCIXC3:0[BE3:0] PCIXParLow PCIParHigh PCIXFrame PCIXINT PCIXIRDY PCIXTRDY PCIXStop PCIXDevSel PCIXIDSel PCIXPErr PCIXSErr PCIXClk PCIXReset PCIXReq64 PCIXAck64 PCIXCap PCIX133Cap PCIXM66En PCIXReq0:5 PCIXGnt0:5 Ethernet Interface EMCRxD0:3 EMCRxDV EMCRxClk EMCRxErr EMCTxD3:0 EMCTxEn EMCTxClk EMCTxErr EMCCRS EMCCD EMCMDIO EMCMDClk Dual Ethernet RMII Interface EMC0RxD0:1 EMC0RxErr EMC0CRSDV ENET0RxDV 10.3 EMCRxClk EMCRxClk EMCRxClk EMCRxClk 10.3 10.3 10.3 10.3 EMCMDClk EMCTxClk EMCRxClk EMCTxClk EMCTxClk EMCRxClk EMCRxClk async async async async async Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note n/a) (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk async async Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (minimum) (minimum) Clock Notes
PowerPC 440GP Embedded Processor Data Sheet
Specifications-400MHz
(Part Notes: Ethernet interface meets timing requirements defined IEEE 802.3 standard. PerClk rising edge package with 10pF load trails internal clock approximately 1.3ns. PCI-X timings asynchronous operation 133MHz. PCI-X input setup time requirement 1.2ns 133MHz 1.7ns 66MHz. timings parentheses) asynchronous operation 66MHz. output hold time requirement 66MHz 33MHz.
Input (ns) Signal EMC0TxD0:1 ENET0TxEn EMC1RxD0:1 EMC1RxErr EMC1CRSDV EMC1TxD0:1 EMC1TxEn EMCRefClk EMCMDIO EMCMDClk Internal Peripheral Interface IICxSClk IICxSDA UARTSerClk UART0_Rx UART0_Tx UART0_DCD UART0_DSR UART0_CTS UART0_DTR UART0_RI UART0_RTS UART1_Rx UART1_Tx UART1_DSR/CTS UART1_RTS/DTR Interrupts Interface IRQ0:12 JTAG Interface TRST 15.3 10.2 async async async async async 15.3 15.3 10.3 10.3 10.3 10.3 10.3 10.2 10.2 Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (minimum) 10.3 10.3 10.3 10.3 10.3 10.3 10.3 10.3 (minimum) EMCTxClk async Clock EMCTxClk EMCTxClk EMCRxClk EMCRxClk EMCRxClk EMCTxClk EMCTxClk async Notes
PowerPC 440GP Embedded Processor Data Sheet
Specifications-400MHz
(Part Notes: Ethernet interface meets timing requirements defined IEEE 802.3 standard. PerClk rising edge package with 10pF load trails internal clock approximately 1.3ns. PCI-X timings asynchronous operation 133MHz. PCI-X input setup time requirement 1.2ns 133MHz 1.7ns 66MHz. timings parentheses) asynchronous operation 66MHz. output hold time requirement 66MHz 33MHz.
Input (ns) Signal System Interface SysClk TmrClk SysReset Halt SysErr TestEn DrvrInh1:2 GPIO0:31 Trace Interface TrcClk PerData0:31 PerAddr0:31 PerPar0:3 PerBE0:3 PerCS0:7 PerOE PerWE PerBLast PerReady[RcvrInh] PerR/W DMAReq0:3 DMAAck0:3 EOT0:3/TC0:3 PerClk ExtReset HoldReq HoldAck ExtReq ExtAck BusReq PerErr 10.3 15.3 15.3 15.3 15.3 15.3 15.3 15.3 15.3 15.3 15.3 15.3 15.3 15.3 15.3 15.3 15.3 15.3 10.2 10.2 10.2 10.2 10.2 10.2 10.2 10.2 10.2 10.2 10.2 10.2 10.2 10.2 10.2 10.2 10.2 PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk External Slave Peripheral Interface 10.3 10.3 async async async async async Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (minimum) (minimum) Clock Notes
External Master Peripheral Interface
PowerPC 440GP Embedded Processor Data Sheet
SDRAM Timing
SDRAM controller times operation with internal 2xPLB clock signals generates MemClkOut from clock. MemClkOut same frequency clock signal. alignment MemClkOut with clock signal delayed maximum driver circuits. Note: MemClkOut advanced delayed with respect clock means SDRAM0_CFGn programming registers. Users might need advance MemClkOut their applications. This depends specific application requires thorough understanding memory system general (refer SDRAM controller chapter PowerPC 440GP User's Manual).
Specifications-DDR SDRAM Write Delay
Notes: 3.225 TCYC where TCYC 7.5ns 133MHz clock.
Input (ns) Signal SDRAM ECC0:7 MemData0:63 DM0:8 MemClkOut0 MemAddr0:12 BA0:1 BankSel0:3 ClkEn0:3 DQS0:8 2xPLB Setup Time Hold Time (minimum) (minimum) Output (ns) Valid Delay (maximum) 50pF load Hold Time (minimum) 50pF load Output Current (mA) (maximum) (minimum) Clock Notes
2xPLB
SDRAM Write Cycle Timing
MemClkOut
2xPLB
MemData
PowerPC 440GP Embedded Processor Data Sheet
SDRAM Read Cycle Timing
MemClkOut
2xPLB
MemData
SDRAM read operations, MemData must valid later than TCYC 0.5ns (1.375ns 133MHz) from rising edge DQS, must held valid until 1/4TCYC 0.4ns (2.275ns MHz) from rising chip pins. Data must have same relationship falling DQS. addition, there setup time with respect clock 2.375ns, unless read data clock been delayed programming SDRAM0_CFGn register.
PowerPC 440GP Embedded Processor Data Sheet
Initialization
PPC440GP provides option setting initial parameters based default values reading initial parameters from slave attached IIC0 bus.
Strapping
While SysReset input (system reset), state certain pins read enable default initial conditions prior PPC440GP start-up. actual capture instant nearest reference clock edge before deassertion reset. These pins must strapped using external pull-up (logical pull-down (logical resistors select desired default conditions. These pins used strap functions only during reset. Following reset they used normal functions. de-assertion reset, bootstrap controller enabled, sequentially reads bytes from external slave uses first bytes SYS0 SYS1 registers accordingly. Otherwise, default values STRP0 STRP1 used initialization. following table lists strapping pins along with their functions strapping options:
Strapping Assignments
Function IIC0 slave address that will respond with boot data 0x54 0x50 Bootstrap controller Disabled Enabled Option Ball Strapping (UART0_DSR) (UART0_DCD)
EEPROM
During reset, initial conditions other than those obtained from strapping pins read from device connected IIC0 port. association bits external with initialization settings their default values covered detail PowerPC 440GP User's Manual.
PowerPC 440GP Embedded Processor Data Sheet
Inside back cover
PowerPC 440GP Embedded Processor Data Sheet
Copyright International Business Machines Corporation 2001, 2002
Rights Reserved Printed United States America March 2002 following trademarks International Business Machines Corporation United States, other countries, both: Blue Logic CodePack CoreConnect Logo PowerPC
Other company, product, service names trademarks service marks others. Preliminary Edition (3/4/02) This document contains information product under development IBM. reserves right change discontinue this product without notice. This document preliminary edition PowerPC 440GP data sheet. Make sure using correct edition level product. While information contained herein believed accurate, such information preliminary, should relied upon accuracy completeness, representations warranties accuracy completeness made. information contained this document subject change without notice. products described this document intended implantation other life support applications where malfunction result injury death persons. information contained this document does affect change product specifications warranties. Nothing this document shall operate express implied license indemnity under intellectual property rights third parties. information contained this document obtained specific environments, presented illustration. results obtained other operating environments vary. INFORMATION CONTAINED THIS DOCUMENT PROVIDED BASIS. event will liable damages arising directly indirectly from information contained this document. Microelectronics Division 1580 Route Bldg. Hopewell Junction, 12533-6351 home page www.ibm.com Microelectronics Division home page www.chips.ibm.com SA14-2561-05

PowerPC processor core operating 400MHz with 32KB D-caches Selectable

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