7814/7851/7854 7814/7851/7854 Streaming Hifnsupplies Internet's m

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

7814/7851/7854 7814/7851/7854 Streaming Hifnsupplies Internet's m

Datasheet Thumbnail

Top Searches for this datasheet

Streaming Application Note
7814/7851/7854
7814/7851/7854 Streaming Hifnsupplies Internet's most important materials creation intelligent secure networks: compression, encryption, flow classification. This central growth Internet, helping make electronic mail, browsing, Internet shopping multimedia communications better, faster more secure. University Avenue Gatos, 95032 info@hifn.com http://www.hifn.com Tel: 408-399-3500 Fax: 408-399-3501 technical support, please contact your local Hifn sales office, representative distributor. locations check: www.hifn.com.
Disclaimer Hifn reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. Hifn warrants performance semiconductor products related software specifications applicable time sale accordance with Hifn's standard warranty. Testing other quality control techniques utilized extent Hifn deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Certain applications using semiconductor products involve potential risks death, personal injury, severe property environmental damage ("Critical Applications"). HIFN SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. Inclusion Hifn products such critical applications understood fully risk customer. Questions concerning potential risk applications should directed Hifn through local sales office. order minimize risks associated with customer's applications, adequate design operating safeguards should provided customer minimize inherent procedural hazards. Hifn does warrant that products free from infringement patents, copyrights other proprietary rights third parties. event shall Hifn liable special, incidental consequential damages arising from infringement alleged infringement patents, copyrights other third party intellectual property rights. "Typical" parameters vary different applications. operating parameters, including "Typicals," must validated each customer application customer's technical experts. this product stateful compression protocols (for example,. multi-history applications) with certain configurations require license from Motorola. such cases, license agreement right Motorola patents obtained through Hifn directly from Motorola.
AN-0045-00 (08/01) 2001 Hi/fn®, Inc., including more U.S. patents No.: 4,701,745, 5,003,307, 5,016,009, 5,126,739, 5,146,221, 5,414,425, 5,414,850, 5,463,390, 5,506,580, 5,532,694. Other patents pending. Hi/fn LZS® registered trademarks Hi/fn, Inc. Hifn trademark Hi/fn, Inc. other trademarks property their respective holders. This product must exported from United States accordance with Export Administration Regulations. Diversion contrary U.S. prohibited.
Page
AN-0045-00 APPLICATION NOTE
7814/7851/7854 Streaming
Table Contents
Overview Scope this Document Streaming Description
Designing with Streaming Bus.7 Choosing between Streaming Interface.7 Multi-chip Streaming Applications.7 Streaming Mode Boot Sequence Session Management Streaming Mode.8 2.4.1 Using Trap Queues Session Management.9 Private Processor Interface Streaming Mode.9 Load Balancing with multiple 78xx devices Signaling Considerations Streaming Mode 2.7.1 Deasserting sync_write signal mid-stream.11 2.7.2 FIFO level signals.12 2.7.3 Overflow Underflow.14 Commands Headers.15 2.8.1 Zero Length Source Descriptors 2.8.2 Pass Header Through 78xx
Streaming Mode Security Boundary
Streaming Example Streaming Initialization.19 Writing Command Source Fragments Reading Result Message Destination Data.23
AN-0045-00 APPLICATION NOTE
Page
7814/7851/7854 Streaming
Overview
Scope this Document
This application note contains information about 7814, 7851, 7854 streaming interface which helpful understanding streaming determining suitability particular application. Interface architectures system level design considerations discussed within this document intended general guide when designing with 78xx security processors. Hifn introduced streaming host interface beginning with 7851 security processor. Subsequently, entire 78xx family security processors adopted streaming interface. 7814, 7851, 7854 share common architecture, common package, common pinout. reader assumed have general knowledge 7851 architecture. Refer 7851 Network Security Processor Device Specification, DS-0030 7851 Programmer's Reference Guide, DS-0041 information about original 7851 part.
Streaming Description
streaming synchronous FIFO based interface that contains independent 32-bit buses, input output. interface designed that host network processor interface many four 78xx devices which share common streaming interface. From host processors perspective, 78xx streaming interface slave.
Sync. Clock
Inbound Flow Control
ASIC FPGA Network Processor (master)
Inbound Parity Inbound Sync Outbound Flow Control Outbound Parity Outbound Sync
78XX Security Processor (slave)
Figure Streaming Interface 78xx security processors streaming interface considered alternate since both interfaces share common pins. Only interface active same time. streaming enabled, packets must flow over streaming interface. Otherwise, they flow across PCI, controlled inbound outbound units.
Page
AN-0045-00 APPLICATION NOTE
7814/7851/7854 Streaming Since only interface used time, there bound unused pins 78xx application. streaming mode unused inputs should pulled their inactive state pulled through resistors. value between ohms will work. unused outputs left unconnected. most important distinction between streaming interface private interface that streaming specialized mechanism transferring packets requests security processor. streaming does directly support read write access processor registers, private memory, public-key core. Unlike interface, streaming does contain units. following figure illustrates data flows through Inbound Outbound ports 78xx streaming interface. Incoming packets ingress through Inbound streaming port consist command message, followed source descriptors, source data fragments. processed packets egress through Outbound port consist result messages followed destination data. Notice that command message contains field which defines number source fragments packet.
Inbound
Hi/fn 7851
Outbound
Command Source Descriptor
Notice that Result Data fragmented
Packet
Source Fragment
Destination Data
Processed Packet
Command Source Descriptor Result
Packet
Source Fragment
Destination Data
Processed Packet
Source Descriptor
Result
Source Fragment
Figure Packet Flow Streaming Mode streaming mode, inbound designed transfer command messages pre-processed packet data into 78xx processor. outbound transfers processed packet data result messages back host. streaming interface considered high-speed since eliminates
AN-0045-00 APPLICATION NOTE
Page
7814/7851/7854 Streaming overhead supports simultaneous bi-directional data transfer. figure below depicts single 7854 application using streaming interface.
Security Subsystem
Private Interface
Private Memory
Hi/fn 78xx
Session Management Security Processor
Host Network Porcessor
X-bus
Sync
Host Memory
Streaming FPGA ASIC
Packet Flow
Figure 78xx Application with Streaming Interface this figure packets flow over Inbound Outbound streaming while session management takes place over private interface. streaming applications private processor interface should used initialize 78xx registers, load programs, perform session management functions, handle security processor exceptions. 7854 7814 streaming applications private processor interface should also used host access public engine. following sections this document will discuss architectural considerations which apply 78xx systems which utilize streaming interface. These considerations include host interface methodology, placement FIPS security boundary, optional private processor, options Hifn's session management software, recommendations implementing multiple 78xx devices shared streaming interface. This document also contains information about streaming interface signaling, flow control, session setup. last section this document contains streaming example.
Page
AN-0045-00 APPLICATION NOTE
7814/7851/7854 Streaming
Designing with Streaming
Choosing between Streaming Interface
System performance host interface architecture primary considerations when choosing between either streaming modes. Systems which employ architectures naturally lend themselves toward using interface. other hand, systems witch require several 78xx security processors performance beyond better suited using shared streaming bus. systems packets ingress egress over same bus. streaming systems packets simultaneously flow through separate 32-bit wide Inbound Outbound data paths speeds Gigabits second Gigabits/sec. full duplex) maximum Mhz. Additionally, streaming fully dedicated interface. Packets flow demand. And, unlike PCI, there arbitration. Either streaming used multi-chip 78xx systems. Systems with more than 78xx processors forced streaming mode. course this assumes that multiple 78xx processors will share either single streaming bus. While multiple and/or streaming busses could used system, single shared assumed more desirable.
Multi-chip Streaming Applications
Applications which require higher overall performance connect four 78xx devices single streaming interface. Outbound streaming interface tri-statable Inbound inactive sync_write signal asserted. following figure contains example application which utilizes multiple 78xx processors which share single streaming interface.
Security Subsystem
Private Interface
Private Memory Private Memory Private Memory Private Memory
Session Management
Hi/fn 7854 Hi/fn 7854 Hi/fnSecurity 7854 Hi/fn Security 78XX Processor Security
Processor Security Processor Processor
Host Network Porcessor
Address Data
Session Logic
Sync
Chip Select Logic
Address Logic
Host Memory
Customer Logic (FPGA ASIC)
Figure Multichip Application with shared Streaming Interface
AN-0045-00 APPLICATION NOTE
Page
7814/7851/7854 Streaming Shared streaming applications require some provision host address individual devices shared bus. This accomplished several ways. most common ways memory individual 78xx devices shown) utilize pass-through field command message. Again, host architecture lend itself more strongly toward other. host interface FPGA/ASIC similar streaming bus, host could easily embed address into pass-through field. These bits could subsequently decoded glue logic used select 78xx device from shared streaming asserting sync_read sync_write signals desired target. host interface FPGA/ASIC traditional address data bus, memory mapped addressing mechanism more appropriate.
Streaming Mode Boot Sequence
streaming mode host required perform private processor functions including 78xx device initialization sequence. with session management streaming mode, initialization process takes place over private processor interface. This process must performed before sessions opened 78xx private memory. sequence involves programming 78xx registers their desired operating state, which reset, enable, disable certain logic blocks. Then required programs must loaded into private memory. actual register initialization values application specific. Refer 7851 Network Security Processor Device Specification register descriptions. Also, 7851 Verilog Model Application Note, AN-0022 provides complete examples initialization packet processing both streaming modes.
Session Management Streaming Mode
This section describes session handling accomplished over streaming interface (without private processor). Session setup must performed either private processor host network processor. Session setup never performed 78xx. following session setup tasks must performed before packets session sent across streaming unused session number must allocated session. session context must initialized appropriate values. Session context resides private SDRAM memory consists small session context optional large session compression context(s). program(s) that going process packets session must loaded into private memory. This task typically done only once beginning several similar sessions. These tasks will take place through private processor interface. They essentially made private memory reads writes which take place through private processor interface. this accomplished streaming application, interface logic between host 78xx device must drive memory transactions through private processor interface. most basic sense, this accomplished through generation address, data, control signals which mimic session handling would performed private processor. following figure illustrates concept host interface 78xx private processor interface through FPGA device.
Page
AN-0045-00 APPLICATION NOTE
7814/7851/7854 Streaming
Private Processor Interface
Read/Write Private Memory Read/Write Registers
SDRAM Registers
Address Data Signals Control Signals
Interrupts
Internal Interrupt Reset Core Descriptor Mgt. Commands Results
Core Descriptors
Host Network Porcessor
Host Memory
Customer Logic (FPGA)
78xx Security Processor
Streaming Interface
Figure Host Interface 78xx Private Processor Interface possible perform session management entirely over streaming interface. this situation special program must setup unique session number designed session management functions. Data associated with that session number would used setup manage session context described above. Such software subject Hifn availability. your Hifn representative more details. 2.4.1
Using Trap Queues Session Management
Trap_out_q Trap_in_q registers designed moving core descriptor indexes from private processor 78xx core. These queues enable private processor transfer receive security/compression tasks from 78xx core. There hidden difficulties when using these queues streaming applications where host required perform regular private processor duties. example, assume that host traps operation core. then completes required processing initiates trap back private (host processor this example). host doesn't respond immediately, mishandles return trap, processing associated session stalled. result, Hifn strongly recommends that customers either manipulate trap queues Hifn reference software these functions. Such software subject Hifn availability. Contact your Hifn representative more information.
Private Processor Interface Streaming Mode
following diagram illustrates host interface logic connected 78xx private processor interface. controller must generated customer logic block more than 78xx device being addressed same private interface bus. Example control logic shown.
AN-0045-00 APPLICATION NOTE
Page
7814/7851/7854 Streaming
Customer Logic
Hifn 78xx MIPS_INT[2:0]# BusClk VccOK* ColdReset* Reset* SysAD[31:0] SysADC[3:0] SysCmd[8:0] SysCmdP VialidOut* MIPS_CLK MIPS_VCCOK MIPS_COLDRESER# MIPS_RESET# MIPS_SYSAD[31:0] MIPS_SYSADC[3:0] MIPS_SYSCMD[8:0] MIPS_SYSCMDP MIPS_VALIDOUT# MIPS_VALIDIN#
ValidIn* BusCtl_VALIDIN* RdRDY* rRDY*
MIPS_RDRDY_EXT# MIPS_W RRDY_EXT#
MIPS_W RRD_RDY#
BusCtl_W RRDY* BusCtl_RDRDY*
Figure Private Processor Interface Streaming Mode
Load Balancing with multiple 78xx devices
When multiple 78xx security processors share single streaming bus, various load balancing schemes used help ensure high degree overall system utilization. simplest load balancing methods statically assign certain blocks session numbers each 78xx device shared streaming bus. Using this method, incoming packet session numbers used route entire packets appropriate 78xx device. This method alone sufficient systems which have requirement ordering processed packets. some systems necessary export packets same order they received. this situation host build maintain index table whereby Inbound packets assigned identifier which records which packet processor assigned each particular command. Head tail pointers index table used read result messages retire packets same order they received. And, pass through field command message contains index number, result message, which will also contain that index number, used error checking mechanism ensure synchronicity maintained with stream. Other more elaborate methods exist, depend largely software hardware capabilities application.
Page
AN-0045-00 APPLICATION NOTE
7814/7851/7854 Streaming
Signaling Considerations Streaming Mode
2.7.1
Deasserting sync_write signal mid-stream
Streaming operation timing requirements described 7851 Network Security Processor Device Specification, DS-0030. Streaming writes contiguous non-contiguous. example, when host processor writing words that make command descriptor necessary deassert write signal before writing data words. however, acceptable pause midcycle deasserting write signal. write process resume future clock cycle reasserting write signal. following figure illustrates typical write cycle command message. this example SYNC_IN_LEVEL signals indicates that Inbound FIFO reached some predefined threshold after first word written. host subsequently deasserts write signal waits Inbound level indicator transition back zero signify that there room Inbound FIFO writing additional words. given example, SYNC_IN_LEVEL signal assumed some unknown arbitrary value. Also, assumed that sufficient amount data already been written Inbound FIFO that threshold level signal exceeded first word write transaction. next section describes FIFO level signals greater detail.
SYNC_CLK
SYNC_W RITE
SYNC_DATA_IN[31:0] cdef
00020000 00000002
00000002 80CB0000
SYNC_IN_LEVEL[1] 32-bit dwords host write delayed while Inbound FIFO level indicates full FIFO.
Figure Example Streaming WRITE with 3-cycle pause. same conditions apply reading data from streaming bus. read signal deasserted time during sequence when words being read. read process resume once read signal reasserted later time. following figure illustrates typical streaming read transaction
AN-0045-00 APPLICATION NOTE
Page
7814/7851/7854 Streaming where Outbound FIFO level signals used gate single multi cycle read sequences.
SYNC_CLK
SYNC_READ
SYNC_OE_n
SYNC_DATA_OUT[31:0]
0000000A
00000002 0000
SYNC_OUT_LEVEL[0] 32-bit dwords SYNC_OUT_LEVEL[1] 32-bit dwords
Notice FIFO level signals used gate sync reads off.
Figure Example Streaming READ with pause. Notice that read signal asserted cycle then deasserted subsequent cycles. this example Outbound FIFO initially only word available, which read cycle Later, SYNC_READ signal reasserted cycle since FIFO level signals, which described next section, indicate that there more words Outbound FIFO. 2.7.2
FIFO level signals
host register programmable FIFO fullness signals determine when there data Inbound Outbound FIFOs. 78xx provides signals Inbound FIFO level detection signals Outbound FIFO level detection. These signals used host gate inbound outbound read write bursts maximum throughput with minimum host intervention. typical implementation program level signal indicate FIFO full condition which would gate host transfers prevent FIFO overrun. second FIFO level indicator programmed signal that FIFO some intermediate fullness which correspond maximum burst transfer size host. Then third FIFO fullness signal could programmed signal FIFO empty condition that interrupt host trigger burst read write that 78xx processor achieves 100% utilization. important recognize that there cycle delay between level change Outbound FIFO update associated level signal(s). Inbound FIFO there 3-cycle delay between writing dword updates associated FIFO level signals. Assuming output enable active, every clock which read signal active, data read from Outbound FIFO driven onto output pins cycles later. Outbound FIFO
Page
AN-0045-00 APPLICATION NOTE
7814/7851/7854 Streaming levels driven three cycles after sync_read asserted. 78xx device spec timing diagram Sync read. Software routines that service Inbound Outbound FIFOs should written that command, source destination data, result messages written read their entirety. Since destination data length independent command source data length, Outbound read routines should written solely fixed length multi-word block reads. optimum Outbound efficiency, helpful program Outbound FIFO level indicators four (level=4) another (level=0). host read blocks four when level=4 signal asserted. When level=4 signal subsides, host poll level=1 signal finish reading result message. This prevent single destination word from remaining Outbound FIFO without being read host. Managing Outbound level indicator signals associated read cycles somewhat more complicated than those Inbound side. This because generally easier write large blocks Inbound FIFO time without having manage individual dword write sequences. fact host make burst writes Inbound FIFO until gated SYNC_IN_LEVEL signal(s). Outbound FIFO works same except that host must take into consideration that there delays between asserting read signal reading from Outbound FIFO update Outbound FIFO level signal(s). following figure illustrates Outbound FIFO level signals used gate block read subsequent individual read cycles.
SYNC_CLK
SYNC_READ
SYNC_OE_n
SYNC_DATA_OUT[31:0]
01234567 89abcdef 01234567
89abcdef
SYNC_OUT_LEVEL[0] 32-bit dwords SYNC_OUT_LEVEL[1] 32-bit dwords
Notice takes cycles sync_out_level[0] update after read asserted.
cyc.
Figure Example Outbound FIFO level signals. Notice cycle SYNC_OUT_LEVEL[1] signal transitions tell host that there less dwords remaining Outbound FIFO. Since there cycle delay between FIFO level change update FIFO level signal, this condition must have began last cycle, which read
AN-0045-00 APPLICATION NOTE
Page
7814/7851/7854 Streaming cycle. response, host must immediately deassert read signal cycle prevent read underflow condition. last dwords read cycles 2-cycle delay between deasserting read signal final word being read. this particular situation SYNC_OUT_LEVEL[1] signal gated host read process just time read data from Outbound FIFO. cycle SYNC_OUT_LEVEL[0] signal tells host that there least more dword waiting Outbound FIFO. read cycle Also notice that takes cycles SYNC_OUT_LEVEL[0] signal update from time read signal asserted host. Inbound FIFO level signaling slightly simpler. There 3-cycle delay between writing data update level signal(s). following figure illustrates Inbound FIFO level signals used gate burst write 78xx device.
SYNC_CLK
SYNC_W RITE
SYNC_IN_LEVEL[1] 32-bit dwords SYNC_DATA_IN[31:0]
78ab 00020000 00000002 00000000 80CB0000
Since level signal program dwords know Inbound FIFO total spaces, host safely write additional dwords (shown) before deasserting write signal.
Figure Example Inbound FIFO level signal.
2.7.3
Overflow Underflow
Inbound FIFO overflow Outbound FIFO underflow both require reset internal FIFO control logic. status pci_stat register host tries write data Inbound FIFO when full. enabled pci_int_mask register, this status will generate interrupt sync_interrupt signal overflow. Reading empty outbound FIFO handled same way. When host tries read from empty Outbound FIFO, separate status pci_stat register. Data lost when host tries write already full Inbound FIFO. Similarly, invalid stale data will read from empty Outbound FIFO. both situations, internal pointing mechanism FIFO becomes corrupt must reset writing appropriate reset Inbound
Page
AN-0045-00 APPLICATION NOTE
7814/7851/7854 Streaming Outbound control registers. Inbound FIFO this located Cmd_ring_ctl register. Outbound FIFO this located Rslt_ring_ctl register.
Commands Headers
2.8.1
Zero Length Source Descriptors
command message contain zero associated source descriptors (NS=0). this situation command data immediately followed command. However, Inbound FIFO writes important realize that number bytes source descriptor cannot zero. Software write routines that designed handle blocks source fragments should written such that zero sized source descriptors used fill remaining words finish block transfer fill boundary. 2.8.2
Pass Header Through 78xx
Some applications require band communications between subsystems. streaming mode, 78xx program could allow variable length header pass through security processor unprocessed. Such software subject Hifn availability. Contact your Hifn representative more details. following diagram illustrates customer header which surrounded command packet data.
Packet Header
SYNC_IN_D[31:0]
Host
Header Rslt Packet
78xx
SYNC_OUT_D[31:0]
Figure Example Header
AN-0045-00 APPLICATION NOTE
Page
7814/7851/7854 Streaming
Streaming Mode
most 78xx streaming implementations, customers will Hifn's 78xx Software Development (SDK) Hifn's 7851 Early Sample Software (7851 ESS). 78xx software designed only applications. When using HSP, private processor responsible performing session setup management through private processor interface. Session setup involves programming session context into private memory prior security processor ever receiving processing packets associated with sessions. This alleviates significant amount processing from host CPU. some 78xx streaming applications possible HSP. this situation session management communications would likely flow across streaming through private processor bus. However, software currently supported this type application subject Hifn availability. Contact your Hifn representative more information. following diagram illustrates this type system.
Security Processor
Private Memory Private Processor
Hi/fn 78xx
Security Processor
Host Network Porcessor
X-Bus
Host Memory
FPGA ASIC
Streaming
Figure 78xx Streaming Private Processor
Page
AN-0045-00 APPLICATION NOTE
7814/7851/7854 Streaming
Security Boundary
private software make security boundary possible offload exception processing session setup tear-down overhead from host. also simplifies host software encapsulating most security software security subsystem. following figure highlights FIPS 140-1 security boundary streaming application which uses 78xx device with private processor present.
FIPS 140-1 Security Boundary
Private Memory Private Processor
Hi/fn 78xx
Security Processor
Host Network Porcessor Streaming FPGA
Host Memory
Streaming
Figure 78xx Security boundary (with private processor present) private processor, running software, would have direct access private memory session context, including material. Assuming private processor present, this sensitive information contained within security boundary shown. However, software currently supported this type application subject Hifn availability. Contact your Hifn representative more information. private processor present, host required perform private processor tasks. this situation security boundary expands include host CPU, host memory, interface logic which used connect private processor interface. applications without private processor host host memory will have access session context contain materials. following figure shows security boundary expanded systems which have private processor.
AN-0045-00 APPLICATION NOTE
Page
7814/7851/7854 Streaming
FIPS 140-1 Security Boundary
Private Processor Interface
Private Memory Private Memory Private Memory Private Memory
Hi/fn 7854 Hi/fn 7854 Hi/fnSecurity 7854 Hi/fnSecurity 78xx Processor Security
Processor Security Processor Processor
Host Network Porcessor Streaming FPGA
Streaming
Host Memory
Figure Security boundary (without private processor present)
Page
AN-0045-00 APPLICATION NOTE
7814/7851/7854 Streaming
Streaming Example
78xx streaming described this section using example. assume 78xx configured Streaming mode, reset session SDRAM desired compression encryption operation. assume required program loaded SDRAM function code offset assume that Sync interrupts disabled ignore parity.
Streaming Initialization
Initialization Sync Interface requires register writes cmd_ring_ctl rslt_ring_ctl.
cmd_ring_ctl written with 32'h7C3C_0018. Referring device
specification that this value means Inbound FIFO reset, command message endian 32-bit Inbound FIFO enabled. Inbound parity disabled inbound mode In_FIFO_Level_0 In_FIFO_Level_1 In_FIFO_Level_2 In_FIFO_Level_0 means SYNC_IN_LEVEL[0] when Inbound FIFO empty. used this example. In_FIFO_Level_2 means SYNC_IN_LEVEL[2] when Inbound FIFO full. used this example. In_FIFO_Level_1 means SYNC_IN_LEVEL[1] when Inbound FIFO dwords free space used following write rule: SYNC_IN_LEVEL[1] then write, else write. This rule ensures that burst qwords dwords) 78xx without Inbound FIFO overflow. This just example. Many other write rules could designed.
rslt_ring_ctl written with 32'h0008_7C18. Referring device
specification that this value means Outbound FIFO reset, result data endian 32-bit Outbound FIFO enabled. Outbound parity ignored outbound mode Out_FIFO_Level_0 Out_FIFO_Level_1 Out_FIFO_Level_2 Out_FIFO_Level_2 means SYNC_OUT_LEVEL[2] when Outbound FIFO full. used this example. Out_FIFO_Level_1 means SYNC_OUT_LEVEL[0] when Outbound FIFO contains more 32-bit dwords Out_FIFO_Level_0 means SYNC_OUT_LEVEL[1] when Outbound FIFO empty. SYNC_OUT_LEVEL[1] will when Outbound FIFO empty. This signal polled prevent read underflow when host reading last dwords from FIFO. read rule SYNC_OUT_LEVEL[1] then read wait. Else SYNC_OUT_LEVEL[0] then read wait clocks.
AN-0045-00 APPLICATION NOTE
Page
7814/7851/7854 Streaming Else read.
This rule ensures that perform continuous reads while there excess dwords from 7851 without danger reading from empty FIFO. When there only dword Outbound FIFO, only allow host read single dword, wait cycles, poll level signals again. Again this prevents host from reading from empty FIFO. This just example. Many other read rules could designed.
Page
AN-0045-00 APPLICATION NOTE
7814/7851/7854 Streaming
Writing Command Source Fragments
operation begins host writing command message over Sync Inbound FIFO. command message given
Referring device specification, that, this command, number source descriptors, overflow zero, Session Number Command Parameter Valid Function Code pass through value 8'hCB. following figure shows Sync signals during this command write.
SYNC_CLK
SYNC_W RITE
SYNC_DATA_IN[31:0]
00020000 00000002 00000000 80CB0000
SYNC_IN_LEVEL[1] 32-bit dwords
this exam write gated when free space Inbound FIFO falls below dwords 64-30=34)
Figure Host writes command. host then writes first source descriptors followed data, then second source descriptor followed data. first source descriptor given
64'h0000_0000_1000_0003
Referring device spec that, this source descriptor, byte alignment source data endian 32-bit fragment size bytes. following figure shows Sync signals during write source descriptor bytes data given
24'h1234_56
AN-0045-00 APPLICATION NOTE
Page
7814/7851/7854 Streaming
SYNC_CLK
SYNC_W RITE
SYNC_DATA_IN[31:0]
00000000 10000003 123456xx
SYNC_IN_LEVEL[1] 32-bit dwords
This write continuous since FIFOlevel does exceed threshold during write sequence.
Figure Host writes first source descriptor bytes data. second source descriptor given
64'h0000_0003_3000_0005
Referring device spec that, this source descriptor, 32-bit byte alignment source data endian 32-bit little fragment size bytes. following figure gives timing diagram write second source descriptor data given
40'habcd_ef01_23 which 40'h80F7_B3D5_C4 32-bit little endian format
Page
AN-0045-00 APPLICATION NOTE
7814/7851/7854 Streaming
SYNC_CLK wrie signal doesn't have deasserted after this data written. next cound ediately follow.
SYNC_W RITE
SYNC_DATA_IN[31:0]
xxxxx
00000003
30000005
xxxxxx80
F7B3D5C4
SYNC_IN_LEVEL[1] 32-bit dwords
Even though FIFOlevel indicator transitions high first cycle, host continue writing dwords before FIFO actually full.
Figure Host writes second source descriptor bytes data.
Reading Result Message Destination Data
parallel writing, host read result destination data from Outbound FIFO becomes available. following figure gives timing diagram reading result message:
Referring device spec this result message Total Destination Count Session Number Result Parameter pass through value 8'hCB, Result Flags Result Code
AN-0045-00 APPLICATION NOTE
Page
7814/7851/7854 Streaming
SYNC_CLK
SYNC_READ Only byte read this since level signals indicate there between dwords waiting
SYNC_OE_n
SYNC_DATA_OUT[31:0] SYNC_OUT_LEVEL[0] 32-bit dwords SYNC_OUT_LEVEL[1] 32-bit dwords
00000014
00000002 00000000 00CB0000
Here becom safe read consecutive dwords since level signals indicate there lease dwords Outbound FIFO.
Figure Host reads result message. Figure illustrates level signals used determine many dwords waiting read from Outbound FIFO. first cycle level signals indicate that there between dwords waiting read. prevent read underflow situation, host reads single dword waits cycles before polling level signals again determine FIFO empty. Since SYNC_OUT_LEVEL[1] signal transitions cycle 78xx must have dumped more dwords into Outbound FIFO while host performing single read. this situation safe host start reading consecutive dwords since FIFO level greater than result message followed destination data. following figure illustrates timing diagram reading data:
Page
AN-0045-00 APPLICATION NOTE
7814/7851/7854 Streaming
SYNC_CLK
SYNC_READ This single read since there between dwords waiting.
SYNC_OE_n
SYNC_DATA_OUT[31:0] 4567 89abcdef 01234567 89abcdef SYNC_OUT_LEVEL[0] 32-bit dwords SYNC_OUT_LEVEL[1] 32-bit dwords
01234567
reads arre allowed. FIFO pty.
there less dwords waiting read.
host polls SYNC_OUT_LEVEL[0] this cycle determ Outbound FIFO pty.
Figure Host reads data. Figure illustrates level signals used empty FIFO without reading while empty. read process began prior first cycle result data shown figure. When SYNC_OUT_LEVEL[1] transitions high there less than dwords waiting read from outbound FIFO. Since level signals updated cycle after change FIFOs, host must deassert read signal begin reading only dword time until FIFO empty until there more dwords FIFO. this situation there only more dwords waiting read from Outbound FIFO. Notice that after reading single dword, host must wait cycles before polling level signals determine there remaining dwords read.
AN-0045-00 APPLICATION NOTE
Page

7814/7851/7854 7814/7851/7854 Streaming Hifnsupplies Internet's m

Top Searches for this datasheet

Other recent searches