S3092 Silicon Germanium BiCMOS technology Complies with Telcordia

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S3092 Silicon Germanium BiCMOS technology Complies with Telcordia

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Part Number S3092 Revision February 2002
S3092
Silicon Germanium BiCMOS technology Complies with Telcordia, ITU-T, G.709 specifications Integrated Phase Lock Loop OC-192 with Digital Wrapper (DW) (9.953 10.709 Gbps) Reference frequency 155.52 equivalent rate) 16-bit parallel, 622.08 Mbps equivalent rate) LVDS data path Lock detect jitter differential serial interface Dual +3.3 -5.2 power supply Performs clock recovery 9.953 Gbps equivalent rate) serial data Synthesizes parallel output clock during lossof-signal conditions Postamp serial input 148-pin CBGA package Typical power dissipation
DEVICE SPECIFICATION
SONET/SDH/AOC-192 1:16 Receiver with Postamp
GENERAL DESCRIPTION
S3092 SONET/SDH receiver chip fully integrated deserializer/CDR with SONET OC-192 with Digital Wrapper (9.953 Gbps 10.709 Gbps) rate capability. S3092 receives OC-192 scrambled signal recovers clock from data. chip performs necessary serial-to-parallel functions conformance with SONET/SDH/Digital Wrapper transmission standards. device suitable SONETbased Aapplications. Figure shows typical network application. S3092 fully integrated OC-192/STM-64 Clock Data Recovery (CDR) demultiplexer (DeMUX). S3092 recovers synchronous signal from incoming 9.953 Gbps 10.709 Gbps serial data stream re-times demultiplexes serial data into parallel 622.08 Mbps equivalent rate) lines. detects Loss-of-Signal condition, outputs stable 622.08 equivalent rate) clock when serial data lost, provides 1:16 demultiplexing. also limiting postamp serial input small signal gain. chip used with 155.52 equivalent rate) reference clock. jitter LVDS interface guarantees compliance with biterror rate requirements Bellcore ITU-T standards.
APPLICATIONS
SONET/SDH-based transmission systems SONET/SDH modules SONET/SDH test equipment Aover SONET/SDH Section repeaters Drop Multiplexers (ADM) Broad-band cross-connects Fiber optic terminators Fiber optic test equipment
Figure System Block Diagram
INDUS (19201), GANGES (19202) HUDSON (19203)
S3091
S3092
S3092
S3091
INDUS (19201), GANGES (19202) HUDSON (19203)
S3092 SONET/SDH/AOC-192 1:16 Receiver with Postamp CONTENTS
Revision February 2002
DEVICE SPECIFICATION
FEATURES APPLICATIONS GENERAL DESCRIPTION CONTENTS LIST FIGURES LIST TABLES SONET OVERVIEW Data Rates Signal Hierarchy Frame Byte Boundary Detection S3092 OVERVIEW S3092 ARCHITECTURE/FUNCTIONAL DESIGN Receiver Description Postamp Clock Recovery Lock Detect Serial-to-Parallel Converter Power Sequencing Ordering Information
S3092 SONET/SDH/AOC-192 1:16 Receiver with Postamp LIST FIGURES
Revision February 2002
DEVICE SPECIFICATION
Figure System Block Diagram Figure SONET Structure Figure STS-192 Frame Format Figure Functional Block Diagram Figure S3092 Pinout Figure S3092 Package Figure Parallel Data Output Delay from POCLK Figure Data Invalid Window Figure S3092 LVDS Driver LVDS Input, Reference Only Figure -5.2 Post S3092 Input Coupled Termination, Reference Only Figure -5.2 Post S3092 Input Coupled Termination, Reference Only Figure External Loop Filter Figure Differential Voltage Measurement Figure Jitter Tolerance UIpp
LIST TABLES
Table SONET Signal Hierarchy Table Input Description Assignment Table Output Description Assignment Table Common Description Assignment Table Thermal Management Table Performance Specifications Table Absolute Maximum Ratings Table Recommended Operating Conditions Table Internally Biased Differential Input Characteristics Table Single-Ended Input Characteristics Table LVDS Output Characteristics Table LVTTL Input Characteristics Table LVTTL Output Characteristics Table Characteristics Table Internally Biased Differential Input Characteristics Table External Loop Filter Components Table Modes
S3092 SONET/SDH/AOC-192 1:16 Receiver with Postamp SONET OVERVIEW
Synchronous Optical Network (SONET) standard connecting fiber system another optical level. SONET, together with Synchronous Digital Hierarchy (SDH) administered ITU-T, forms single international standard fiber interconnect betwe ephone works diff erent countries. SONET capable accommodating variety transmission rates applications. SONET standard layered protocol with four separate layers defined. These are: Photonic Section Line Path
Revision February 2002
DEVICE SPECIFICATION
Frame Byte Boundary Detection SONET/SDH fundamental frame format STS192 consists transport overhead bytes followed Synchronous Payload Envelope (SPE) bytes. This pattern overhead 16,704 bytes repeated nine times each frame. Frame byte boundaries detected using bytes found transport overhead. (See Figure S3092 does provide A1/A2 detection alignment more details SONET operations, refer Bellcore SONET standard document. Figure SONET Structure
Functions Payload mapping Maintenance, protection, switching Scrambling, framing Optical transmission
Figure shows layers their functions. Each layers overhead bandwidth dedicated administration maintenance. photonic layer simply handles conversion from electrical optical back with overhead. responsible transmitting electrical signals optical form over physical media. section layer handles transport framed electrical signals across optical cable from next. functions this layer framing, scrambling, error monitoring. line layer responsible reliable transmission path layer information stream carrying voice, data, video signals. main functions synchronization, multiplexing, reliable transport. path layer responsible actual transport services appropriate signaling rates. Data Rates Signal Hierarchy Table contains data rates signal designations SONET hierarchy. lowest level basic SONET signal referred synchronous transport signal level-1 (STS-1). STS-N signal made byte-interleaved STS-1 signals. optical counterpart each STS-N signal optical carrier level-N signal (OC-N). chip supports OC-192 with Digital Wrapper (9.95328 Gbps 10.709 Gbps) rates.
Path layer
Path layer
Line layer
Line layer
Section layer
Section layer
Photonic layer
Photonic layer
Equipment
Fibre Cable
Equipment
Table SONET Signal Hierarchy
Elec. STS-1 STS-3 STS-12 STS-24 STS-48 STS-192 STM-1 STM-4 STM-8 STM-16 STM-64 ITU-T Optical OC-1 OC-3 OC-12 OC-24 OC-48 OC-192 Data Rate (Mbps) 51.84 155.52 622.08 1244.16 2488.32 9953.28
S3092 SONET/SDH/AOC-192 1:16 Receiver with Postamp
Figure STS-192 Frame Format
Rows Bytes Bytes
Revision February 2002
DEVICE SPECIFICATION
Transport Overhead Columns 5,184 bytes µsec
Synchronous Payload Envelope 16,704 Columns 16,704 150,336 bytes
S3092 SONET/SDH/AOC-192 1:16 Receiver with Postamp S3092 OVERVIEW
S3092 with DeMUX implements SONET/ deserialization functions. block diagram Figure shows basic operation chip. This chip used implement front SONET equipment, which consists primarily serial transmit interface serial receive interface. chip includes clock data recovery, serial-to-parallel conversion system timing. sequence operations S3092 follows: Receiver operations: Serial input limiting postamp Clock data recovery Serial-to-parallel conversion 16-bit parallel output Figure Functional Block Diagram
Revision February 2002
DEVICE SPECIFICATION
Suggested Interface Devices
AMCC AMCC AMCC AMCC AMCC AMCC S3091 S19201 S19202 S3196 S3090 S19203 OC-192 Transmitter OC-192 OC-48 MUX/DeMUX OC-192 SONET/SDH Mapper OC-192 Postamp OC-192 OC-192 Digital Wrapper
1:16 SERIAL PARALLEL
POUTP/N[15:0]
TIMING CAP1 CAP2 LOOP FILTER
RX622MCKP/N POCLKP/N
SERCLKOP/N REFCLKP/N TSTSIG LCKREFN LOCK DETECTOR LOCKDET CLOCK DIVIDER
RSTB TESTB POSTAMP SERDATIP/N
PHASE/FREQUENCY DETECTOR SERDATOP/N
S3092 SONET/SDH/AOC-192 1:16 Receiver with Postamp S3092 ARCHITECTURE/FUNCTIONAL DESIGN
Receiver Description S3092 receiver chip provides first stage digital processing receive SONET STS-192 bitserial stream. converts bit-serial 9.953 Gbps 10.709 Gbps data stream into 622.08 Mbps 669.33 Mbps 16-bit parallel data format. Table Reference Clock (REFCLK) required. Postamp S3092 limiting postamp takes differential serial data from SERDATIP/N pins provides small signal gain. input postamp either coupled. Clock Recovery Clock recovery, shown block diagram Figure generates clock that same frequency incoming data rate serial data input. clock phase aligned that samples data center data pattern. Clock Data Recovery (CDR) extracts synchronous signal from serial data input using frequency Phase Lock Loop (PLL). consists Voltage Controlled Oscillator (VCO), Phase/ Frequency Detectors (PFD), loop filter. frequency detector ensures predictable lock-up conditions. used during acquisition, serves means pulling into range data rate where phase detector capable acquiring lock. phase detector used designed give minimum static phase error PLL. When transition occurred, value sample vicinity transition indicates whether clock leads lags incoming data. phase detector then produces binary output accordingly. When loss-of-signal condition exists, goes inactive, locks onto Reference Clock (REFCLK) provide steady output clock. There pins (CAP1 CAP2) connect external capacitors resistors order adjust loop performance. phase relationship between edge transitions data those generated clock compared phase/frequency discriminator. Output
Revision February 2002
DEVICE SPECIFICATION
pulses from discriminator indicate required direction phase corrections. These pulses smoothed integral loop filter. output loop filter controls frequency Voltage Contr scil CO), generates recovered clock. loop filter transfer function optimized enable track jitter, tolerate minimum transition density expected received SONET data signal. total loop dynamics clock recovery yield jitter tolerance that exceeds minimum tolerance proposed SONET equipment Bellcore TA-NWT-000253 standard. Lock Detect S3092 contains lock detect circuit that monitors integrity serial data inputs. received serial data fails frequency test, will forced lock local reference clock. This will maintain correct frequency recovered clock output under loss-of-signal loss-of-lock conditions. recovered clock frequency deviates from local reference clock frequency more than typical value stated Table will declared lock. lock detect circuit will poll input data stream attempt reacquire lock data. recovered clock frequency determined within typical value stated Table will declared lock, lock detect output will active. inactive will also cause out-of-lock condition. Serial-to-Parallel Converter serial-to-parallel converter consists three 16-bit registers. first serial-in, parallel-out shift register, which performs serial parallel conversion. second 16-bit internal holding register, which transfers data from serial parallel register. falling edge POCLK, data holding register transferred output holding register which drives POUTP/N[15:0]. Power Sequencing order avoid latch required that -5.2 power applied S3092 minimum before application power.
S3092 SONET/SDH/AOC-192 1:16 Receiver with Postamp
Table Input Description Assignment
Name SERDATIP SERDATIN Level Diff.CML
Revision February 2002
DEVICE SPECIFICATION
Description Receive Serial Data Input. Differential high frequency serial data input limiting postamp small signal gain. Coplanar Waveguide Structure best results. Layout Recommendation application note. Characterization Report plot. Characterization Report Differential Input Voltage plot. Reference Clock. Differential reference clock input 155.52 MHz. will lock onto this reference absence serial input data. Internally biased terminated. Loop Filter Capacitors. external loop filter capacitor resistors connected these pins. Used adjust loop filter performance. Figure Lock Reference. Active Low. When active, will forced lock local reference clock input [REFCLK]. RX622MCK remains locked VCO. Signal Detect. Active Low. single-ended input driven external optical receiver module indicate loss received optical power. When inactive, data Serial Data (SERDATIP/N) pins will internally forced constant zero, will forced lock REFCLK inputs. When active, data SERDATIP/N pins will processed normally. used, leave open. Master Reset. Active Low. Reset input device. correct reset, this input must asserted Test Enable. Active Low. Used during production test bypass PLL. Pull High normal operation. Test Input Signal. Active Low. Signal used production test. Pull High normal operation.
REFCLKP REFCLKN CAP1 CAP2 LCKREFN
Diff.ECL
Analog LVTTL
RSTB TESTB TSTSIG
LVTTL LVTTL LVTTL
S3092 SONET/SDH/AOC-192 1:16 Receiver with Postamp
Table Output Description Assignment
Name POCLKP POCLKN Level LVDS
Revision February 2002
DEVICE SPECIFICATION
Description Parallel Clock Output. Regenerated 622.08 equivalent rate) differential output clock, synchronized parallel output data (see Figure Note that order comply with Optical Internetworking Forum (OIF) specifications, POCLKP POCLKN should exchanged module board. Parallel Data Output. Re-timed data from DeMUX rate 622.08 Mbps equivalent rate). first received. POUTP/N[15] most significant (corresponding each word, first transmitted). POUTP/N[0] least significant corresponding each word, last transmitted).
POUTP0 POUTN0 POUTP1 POUTN1 POUTP2 POUTN2 POUTP3 POUTN3 POUTP4 POUTN4 POUTP5 POUTN5 POUTP6 POUTN6 POUTP7 POUTN7 POUTP8 POUTN8 POUTP9 POUTN9 POUTP10 POUTN10 POUTP11 POUTN11 POUTP12 POUTN12 POUTP13 POUTN13 POUTP14 POUTN14 POUTP15 POUTN15 LOCKDET
LVDS
LVTTL
Lock Detect. Clock recovery indicator. Active High. High when internal clock recovery locked onto incoming data stream after internal delay. LOCKDET asynchronous output. 622.08 equivalent rate) clock output. This clock derived from clock.
RX622MCKP RX622MCKN
LVDS
S3092 SONET/SDH/AOC-192 1:16 Receiver with Postamp
Table Common Description Assignment
Name VCCDIG VCCLVDS DGND VCCLVTTL AGND AVEE VEEDIG THERMALGND -5.2 -5.2 Level +3.3 +3.3 +3.3 H13, A10, A13, A14, B14, C10, E13, L14, M10, N10, P11, P12, P13, Number
Revision February 2002
DEVICE SPECIFICATION
Description Digital LVDS Digital Ground LVTTL Connected Analog Ground Analog Digital Thermal Grounds
D14, B12, B13, D13, J13, E10, F10, G10, H10, J10,
VEE_FILTER VEE_VCO VEE_REFCLK
-5.2 -5.2 -5.2
Analog Filter Analog Analog REFCLK
Note: digital, analog, thermal grounds connected together package.
S3092 SONET/SDH/AOC-192 1:16 Receiver with Postamp
Figure S3092 Pinout
Revision February 2002
DEVICE SPECIFICATION
AGND
AGND
FILTER
AGND
TSTSIG
RSTB
DGND
DGND
RX622MCKN
DGND
DGND
REFCLKP
AGND
AGND
CAP1
AGND
AGND
DGND
VEEDIG
POCLKN
POCLKP
RX622MCKP
VEEDIG
VEEDIG
DGND
REFCLKN
AGND
AGND
CAP2
AGND
TESTEN
VCCLVTTL
VEEDIG
VCCLVDS
DGND
LOCKDET
VCCLVTTL
LCKREFN
REFCLK
AGND
VEEDIG
AGND
AGND
AVEE
THERMAL
THERMAL
THERMAL
THERMAL
THERMAL
DGND
POUT15N
AGND
AGND
THERMAL
THERMAL
THERMAL
THERMAL
THERMAL
THERMAL
POUT14N
POUT15P
SERDATIP
THERMAL
THERMAL
THERMAL
THERMAL
THERMAL
THERMAL
POUT14P
POUT13N
AGND
AGND
THERMAL
THERMAL
THERMAL
THERMAL
THERMAL
THERMAL
VCCLVDS
POUT13P
SERDATIN
THERMAL
THERMAL
THERMAL
THERMAL
THERMAL
THERMAL
VEEDIG
POUT12N
AGND
AGND
THERMAL
THERMAL
THERMAL
THERMAL
THERMAL
THERMAL
POUT11N
POUT12P
AGND
AVEE
POUT11P
DGND
AGND
AVEE
VCCLVDS
DGND
VEEDIG
VCCLVDS
DGND
VEEDIG
VCCDIG
DGND
POUT8P
POUT8N
VCCLVDS
POUT10N
DGND
POUT0P
POUT0N
POUT2P
POUT2N
POUT4P
POUT4N
POUT6P
POUT6N
DGND
VEEDIG
POUT9P
POUT9N
POUT10P
DGND
DGND
POUT1P
POUT1N
POUT3P
POUT3N
POUT5P
POUT5N
POUT7P
POUT7N
DGND
DGND
DGND
DGND
S3092 (Package View) (Die BOTTOM View)
S3092 SONET/SDH/AOC-192 1:16 Receiver with Postamp
Figure S3092 Package
Revision February 2002
DEVICE SPECIFICATION
Table Thermal Management
Device S3092 Package Power (70°C Ambient) 2.68 20.5 °C/W °C/W
Note: Application Note simulation results, thermal management suggestions, thermal profile package attachment.
S3092 SONET/SDH/AOC-192 1:16 Receiver with Postamp
Table Performance Specifications
Parameter Nominal Center Frequency Reference Clock Frequency Tolerance SERDATIP/N Input Return Loss (S11) (when driven differentially) Capture Range Acquisition Lock Time -220 9.953 -100 10.709 +100 +220 Units µsec
Revision February 2002
DEVICE SPECIFICATION
Condition
required meet SONET output frequency specification. With respect fixed reference frequency. Minimum transition density 50%. Guaranteed tested. With device already powered valid REFCLK.
Reference Clock Input Duty Cycle Reference Clock Rise Fall Times Frequency difference which goes lock (REFCLK compared divided down clock). Frequency difference which receive goes into lock (REFCLK compared divided down clock).
amplitude.
S3092 SONET/SDH/AOC-192 1:16 Receiver with Postamp
Table Absolute Maximum Ratings
Parameter Storage Temperature Supply -5.2 Supply LVTTL Input Voltage LVTTL Output Voltage LVDS Output Voltage Input Voltage Input Voltage LVTTL Input Current LVTTL Output Current
Electrostatic Discharge (ESD) Ratings S3092 rated following voltages based human body model: pins rated Volts.
Revision February 2002
DEVICE SPECIFICATION
-0.5 -0.5 -0.5 0.25 0.25 -450
-7.0 AGND AGND 1000
Units
Standards protection should adhered when handling devices ensure that they damaged. standards used defined ANSI standard ANSI/ESD S20.20-1999, "Protection Electrical Electronic Parts, Assemblies Equipment." Contact your local sales representative application notes.
Table Recommended Operating Conditions
Parameter Ambient Temperature Under Bias (Commercial) Junction Temperature Under Bias Voltage with Respect Voltage with Respect Supply Current, includes bias resistors Supply Current 3.135 -4.94 -5.2 3.465 -5.46 Units
S3092 SONET/SDH/AOC-192 1:16 Receiver with Postamp
Table Internally Biased Differential Input Characteristics
Parameters VINDIFF VINSINGLE RDIFF Description Differential Input Voltage Swing Single-Ended Input Voltage Swing (while driven differentially) Differential Input Resistance Input High Voltage Input Voltage AGND
Revision February 2002
DEVICE SPECIFICATION
1400 AGND
Units
Comments Figure Figure
Table Single-Ended Input Characteristics
Parameters Description Input Voltage Input High Voltage AGND AGND 1.225 AGND AGND 0.525 Units Conditions
Table LVDS Output Characteristics1, (See Figure
Symbol VOUTDIFF VOUTSINGLE Description Output High Voltage Output Voltage Output Differential Voltage Output Single-ended Voltage 1.25 0.85 1100 Unit Conditions Output loading line-to-line. Over process, voltage temperature range. Output loading line-to-line. Over process, voltage temperature range. Output loading line-to-line. Over process, voltage temperature range. Output loading line-to-line. Over process, voltage temperature range.
Output loading line-to-line. pull-down resistor line ground.
Table LVTTL Input Characteristics
Symbol Description Input High Voltage Input Voltage Input High Current Input Current -500 3.47 Unit Conditions LVTTL LVTTL
S3092 SONET/SDH/AOC-192 1:16 Receiver with Postamp
Table LVTTL Output Characteristics
Parameters Description Output High Voltage
Revision February 2002
DEVICE SPECIFICATION
Units
Condition
Output Voltage
Table Characteristics
Symbol JTOL Parameter Jitter Tolerance 15/(f 2400) 15/(f 103) 0.15 LCID CDUTY TTLH Consecutive Identical Digits RX622MCK POCLKP/N RX622MCKP/N Duty Cycle POCLKP/N Rise Time POUTP/N Rise Time TTHL POCLKP/N Fall Time POUTP/N Fall Time TCQ_MIN TCQ_MAX POUTP/N Delay from POCLKP/N POCLKP/N POUTP/N POCLKP/N POUTP/N Data Invalid Window with respect Falling Edge POCLKP. RSTB Minimum Pulse Width1 1000 Figure Figure Figure Figure 80%, line-to-line. Units (p-p) (p-p) (p-p) (p-p) (p-p) bits Test Conditions (Sinusoidal). Figure (Sinusoidal). Figure (Sinusoidal). Figure (Sinusoidal). Figure (Sinusoidal). Figure Number bits with transitions. line-to-line, SONET spec 45/55. 80%, line-to-line.
Guaranteed design.
S3092 SONET/SDH/AOC-192 1:16 Receiver with Postamp
Table Internally Biased Differential Input Characteristics
Parameters VINDIFF VINSINGLE RDIFF Description Differential Input Voltage Swing Single-ended Input Voltage Swing Differential Input Resistance Input High Voltage Input Voltage AGND
Revision February 2002
DEVICE SPECIFICATION
1600 AGND
Units
Comments Figure Figure
Table External Loop Filter Components
Symbol Description Resistor, Surface Mount, 0402 Capacitor, Surface Mount, 0603 larger Value Unit
Figure Parallel Data Output Delay from POCLK
POCLKP
POUTP
Tpdmin Tpdmax 1000
Tpdmin Tpdmax
S3092 SONET/SDH/AOC-192 1:16 Receiver with Postamp
Figure Data Invalid Window
Revision February 2002
DEVICE SPECIFICATION
AMCC: POCLK_P
OIF: RXCLK_P Tcq_min Tcq_max
Spec.
POUT_P/N Data
Note: Specs SERDES outputs.
Table Modes
Error Correcting Capability bytes 255-byte block bytes 255-byte block bytes 255-byte block bytes 255-byte block bytes 255-byte block bytes 255-byte block bytes 255-byte block Digital Wrapper (OTU2) Code Rate Showing Bandwidth Expansion Code Words Increase 2.82% Increase 3.66% Increase 4.51% Increase 5.37% Increase 6.25% Increase 7.14% Increase 7.59% Increase Increased SERDATIN Frequency 9.953 Gbps 10.234 Gbps 10.317 Gbps 10.402 Gbps 10.488 Gbps 10.575 Gbps 10.664 Gbps 10.709 Gbps Increased Input Clock (REFCLK) Frequency 155.52 159.90 161.21 162.53 163.87 165.24 166.62 167.32
Figure S3092 LVDS Driver LVDS Input, Reference Only
+3.3
Zo=50 Zo=50
+3.3
S3092
LVDS Input
S3092 SONET/SDH/AOC-192 1:16 Receiver with Postamp
Revision February 2002
DEVICE SPECIFICATION
Figure -5.2 Post S3092 Input Coupled Termination, Reference Only
Zo=50 Zo=50 -5.2 POST AMPLIFIER S3096
-5.2 S3092 SERDATIP/N
Figure -5.2 Post S3092 Input Coupled Termination, Reference Only
Zo=50 0.1µF Zo=50 0.1µF
-5.2 POST AMPLIFIER S3096
-5.2 S3092 SERDATIP/N
Figure External Loop Filter
CAP1 CAP2
S3092 SONET/SDH/AOC-192 1:16 Receiver with Postamp
Figure Differential Voltage Measurement
V(+)
Revision February 2002
DEVICE SPECIFICATION
VISINGLE V(-)
V(+) V(-) IDIFF ISINGLE
Note: with respect
Figure Jitter Tolerance UIpp GR-1377 Limit S3092 Capability
S3092 SONET/SDH/AOC-192 1:16 Receiver with Postamp
Ordering Information
Prefix Integrated Circuit Device 3092 Package CBGA
Revision February 2002
DEVICE SPECIFICATION
Revision
Prefix
XXXX
Device
Package
Revision
Applied Micro Circuits Corporation 6290 Sequence Dr., Diego, 92121 Phone: (858) 450-9333 (800) 755-2622 Fax: (858) 450-9885 http://www.amcc.com Applied Micro Circuits Corporation 6290 Sequence Dr., Diego, 92121 Phone: (858) 450-9333 (800) 755-2622 Fax: (858) 450-9885 http://www.amcc.com
AMCC reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. AMCC does assume liability arising application product circuit described herein, neither does convey license under patent rights rights others. AMCC reserves right ship devices higher grade place those lower grade. AMCC SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITAB -SUPPO ICATIONS, DEVICES SYSTEMS THER CRITICAL APPLICATIONS. AMCC registered trademark Applied Micro Circuits Corporation. Copyright 2002 Applied Micro Circuits Corporation. D525/R965

S3092 Silicon Germanium BiCMOS technology Complies with Telcordia

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