SONET/SDH/AOC-48 4-BIT TRANSCEIVER WITH BiCMOS LVPECL OC-48 TRANSMITTE

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SONET/SDH/AOC-48 4-BIT TRANSCEIVER WITH BiCMOS LVPECL OC-48 TRANSMITTE

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DEVICE SPECIFICATION
SONET/SDH/AOC-48 4-BIT TRANSCEIVER WITH BiCMOS LVPECL OC-48 TRANSMITTER WITH CLOCK GENERATOR SONET/SDH/AOC-12 4-BIT TRANSCEIVER RECEIVER
Drop Multiplexers (ADM) Broad-band cross-connects Fiber optic terminators Fiber optic test equipment
S3455 S3455 S3455
FEATURES
CMOS 0.18 micron technology Complies with Bellcore ITU-T specifications On-chip high-frequency clock generation clock recovery Supports OC-48 (2488.32 Mbps) with Reference frequency 155.52 166.62 Interface LVDS LVCMOS logic 4-bit LVDS data path FC-PBGA Diagnostic loopback mode Supports line timing Lock detect Signal detect input jitter LVDS interface Internal FIFO decouple transmit clocks Single supply Typical power under Available form
GENERAL DESCRIPTION
S3455 SONET/SDH transceiver chip fully integrated serialization/deserialization SONET OC-48 (2.488 Gbps 2.670 Gbps) interface device. S3455 receives OC-48 scrambled Non-Return Zero (NRZ) signal recovers clock from data. chip performs necessary serial-to-parallel parallel-to-serial functions conformance with SONET/SDH transmission standards. device suitable SONET-based applications. Figure shows typical network application. On-chip clock synthesis performed highfrequency Phase-Locked Loop (PLL) S3455 transceiver chip allowing slower external transmit clock reference. chip used with 155.52 166.62 MHz) reference clock support existing system clocking schemes. jitter LVDS interface compliant with biterror rate requirements Bellcore ITU-T standards. S3455 packaged FCPBGA, offering designers small package outline. S3455 also available form.
APPLICATIONS
Wavelength Division Multiplexing (WDM) equipment SONET/SDH-based transmission systems SONET/SDH modules SONET/SDH test equipment Aover SONET/SDH Section repeaters
Figure System Block Diagram
GANGES S19202 AMCC S3455 AMCC S3455 AMCC S3455
AMCC S3455 GANGES S19202
AMCC S3455 AMCC S3455
AMCC S3455 AMCC S3455
January 2002 Revision
S3455 S3455 OVERVIEW
SONET/SDH/AOC-48 4-BIT TRANSCEIVER WITH
S3455 divided into transmitter section receiver section. sequence operations follows: Transmitter Operations: 4-bit parallel input Parallel-to-serial conversion Serial output Receiver Operations: Clock data recovery from serial input Serial-to-parallel conversion 4-bit parallel output Internal clocking control functions transparent user.
S3455 transceiver implements SONET/SDH serialization/deserialization, transmission functions. block diagram Figure shows basic operation chip. This chip used implement front SONET equipment, which consists primarily serial transmit interface serial receive interface. chip handles functions these elements, including parallel-to-serial serial-to-parallel conversion, clock generation, system timing. system timing circuitry consists management data stream clock distribution throughout front end. Table shows suggested interface devices S3455.
Table Sugggested Interface Devices STS-192 POS/AAMCC S19202 SONET/SDH Mapper
January 2002 Revision
SONET/SDH/AOC-48 4-BIT TRANSCEIVER WITH
Figure S3455 Transceiver Functional Block Diagram
PHINITP/N TXCLK_SEL REFSEL[1:0] REFCLKP/N1 REFCLKP/N2 CLOCK SYNTHESIZER CLOCKS CSU-REFCLK TXLOCKDET
S3455
155/77 MCKP/N
REFCLKP/N POCLK÷4 RLPTIME BYPASSCLKP/N TXCAP1 TXCAP2 BYPASS TESTEN PINP/N[3:0] PICLKP/N SLPTIME LLEB
TIME
PCLKP/N PHERRP/N
Parallel Serial
TXDP/N TSDP/N
TXCLKP/N KILLRXCLKB TSCLKP/N
BACKUP REFERENCE GENERATOR TSCLKOFF CDR_REFCLK TIME
POCLKP/N
TXDP/N (Internal) RSDP/N RXCAP1 RXCAP2 SERIAL PARALLEL POUTP/N[3:0]
DLEB
LCKREFN
LOCKDET
RXLOCKDET
SDLVCMOS
RSTB
January 2002 Revision
S3455 S3455 TRANSCEIVER FUNCTIONAL DESCRIPTION
TRANSMITTER OPERATION
SONET/SDH/AOC-48 4-BIT TRANSCEIVER WITH
loop filter generates control voltage based average level phase discriminator output pulses. single external clean-up capacitor utilized part loop filter. loop filter's corner frequency optimized minimize output phase jitter.
S3455 transceiver chip performs serialization stage processing transmit SONET STS-48 data stream. converts 4-bit parallel data serial format 2488.32 Mbps equivalent rate). high-frequency clock generated from 155.52 166.62 frequency reference using integral frequency synthesizer consisting Phase-Locked Loop (PLL) circuit with divider loop. Diagnostic loopback (transmitter receiver) line loopback (receiver transmitter) provided. Other Operating Modes.
Timing Generator
timing generation function, seen Figure provides divide-by-4 rate version transmit serial clock. This circuitry also provides internally generated load signal, which transfers PINP/N[3:0] data from FIFO serial shift register. PCLK output divide-by-4 rate version transmit serial clock. PCLK intended divide-by-4 clock upstream multiplexing overhead processing circuits. Using PCLK upstream circuits will ensure stable frequency phase relationship between data coming into leaving S3455 device. timing generator also produces feedback reference clock clock synthesizer. counter divides synthesized clock down same frequency CSU-REFCLK. clock synthesizer maintains stability synthesized clock comparing phase internal clock with that CSU-REFCLK.
Clock Synthesizer
clock synthesizer, shown block diagram Figure monolithic that generates serial output clock frequency locked input Reference Clock (CSU-REFCLK). REFCLKP/N1 REFCLKP/N2 input must generated from crystal oscillator which frequency accuracy that meets value stated Table order Transmit Serial Clock (TSCLK) frequency have same accuracy required operation SONET system. REFCLK must meet phase noise requirements shown Figure meet jitter generation specifications given Table Lower accuracy crystal oscillators used applications less demanding than SONET/SDH. on-chip consists phase detector, which compares phase relationship between output CSU-REFCLK input, loop filter which converts phase detector output into smooth voltage, VCO, whose frequency varied this voltage.
Table Reference Jitter Limits
Operating Mode STS-48 Band Width Jitter
January 2002 Revision
SONET/SDH/AOC-48 4-BIT TRANSCEIVER WITH
Parallel-to-Serial Converter
parallel-to-serial converter shown Figure comprised FIFO parallel-to-serial register. FIFO input latches data from PINP/N[3:0] rising edge PICLK. parallel-to-serial register loadable shift register which takes parallel input from FIFO output. internally generated divide-by-4 clock, which phase aligned transmit serial clock described Timing Generator description, activates parallel data transfer between registers. serial data shifted parallel-to-serial register TSCLK rate.
S3455
prevent errors caused short setup hold times between timing domains, timing generator circuitry monitors phase relationship between PICLK internally generated clock. When potential setup hold time violation detected, phase error becomes active. When Phase Error (PHERR) conditions occur, PHINIT should activated recenter FIFO least PCLK periods). This done connecting PHERR PHINIT. When realignment occurs, bytes data will lost. user also take PHERR signal, process send output PHINIT such that idle bytes lost during realignment process. PHERR will inactive when realignment complete.
FIFO
FIFO added decouple internal external (PICLK) clocks. internally generated divideby-4 clock used clock data from FIFO. Phase Initialization (PHINIT) Lock Detect (LOCKDET) used center reset FIFO. PHINIT LOCKDET signals will center FIFO after third PICLK pulse. This order insure that PICLK stable. This scheme allows user have infinite PCLK PICLK delay through ASIC. Once FIFO centered, PCLK PICLK delay have maximum drift specified Table
RECEIVER OPERATION
S3455 transceiver chip provides first stage digital processing receive SONET STS-48 bit-serial stream. converts bit-serial 2.488 Gbps equivalent rate) data stream into 4-bit parallel data format. loopback mode provided diagnostic loopback (transmitter receiver). line loopback (receiver transmitter) also provided.
Clock Recovery
S3455 clock recovery device performs clock recovery function SONET OC-48 serial data links. chip extracts clock from serial data inputs provides retimed clock data outputs. 155.52 166.62 reference clock used phase locked loop start proper operation under loss signal conditions. integral prescaler phase locked loop circuit used multiply this reference nominal rate. clock recovery generates clock that same frequency incoming data rate serial data input. clock phase aligned that samples data center data pattern. phase relationship between edge transitions data those generated clock compared phase/frequency discriminator. Output pulses from discriminator indicate required direction phase corrections. These pulses smoothed integral loop filter. output loop filter controls frequency Voltage Controlled Oscillator (VCO), which generates recovered clock.
FIFO Initialization
FIFO initialized following three ways: During power once locked reference clock provided REFCLKP/N1 REFCLKP/N2 pins, LOCKDET will active initialize FIFO. When RSTB goes active, entire chip reset. This causes lock thus LOCKDET goes inactive. When reacquires lock, LOCKDET goes active initializes FIFO. Note: PCLK held reset when RSTB active. user also initialize FIFO raising PHINIT. During normal operation, incoming data passed from PICLK timing domain internally generated divide-by-4 clock domain. Although frequency PICLK internally generated clock same, their phase relationship arbitrary.
January 2002 Revision
S3455
SONET/SDH/AOC-48 4-BIT TRANSCEIVER WITH OTHER OPERATING MODES
Diagnostic Loopback
When Diagnostic Loopback Enable (DLEB) input active, loopback from transmitter receiver serial data rate diagnostic purposes. differential serial output data from transmitter routed serial-toparallel block place Receiver Serial Data (RSD). Transmit Serial Data/Transmit Serial Clock (TSD/TSCLK) outputs active. DLEB takes precedence over SDLVCMOS.
Frequency stability without incoming data guaranteed alternate reference input (CDR-REFCLK) that locks onto when data lost. frequency incoming signal varies value greater than that stated Table with respect CDR-REFCLK, will declared lock, will lock reference clock. assertion LVCMOS Signal Detect will also cause out-of-lock condition. loop filter transfer function optimized enable track jitter, tolerate minimum transition density expected received SONET data signal. total loop dynamics clock recovery yield jitter tolerance which exceeds minimum tolerance proposed SONET equipment Bellcore TA-NWT-000253 standard, shown Figure
Line Loopback
line loopback circuitry selects source data clock which output TSCLK. When Line Loopback Enable (LLEB) input inactive, selects data clock from parallel serial converter block. When LLEB active, forces output data multiplexer select data clock from Receive Serial Clock (RSCLK) inputs, receive-to-transmit loopback established serial data rate.
Lock Detect
S3455 contains lock detect circuit which monitors integrity serial data inputs. received serial data fails frequency test, will forced lock local reference clock. This will maintain correct frequency recovered clock output under loss signal loss lock conditions. recovered clock frequency deviates from local reference clock frequency value greater than that stated Table will declared lock. lock detect circuit will poll input data stream attempt reacquire lock data. recovered clock frequency determined within values stated Table will declared lock lock detect output will active. assertion SDLVCMOS will also cause lock condition.
Loop Timing
Serial Loop Timing (SLPTIME) mode, clock synthesizer S3455 bypassed, timing entire transmitter section controlled Receive Serial Clock, RSCLKP/N. This mode entered setting SLPTIME input LVCMOS high level. this mode, CSU-REFCLK input used. should carefully noted that internal continue operate this mode, continue source 155/77MCK RSD/ RSCLK, these signals being used, CSU-REFCLK input must properly driven. Reference Loop Timing (RLPTIME) mode, Parallel Output Clock (POCLK) from receiver used reference clock transmitter. this mode, CSU-REFCLK input used. 155/ 77MCK generated from POCLK this operating mode.
Serial-to-Parallel Converter
serial-to-parallel converter consists 4-bit registers. first serial-in, parallel-out shift register, which performs serial-to-parallel conversion clocked clock recovery block. falling edge Parallel Output Clock (POCLK), data parallel register transferred output parallel register which drives POUTP/N[3:0].
January 2002 Revision
SONET/SDH/AOC-48 4-BIT TRANSCEIVER WITH CHARACTERISTICS
Performance S3455 complies with jitter specifications proposed SONET/SDH equipment defined Bellcore Specifications: GR-253CORE, Issue December 1995 ITU-T Recommendations: G.958 document, when used specified. Input Jitter Tolerance Input jitter tolerance defined peak peak amplitude sinusoidal jitter applied input signal that causes equivalent optical/electrical power penalty. SONET input jitter tolerance requirements shown Figure Jitter Transfer jitter transfer function defined ratio jitter output OC-N/STS-N signal jitter applied input OC-N/STS-N signal versus frequency. Jitter transfer requirements shown Figure measurement condition that input sinusoidal jitter mask level Figure applied. Jitter Generation jitter generation serial clock serial data outputs shall exceed value specified Table when serial data input with jitter presented serial data inputs. REFCLK input must meet phase noise requirements shown Figure meet jitter generation value specified Table
Jitter Transfer Acceptable
S3455
Figure Input Jitter Tolerance Specification
Sinusodal Input Jitter Amplitude p-p)
0.15
Frequency
OC/STS Level (Hz) (Hz) (Hz) 6000 (kHz) (kHz) 1000
Figure Jitter Transfer Specification
slope dB/decade
Range
Frequency
OC/STS Level1,2
(kHz) 2000
(dB)
Bellcore Specifications: GR-253- CORE, Issue December 1995. ITU-T Recommendations: G.958.
January 2002 Revision
S3455
SONET/SDH/AOC-48 4-BIT TRANSCEIVER WITH
Table S3455 Transmitter Assignment Descriptions
Name PINP0 PINN0 PINP1 PINN1 PINP2 PINN2 PINP3 PINN3 PICLKP PICLKN Level LVDS Description Parallel Input Data, aligned PICLK parallel input clock. PINP/N[3] most significant (corresponding each word, first transmitted). PINP/N[0] least significant (corresponding each word, last transmitted). PINP/N[3:0] sampled rising edge PICLK. Internally terminated.
LVDS
Parallel Input Clock. divide-by-4, nominally duty cycle input clock, which PINP/N[3:0] aligned. PICLK used transfer data PINP/N inputs into holding register parallel-to-serial converter. rising edge PICLK samples PINP/N[3:0]. Internally terminated. Transmit Loop Filter Capacitor. external loop filter capacitor resistors connected these pins. Figure Phase Initialization. Rising edge will realign internal timing. Internally terminated. Transmit Clock Select. Used select between 155.52 77.76 clock 155/77MCKP/N output. TXCLK_SEL selects 155.52 output clock, high TXCLK_SEL selects 77.76 output clock. Transmit Serial Clock Off. This input should pulled default mode. When pulled high, shuts TSCLK macro save power. Transmit Serial Data. Differential serial data stream signals, normally connected optical transmitter module. Transmit Serial Clock that used retime signal. Parallel Clock. reference clock generated dividing internal clock normally used coordinate 4-bit wide transfers between upstream logic S3455 device. Phase Error. Active high. Pulses high during each PCLK cycle which there potential setup/hold timing violation between internal byte clock PICLK timing domains. Transmit Lock Detect. Goes High after locked clock provided CSU-REFCLK. TXLOCKDETB asynchronous output.
TXCAP1 TXCAP2 PHINITP PHINITN TXCLK_SEL
Analog LVDS LVCMOS
TSCLKOFF
LVCMOS
TSDP TSDN TSCLKP TSCLKN PCLKP PCLKN PHERRP PHERRN TXLOCKDET
Diff. Diff. LVDS
LVDS
LVCMOS
January 2002 Revision
SONET/SDH/AOC-48 4-BIT TRANSCEIVER WITH
Table S3455 Receiver Assignment Descriptions
Name RSDP RSDN SDLVCMOS Level Diff. LVCMOS Description
S3455
Receive Serial Data stream signals normally connected optical receiver module. Internally biased terminated. LVCMOS Signal Detect. Active High. single-ended LVCMOS input driven external optical receiver module indicate loss received optical power. When LVCMOS inactive, data POUTP/N[15:0] pins will internally forced constant state (one zero), transition RSDP/N will squelched. When LVCMOS active, data RSDP/N pins will processed normally. Receive Loop FIlter Capacitor. external loop filter capacitor resistors connected these pins. Figure Parallel Data Output bus, aligned Parallel Output Clock (POCLK). POUTP/N[3] most significant (corresponding each word, first received). POUTP/N[0] least significant bit. POUTP/N[3:0] updated falling edge POCLK.
RXCAP1 RXCAP2 POUTP0 POUTN0 POUTP1 POUTN1 POUTP2 POUTN2 POUTP3 POUTN3 POCLKP POCLKN
Analog
LVDS
LVDS
Parallel Output Clock. divide-by-4, nominally duty cycle, parallel output clock that aligned POUTP/N[3:0] 4-bit parallel output data. POUTP/N[3:0] updated falling edge POCLK. Receive Lock Detect. Clock recovery indicator that high when internal clock recovery locked onto incoming data stream. RXLOCKDET asynchronous output. Lock Reference. Active Low. When active, serial clock output will forced lock local reference clock input.
RXLOCKDET
LVCMOS
LCKREFN
LVCMOS
January 2002 Revision
S3455
SONET/SDH/AOC-48 4-BIT TRANSCEIVER WITH
Table S3455 Common Assignment Descriptions
Name REFCLKP1 REFCLKN1 REFCLKP2 REFCLKN2 Level LVDS Description Reference Clocks. Used reference internal clock frequency synthesizer. Internally terminated biased. REFCLKP/N1 connected 155.52 crystal (for OC-48 non-FEC rate) REFCLKP/N2 connected 166.63 crystal (for OC-48 rates). REFCLKP/N1 REFCLKP/N2 selected REFSEL[1:0] switch between non-FEC rates. Reference Clock Select. Selects between REFCLKP/N REFCLKP/N2. (See Table 18.) Diagnostic Loopback Enable. Active low. Selects diagnostic loopback. When DLEB inactive, S3455 device uses primary data (RSD) input. When active, S3455 device uses diagnostic loopback data from transmitter. TSD/TSCLK active DLEB. Line Loopback Enable. Active low. Selects line loopback. When LLEB active, S3455 will route data from RSD/RSCLK inputs TSD/TSCLK outputs. Kill Receive Clock Input. Active low. normal operation, KILLRXCLKB high. When this input low, will force POCLK output logic state. SLPTIME enables recovered clock from receive section used place synthesized transmit clock. Reference Clock Loop Time Select input. Active high. When active, RLPTIME enables POCLK from receiver used reference clock input transmitter. Master Reset. Reset input device. Active duration five REFCLK cycles. During reset, clocks disabled. Test Enable. Used production testing. normal operation. 155.52/77.76 clock output from clock synthesizer.
REFSEL1 REFSEL0 DLEB
LVCMOS
LVCMOS
LLEB
LVCMOS
KILLRXCLKB
LVCMOS
SLPTIME
LVCMOS
RLPTIME
LVCMOS
RSTB TESTEN 155/77MCKP 155/77MCKN
LVCMOS LVCMOS LVDS
January 2002 Revision
SONET/SDH/AOC-48 4-BIT TRANSCEIVER WITH
Table S3455 Common Assignment Descriptions (Continued)
Name BYPASSCLKP BYPASSCLKN BYPASS VSS_RSD VSS_TSD VSS_BYPASS VSS_TSCLK VSS_CMOS VSS_RX VSS_TX VSS_LVDS Level Diff. LVCMOS A14, D10, H11, M12, B14, B10, B12, L10, L12, P10, P12, L14, Description
S3455
Bypass Clock. Provides alternative serial clock bypassing internal VCO. Internally biased terminated. Active high. Selects between BYPASS clock clock. Connected. connect these pins power ground. Ground Ground Ground Ground Ground Ground Ground Ground Ground
VSS_REFCLK AVSS_RX AVSS_TX
Ground
Ground E13, E14, F13, G13, H13, H14, Ground
January 2002 Revision
S3455
SONET/SDH/AOC-48 4-BIT TRANSCEIVER WITH
Table S3455 Common Assignment Descriptions (Continued)
Name VDD_RSD VDD_TSD VDD_BYPASS VDD_TSCLK VDD_CMOS VDD_RX VDD_TX VDD_LVDS Level +1.8 +1.8 +1.8 +1.8 +1.8 +1.8 +1.8 +1.8 +1.8 C10, A10, A13, E10, F10, F11, G10, H10, J10, J11, K10, K12, M11, E11, E12, F12, G12, H12, J12, L13, Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply Description
AVDD_RX AVDD_TX VDD_REFCLK
+1.8 +1.8 +1.8
Power Supply Power Supply Power Supply
January 2002 Revision
SONET/SDH/AOC-48 4-BIT TRANSCEIVER WITH
Figure S3455 Pinout BottomView
S3455
VDD_ TSCLK VSS_ TSCLK VDD_ BYPASS VSS_ BYPASS
TSCLKP
TSCLKN
VDD_ TSCLK VSS_ TSCLK
VDD_TSD
TSDP
TSDN
VDD_TSD VSS_RSD
RSDN
RSDP
VSS_ BYPASS BYPASSCLKP BYPASSCL
VSS_ TSCLK
VDD_ TSCLK TSCLKOFF KILLRXCL
VSS_TSD VSS_TSD VDD_TSD VSS_TSD
DLEB
VSS_RSD VDD_RSD
RSTB
BYPASS
REFSEL0
SDLV CMOS
SLPTIME
TESTEN
VDD_ CMOS VSS_ CMOS
LPTIME
VDD_ CMOS
VSS_ CMOS
REFSEL1
TXCLK_
LCKREFN
VSS_ CMOS
AVSS_TX AVSS_TX AVDD_TX AVDD_TX
VDD_TX
VDD_TX
VSS_RX
VSS_RX
VSS_RX AVDD_RX AVSS_RX AVSS_RX AVSS_RX
TXCAP1
AVSS_TX AVDD_TX
VDD_TX
VDD_TX
VSS_TX
VSS_T
VSS_RX
VDD_RX
VDD_RX AVDD_RX AVSS_RX RXCAP1
TXCAP2 AVSS_TX AVDD_TX
VDD_TX
VSS_TX
VSS_T
VSS_T
VSS_RX
VDD_RX AVDD_RX AVDD_RX AVSS_RX RXCAP2
AVSS_TX AVSS_TX AVDD_TX
VDD_ LVDS VDD_ LVDS VSS_
VSS_ LVDS VSS_ LVDS
VSS_ LVDS
VSS_TX
VDD_RX
VDD_RX
VDD_RX AVDD_RX AVSS_RX AVSS_RX
AVSS_TX AVDD_TX AVDD_TX
VDD_
PHERRP
VDD_ LVDS VSS_ LVDS VDD_ LVDS VSS_ LVDS VDD_ LVDS VSS_ LVDS
VSS_ LVDS
POCLKP
VDD_ LVDS
AVDD_RX AVDD_RX AVSS_RX
REFCLKP1 REFCLKN1
VDD_ VSS_ LVDS
PICLKP
PINN0
PHERRN
PCLKN
POCLKN
POUTP1
VDD_ LVDS
TXLOCK- RXLOCKDET VSS_ LVDS 155/77 MCKP VDD_ LVDS VSS_ LVDS
VSS_ REFCLK
VDD_ REFCLK
PICLKN
PINP0
VSS_ LVDS
PCLKP
VSS_ LVDS
POUTN1
REFCLKP2 REFCLKN2
VDD_ LVDS
PINP1
VDD_ LVDS
PHINITN
VDD_ LVDS
POUTN2
VDDLVDS
VSS_ LVDS VDD_ LVDS VSS_ LVDS
155/77 MCKN VSS_ LVDS
VSS_ REFCLK
VDD_ REFCLK VSS_ LVDS
LVDS VSS_
PINP3
PINN1
PINN2
PHINITP
POUTN3
POUTP2
POUTP0
PINN3
VSS_ LVDS
PINP2
VSS_ LVDS
POUTP3
VSS_ LVDS
POUTN0
January 2002 Revision
S3455
Figure S3455 Pinout View
RSDP RSDN
SONET/SDH/AOC-48 4-BIT TRANSCEIVER WITH
VSS_RSD VDD_TSD
TSDN
TSDP
VDD_TSD
VDD_ TSCLK VSS_ TSCLK
TSCLKN
TSCLKP
VDD_ TSCLK VSS_ TSCLK VDD_ BYPASS VSS_ BYPASS
RSTB
VDD_RSD VSS_RSD
DLEB
VSS_TSD VDD_TSD VSS_TSD VSS_TSD
VDD_ TSCLK TSCLKOFF KILLRXCL
VSS_ TSCLK
VSS_ BYPASS BYPASSCL BYPASSCLKN
VDD_ CMOS VSS_ CMOS
TESTEN
SLPTIME
CMOS
LLEB
REFSEL0
BYPASS
VSS_ CMOS
LCKREFN
TXCLK_
REFSEL1
VSS_ CMOS
VDD_ CMOS
LPTIME
AVSS_RX AVSS_RX AVSS_RX AVDD_RX VSS_RX
VSS_RX
VSS_RX
VDD_TX
VDD_TX
AVDD_TX AVDD_TX AVSS_TX
AVSS_TX
RXCAP1 AVSS_RX AVDD_RX VDD_RX
VDD_RX
VSS_RX
VSS_RX
VSS_T
VDD_TX
VDD_TX
AVDD_TX AVSS_TX
TXCAP1
RXCAP2 AVSS_RX AVDD_RX AVDD_RX VDD_RX
VSS_RX
VSS_TX
VSS_T
VSS_T
VDD_TX
VDD_TX
AVDD_TX AVSS_TX
TXCAP2
AVSS_RX AVSS_RX AVDD_RX VDD_RX
VDD_RX
VDD_RX
VSS_TX
VSS_
VSS_ LVDS VSS_ LVDS
VDD_ VSS_ LVDS
AVDD_TX AVSS_TX
AVSS_TX
AVSS_RX AVDD_RX AVDD_RX
VDD_
POCLKP
VSS_
VDD_ VSS_ LVDS VSS_ VDD_ VSS_
PHERRP
VDD_ LVDS
AVDD_TX AVDD_TX AVSS_TX
RXLOCK- TXLOCKDET VSS_ LVDS 155/77 MCKP VDD_ LVDS VSS_ LVDS
VDD_ LVDS
POUTP1
POCLKN
PCLKN
PINN0
PICLKP
VDD_ VSS_
REFCLKN1 REFCLKP1
POUTN1
VSS_ LVDS
VSS_
PICLKN
VDD_ REFCLK
VSS_ REFCLK
155/77 MCKN VSS_ LVDS
VSS_ LVDS VDD_ LVDS VSS_ LVDS
VDDLVDS
POUTN2
VDD_
PHINITN
VDD_
PINP1
VDD_ LVDS
REFCLKN2 REFCLKP2
POUTP0
POUTP2
POUTN3
PHINITP
PINN2
PINN1
PINP3
VDD_ LVDS VSS_
VDD_ REFCLK VSS_
VSS_ REFCLK
POUTN0
VSS_
POUTP3
VSS_ LVDS
PINP2
VSS_ LVDS
PINN3
January 2002 Revision
SONET/SDH/AOC-48 4-BIT TRANSCEIVER WITH
Figure Package Drawing
S3455
Table Thermal Management
Device
S3455
Package Power
1.25
34.0° Still
Note: S3455 requires LFMP airflow industrial operating temperature 85°C/W. airflow heatsink required commercial operating temperature 70°C.
January 2002 Revision
S3455
SONET/SDH/AOC-48 4-BIT TRANSCEIVER WITH
Table Performance Specifications
Parameter Frequency Jitter Generation (CSU)
2.488
2.67
Units
Conditions
0.007 Reference Clock (REFCLKP/N1 REFCLKP/N2) Frequency Tolerance Reference Clock (REFCLKP/N1 REFCLKP/N2) Input Duty Cycle Reference Clock (REFCLKP/N1 REFCLKP/N2) Rise Fall Times Acquisition Time (CDR) 155.52 CDR_REFCLK Frequency difference which goes lock (CDR_REFCLK compared divided down clock) Frequency difference which receive goes into lock (CDR_REFCLK compared divided down clock) Jitter Generation (CDR) with locked SERDATIP/N (REFCLKP/N1/REFCLKP/N2) PCLK Delay RSTB TXLOCKDET Delay Latency Number clock cycles after PINP/N[X] appears TSDP/N
(rms)
Note: Output jitter measured SONET operating rate using appropriate filter, jitter, lock. required meet SONET output frequency specification.
-100
+100
amplitude. Minimum transition density 20%. Guaranteed tested. With device already powered valid ref. clk. Guaranteed tested.
µsec
Guaranteed tested. Note: This mode valid SLPTIME, RLPTIME LLEB mode only. Guaranteed tested. Guaranteed tested.
0.01
(rms)
6.43
REFCLK Guaranteed tested. Cycles
January 2002 Revision
SONET/SDH/AOC-48 4-BIT TRANSCEIVER WITH
Table Jitter Tolerance Specifications
Parameter Jitter Tolerance STS-48 Units Conditions
S3455
Data Pattern 27-1 PRBS
Table Absolute Maximum Ratings
Parameter Storage Temperature Voltage Volt Power pins with respect Voltage LVDS Input
Ratings S3455 rated following voltages based human body model: pins rated above 1000
-0.2
+2.0 VDD_LVDS
Units
Table Recommended Operating Conditions
Parameter Ambient Temperature Under Bias1 Voltage Volt Power planes with respect Voltage LVDS Input Voltage LVCMOS Input Volts Supply Current 1.71 1.89 VDD_LVDS VDD_CMOS Units
LFMP airflow required industrial operating temperature 85°C/W. airflow required commercial operating temperature 70°C.
January 2002 Revision
S3455
SONET/SDH/AOC-48 4-BIT TRANSCEIVER WITH
Table LVCMOS Input/Output Characteristics
Parameter Description Input High Voltage Input Voltage Input High Current Input Current Output High Voltage Output Voltage VDD_CMOS -0.2 VDD_CMOS -0.4 Units -200 Conditions
Table LVDS Input Characteristics
Parameter VICM VINSINGLE VINDIFF Description Input Voltage Input High Voltage Receiver Common Mode Range Single Ended Input Voltage Swing Differential Input Voltage Swing 0.775 0.96 0.90 1.25 1.42 1.80 1.56 1300 Units Conditions
Table LVDS Output Characteristics
Parameter VOUTSINGLE Description Output High Voltage Output Voltage Single Ended Output Voltage Swing Output Offset Voltage 1.16 0.81 1.00 1.60 1.20 1.37 Units Conditions line line line line line line line line
January 2002 Revision
SONET/SDH/AOC-48 4-BIT TRANSCEIVER WITH
Table Differential Output Characteristics
Parameter (CLOCK) Description Output High Voltage. VDD_ TSCLK -0.45 VDD_ TSCLK -1.15 VDD_ -0.45 VDD_ -1.15 VDD_ TSCLK -0.25 VDD_ TSCLK -0.73 1400 VDD_ -0.25 VDD_ -0.73 1400 Units
S3455
Conditions
(CLOCK) VOUTDIFF (CLOCK) VOUTSINGLE (CLOCK) (DATA)
Output Voltage. Serial Output Differential Voltage Swing Serial Output SingleEnded Voltage Swing Output High Voltage.
line-to-line. Figure line-to-line. Figure
(DATA) VOUTDIFF (DATA) VOUTSINGLE (DATA)
Output Voltage. Serial Output Differential Voltage Swing Serial Output SingleEnded Voltage Swing
line-to-line. Figure line-to-line. Figure
Table Input Characteristics
Parameter VINDIFF VINSINGLE RDIFF Description Differential Input Voltage Swing Single-Ended Input Voltage Swing Differential Input Resistance 1600 Units Conditions Figure Figure
Table Transmitter Timing Characteristics
Parameter TSCLK Frequency TSCLK Duty Cycle TSCLK Duty Cycle Distortion w.r.t. RSCLK BYPASSCLK SLPTIME, LLEB BYPASS modes) PICLK Duty Cycle tSPIN tHPIN tSTSD tHTSD PINP/N[3:0] Setup Time w.r.t. PICLK PINP/N[3:0] Hold Time w.r.t. PICLK Setup Time w.r.t. TSCLK Rising Hold Time w.r.t. TSCLK Rising PCLK PICLK drift after FIFO centered PCLK Duty Cycle TSD/TSCLK Rise Fall Time Description 2.488 2.67 Units
January 2002 Revision
S3455
Figure Transmitter Input Timing1
SONET/SDH/AOC-48 4-BIT TRANSCEIVER WITH
Figure Transmitter Output Timing1
TSCLKP tSTSD
tSPIN tHPIN
PICLKP
tHTSD
PINP/N[3:0]
Notes Timing: Timing measured from crossover point clock crossover point data.
Table Receiver Timing Characteristics Parameter Parameter
POCLKP/N POCLKP/N Rise Time POUTP/N Rise Time POCLKP/N Fall Time POUTP/N Fall Time POUTP/N Delay from POCLKP/N POUTP/N[3:0] Set-Up Time w.r.t. POCLK POUTP/N[3:0] Hold Time w.r.t. POCLK
1000
Units
Test Conditions line-to-line. 20%-80%, line-to-line. 20%-80%, line-to-line. Figure Figure Figure
Figure Parallel Data Output Delay from POCLK1
POCLKP
POUTP/N[3:0]
tPDmin tPDmin tPDmax 1000 tPDmax
Notes Timing: Timing measured from crossover point clock crossover point data.
January 2002 Revision
SONET/SDH/AOC-48 4-BIT TRANSCEIVER WITH
Table Reference Clock Select Modes
REFSEL1 REFSEL0 CSU-REFCLK Frequency CDR-REFCLK Frequency Mode
S3455
Non-FEC CSU_REFCLK CDR_REFCLK Non-FEC REFCLKP/N1 155.52 REFCLKP/N1 155.52 REFCLKP/N2 used CSU_REFCLK CDR_REFCLK REFCLKP/N1 155.52 REFCLKP/N2 166.62 Non-FEC CSU_REFCLKP/N CDR_REFCLK Non-FEC REFCLKP/N2 166.62 REFCLKP/N1 155.52 CSU_REFCLKP/N CDR_REFCLK REFCLKP/N2 166.62 REFCLKP/N2 166.62 REFCLKP/N1 used
Figure S3455 155.52 REFCLK Phase Noise Limit
Phase Noise (dBc)
Limit (100mUI jitter)
-100
Limit (100mUI jitter)
-120
-140
-160
1,000 10,000 100,000 1,000,000 10,000,000 100,000,000
Freq (Hz)
January 2002 Revision
S3455
SONET/SDH/AOC-48 4-BIT TRANSCEIVER WITH
Figure Differential Voltage Measurement
V(+) VSINGLE V(-)
V(+) V(-) VDIFF VSINGLE 0.0V
Note: V(+) V(-) algebraic difference input signals.
Figure Phase Adjust Timing1
4-10 BYTE CLOCKS
BYTE CLOCKS
PHERR PHINIT
PCLKP
PICLKP
TRANSFER (Internal)
byte clock 622.08
January 2002 Revision
SONET/SDH/AOC-48 4-BIT TRANSCEIVER WITH
Figure Differential Output V/+3.3 PECL Input Coupled Termination
S3455
+1.8
0.01
Zo=50
V/+3.3
0.01 S3455 TSDP/N TSCLKP/N
Zo=50
Figure LVDS Driver LVDS Input Termination
+1.8
Zo=50 Zo=50
+3.3
S3455 POUTP/N[3:0] POCLKP/N PCLKP/N PHERRP/N 155/77MCKP/N
LVDS
Figure Differential PECL Driver S3455 Differential Input Coupled Termination
0.01 0.01 Zo=50 -0.5 S3455 RSDP/N BYPASSCLKP/N Zo=50 -0.5 +1.8
January 2002 Revision
S3455
SONET/SDH/AOC-48 4-BIT TRANSCEIVER WITH
Figure V/+3.3 Differential PECL Driver S3455 LVDS Reference Clock Input Coupled Termination
V/3.3 0.01 0.01 Zo=50 Zo=50
-0.4
+1.8
-0.4 S3455 REFCLKP/N
OSCILLATOR
Figure LVDS Driver S3455 LVDS Inputs
+3.3 Zo=50 Zo=50 S3455 PINP/N[3:0] PICLKP/N PHINITP/N
+1.8
Figure External Loop Filter Components
RXCAP1 RXCAP2
TXCAP2
TXCAP1
January 2002 Revision
SONET/SDH/AOC-48 4-BIT TRANSCEIVER WITH
Ordering Information
PREFIX DEVICE PACKAGE
S3455
Integrated Circuit
3455
196PBGA
Prefix
XXXX Part
Package (S3455
Applied Micro Circuits Corporation 6290 Sequence Dr., Diego, 92121 Phone: (858) 450-9333 (800) 755-2622 Fax: (858) 450-9885 http://www.amcc.com
AMCC reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. AMCC does assume liability arising application product circuit described herein, neither does convey license under patent rights rights others. AMCC reserves right ship devices higher grade place those lower grade. AMCC SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. AMCC registered trademark Applied Micro Circuits Corporation. Copyright 2001 Applied Micro Circuits Corporation D145/R1084
January 2002 Revision

SONET/SDH/AOC-48 4-BIT TRANSCEIVER WITH BiCMOS LVPECL OC-48 TRANSMITTE

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