Diagram PORT COMPANION CIRCUIT Features channels protec

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Diagram PORT COMPANION CIRCUIT Features channels protec

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PACVGA200
Diagram
PORT COMPANION CIRCUIT
Features
channels protection port connector pins meeting IEC-61000-4-2 Level-4 requirements (8KV contact discharge) Very loading capacitance from protection diodes VIDEO lines, typical CMOS level-translating buffers with power down mode HSYNC VSYNC lines termination resistors VIDEO lines (matched typ.) Bi-directional level shifting N-channel FETs provided DDC_CLK DDC_DATA channels Compact 24-pin QSOP package
24-PIN QSOP PACKAGE
Product Description
PACVGA200 incorporates channels protection signal lines commonly found port. protection implemented with current steering diodes designed safely handle high surge currents encountered with IEC-1000-42 Level-4 Protection (8KV contact discharge). When channel subjected electrostatic discharge, current pulse diverted protection diodes into positive supply rail ground where safely dissipated. Separate positive supply rails provided VIDEO, SYNC channels facilitate interfacing with voltage Video Controller provide design flexibility multi-supply-voltage environments. non-inverting drivers provide buffering HSYNC VSYNC signals from Video Controller (SYNC1, SYNC2). These buffers accept input levels convert them CMOS output levels that swing between Ground VCC4. These drivers have nominal output impedance match characteristic impedance HSYNC VSYNC lines video cables typically used applications. N-channel FETs provide level shifting function required when controller operated lower supply voltage than monitor. Three termination resistors suitable terminating video signals from video also provided. These resistors have separate input pins allow insertion additional filtering, required, between termination point protection diodes. These resistors matched better than excellent signal level matching R/G/B signals. When PWR_UP input driven SYNC inputs floated without causing SYNC buffers draw current from VCC3 supply. When PWR_UP input SYNC outputs driven LOW. internal diode schematic below) also provided that VCC3 derived from VCC4, desired, connecting VCC3 V_BIAS. applications where VCC4 powered down, diode blocks current paths from DDC_OUT pins back powered down VCC4 rail protection diodes.
Schematic Diagram
2000 California Micro Devices Corp. rights reserved. PACVGA200 trademark California Micro Devices Corp. 4/00
C0641299
Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
ABSOLUTE MAXIMUM RATINGS Parameter VCC1, VCC2 VCC3 VCC4 supply voltage Temperature: Storage Operating Ambient Package power dissipation +150
PACVGA200
Unit
Rating -0.5, +6.0 -0.5, VCC1+0.5 -6.0, +6.0 -0.5, VCC2+0.5 -0.5, VCC3+0.5 -0.5, VCC4+0.5
ELECTRICAL OPERATING CHARACTERISTICS (over operating conditions unless specified other wise)
Symbol Parameter Conditions UNIT
CC2, ICC4
CC2, VCC4 supply current
VBIAS
VBIAS open circuit voltage pull-down resistor Input current inputs HSYNC, VSYNC inputs
inputs VCC2 VCC3 VCC4 SYNC inputs VCC4; PWR_UP VCC4; SYNC outputs unloaded VCC4 SYNC inputs 3.0V; PWR_UP VCC4; SYNC outputs unloaded VCC4 PWR_UP input SYNC outputs unloaded external current drawn from VBIAS 71.25 -4mA, VCC4 5.0V 4mA, VCC4 5.0V PWR_UP, VCC3 5.0V VCC2 3.0V VCC1 VCC1 VCC4 VCC4 (VCC2 VDDC_IN) 0.4V; VDDC_OUT= VCC2 (VCC2 VDDC_OUT) 0.4V; VDDC_IN= VCC2 VCC2 2.5V;
VCC4-0.8 78.75 0.15
IOFF
state leakage current, level shifting NFET Voltage drop across level shifting NFET when turned Input capacitance EO_1, EO_2, EO_3
tPLH tPHL VESD
Note Note
VCC1 2.5V; 1.25V; measured 1MHz SYNC drivers propagation delay SYNC drivers propagation delay SYNC drivers output rise fall times withstand voltage2, VCC1 VCC3 VCC4
These parameter applies only HSYNC VSYNC channels. IEC-61000-4-2 International Standard, Level contact discharge method. VCC1, VCC3 VCC4 must bypassed impedance ground plane with 0.2uF, inductance, chip ceramic capacitor each supply pin. pulse applied between applicable pins GND. pulse positive negative with respect GND. Applicable pins are: VIDEO_1, VIDEO_2, VIDEO_3, SYNC_OUT1, SD1, SYNC_OUT2, SD2, DDC_OUT1 DDC_OUT2. other pins protected industry standard Human Body model (MIL-STD-883, Method 3015). This parameter guaranteed design characterization.
Note
©2000 California Micro Devices Corp. rights reserved.
Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
4/00
Typical Connection Diagram
PACVGA200
resistor necessary between VCC3 ground protection against stream pulses required while PACVGA200 power-down state. value this resistor should chosen such that extra charge deposited into VCC3 bypass capacitor each pulse will discharged before next pulse occurs. maximum repetition rate specified IEC-61000-4-2 standard pulse second. When PACVGA200 power-up state, internal discharge resistor connected ground switch this purpose. same reason, VCC1 VCC4 also require bypass capacitor discharging resistors ground there other components system provide discharge path ground. GNDA, reference voltage resistors connected internally GNDD should ideally connected ground video
Pins
STANDARD PART ORDE RING INFORMATION Package Ordering Part Number Style Part Marking
QSOP PACVGA200Q
When placing order please specify desired shipping: Tubes Tape Reel.
2000 California Micro Devices Corp. rights reserved. 4/00
Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com

Diagram PORT COMPANION CIRCUIT Features channels protec

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