Features Standard Fault Tolerant differential CAN-Transceiver failure

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Features Standard Fault Tolerant differential CAN-Transceiver failure

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Features Standard Fault Tolerant differential CAN-Transceiver failure management current consumption mode <70µA data transmission rate kBaud Low-Dropout Voltage Regulator Side Switches Three High Side Switches with internal Charge Pump Power under-voltage Reset Generator Supervisor Window Watchdog Programable Cyclic Wake Timing Integrated fail-safe mechanism Standard SPI-Interface Wide input voltage temperature range Thermal protection Enhanced power P-DSO-Package Wakeup input
6266
P-DSO-28-6 Enhanced Power
Type 6266
Ordering Code request
Package P-DSO-28-6
Description
6266 monolithic integrated circuit enhanced power P-DSO-28-6 package, which incorporates failure tolerant speed CAN-transceiver differential mode data transmission, dropout voltage regulator internal external supply well interface control monitor Further there integrated additional features like three high side switches, side switches, window watchdog circuit reset circuit. offers current consumption mode, that reduces current typ. 70µA. designed withstand severe conditions automotive applications optimized low-speed data transmission kBaud).
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Configuration (top view)
CANH CANL OUTH1 OUTL1 OUTL2 OUTH2 OUTH3
P-DSO-28-6
(enhanced power package)
Figure
6266 Block Diagram
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Definitions Functions Symbol CANH CANL Function CAN-H line; HIGH dominant state Termination input CANH Reset output; open drain output; integrated pull active CAN-L line; dominant state Termination input CANL Ground; reduce thermal resistance place cooling areas close this pins. High side output controlled input and/or input, short circuit protected side output controlled, with active zener side output controlled, with active zener High side output controlled High side output controlled, cyclic wake mode controlled internal autotiming function Power supply; block directly with ceramic capacitor interface chip select not; active input; serial communication enabled pulling terminal LOW; input should only transitioned when LOW; internal active pull requires CMOS logic level inputs interface data out; this tristate output transfers diagnosis data control device; output will remain 3-stated unless device selected Chip-Select-Not (CSN); Table diagnosis protocol interface data receives serial data from control device; serial data transmitted control word with Least Significant (LSB) being transferred first: input active pull down requires CMOS logic level inputs; will accept data falling edge CLK-signal; Table input data protocol
OUTH1 OUTL1 OUTL2 OUTH2 OUTH3
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Definitions Functions (cont'd) Symbol Function interface clock input; clocks shiftregister; internal active pull down requires CMOS logic level inputs Output voltage regulator; logic supply, block with 100nF external ceramic capacitor directly external capacitor Receive data output; integrated pull LOW: becomes dominant, HIGH: becomes recessive Transmit data input; integrated pull LOW: becomes dominant, HIGH: becomes recessive Pulse Width Modulation control; high side switch Wake-Up input; detection external wake-up events within cyclic wake mode, active
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Functional Block Diagram
OUTL1 Charge Pump Drive OUTL2 Drive Protection Drive Switch Fail Detect OUTH2 Drive OUTH3 Drive OUTH1
UVLO
Band
Timer
Oscillator
Reset Generator Window Watchdog Mode Control
Fail Management
CANH CANL Filter
Output Stage Output Stage
Driver Temp. Protect Input Stage
Receiver
Fail Detect
akt.Dat.: 18.04.01
Figure
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6266 Functional Block Diagram
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Circuit Description
6266 monolithic which incorporates failure tolerant speed CANtransceiver differential mode data transmission, dropout voltage regulator internal external supply well interface control monitor Further there three high side switches, side switches, window watchdog circuit reset circuit integrated. Figure shows block diagram 6266. transceiver 6266 works interface between protocol controller physical bus-lines. Figure shows principle configuration network. normal operation mode differential signal transmitted/received. When wiring failures detected device automatically switches dedicated single-wire mode maintain communication. While data transferred, power consumption minimized multiple power operation modes. Further receive-only mode implemented that allows separate node diagnosis. reduce radiated electromagnetic emission (EME) dynamic slopes CANL CANH signals both limited symmetric. This allows unshielded twisted parallel pair wires bus. During single-wire transmission (one lines affected line failure) performance system degraded from differential mode. case transmission data input permanently dominant, both, CANH CANL transmitting stage disabled after certain delay time. This necessary prevent from being blocked defective protocol unit short input.
Controller RxD1 TxD1 RxD2
Controller TxD2
Transceiver1
Transceiver2
Line
Figure
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Operation Modes
6266 offers four different operation modes (see Figure that controlled input bits 9,10 (mode bits M0,M1) shown Table normal operation mode, receive-only mode, Vbat stand-by mode cyclic wake operation mode. cyclic wake mode itself subdivided into modes: cyclic cyclic mode. Both, cyclic wake Vbat stand-by designed periods that require communication CAN-Bus offer power mode, especially cyclic wake mode (<70µA). There also called supervisor feature, that monitors output voltage fallen below supervisor threshold VST. This feature activated every operation mode (see 6.7). Table Operation modes settings Mode (SPI Normal operation only Cyclic Wake Vbat stand-by Mode (SPI
Normal operation mode normal operation mode designed receive transmit data messages. Cyclic Wake Modes cyclic wake operation mode lowest power consumption achieved. This mode consists states, Cyclic Cyclic mode. state, almost functions deactivated. Only wake-up input, oscillator Power Reset circuit activated. voltage regulator switched soon voltage falls below load-threshold charge external capacitor (see Figure When nominal voltage level reached again, voltage regulator automatically deactivated minimize current consumption. oscillator used realize HS3-autotiming function that allows HS3-switch automatically enabled after programed time (via input bits 12,13 Table CANL line pulled-up battery supply voltage output this mode. There three possibilities enter cyclic mode from mode: cyclic wake time function falling edge wake-up wake
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state deactivated functions from HS-OFF mode activated. wake-up sets output LOW. state, long open window started. there valid trigger transition into state during this time, watchdog reset activated. correct trigger signal causes transition into cyclic state. This behavior grants watchdog feature also cyclic wake mode, with longer period time. This called
Table
settings cyclic wake period Input Bit12 Period 48ms 96ms 192ms cyclic wake-up
Input
battery supply voltage output. Wake-up requests Wake-Up lines immediately reported microcontroller setting RxD=LOW. power-on condition (Vbat supplied) watchdog reset, automatically switches 6266 Vbat stand-by mode. Also supply voltage drops below specified limits (undervoltage reset), transceiver automatically switched Vbat stand-by mode power down mode, respectively. RxD-only mode
Vbat stand-by mode Vbat stand-by mode voltage regulator remains active. CANL line pulled-
receive-only mode data CAN-bus transferred output, both output stages, CANH well CANL disabled. This means that data input transmitted bus. CANL line pulled-up output. This mode useful combination dedicated network-management software that allows separate diagnosis nodes. Table shows overview about different features 6266 their activation status operation modes.
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Power Down
Start Power
Normal Mode
functions active
Power Reset
RxD-Only
functions active
Vbat Stand-By
active 3VSU
Cyclic Wake Cyclic
OFF/ON
t>TWDR
Watch Reset
cyclic wake time wake
Cyclic
Figure
State Diagram
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Table Feature
Operation mode table Normal mode
stand-by mode
Vbat stand-by mode
Cyclic Wake
Cyclic Wake OFF/ON
Reset Watchdog Oscillator transmit receive OUTHS OUTHS OUTHS OUTHS cycl. ON1) OUTLS OUTLS
Timebase-Test Failsafe Supervisor output output
switched dominant; recessive
switched dominant; recessive
switched active wake-up interrupt
switched active wake-up interrupt
switched active wake-up interrupt
only active when selected also active when driven input automatically disabled when reset occures automatically disabled when reset resp. watchdog reset occures
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Failure Management
Normally differential signal transmitted resp. received. When wiring failure (see Table detected device automatically switches dedicated CANH CANL single-wire mode maintain communication necessary. Therefore equipped with differential receiver four single ended comparators (two each line). avoid false triggering external influences, single wire modes activated after certain delay time. soon failure disappears transceiver switches back differential mode after another time delay. failures monitored diagnosis protocoll SPI. Therefore possible distinguish failures failure groups output bits (see Table failures reported until transmission next word begins. differential receiver threshold typ. -2.5V. This ensures correct reception normal operation mode well failure cases with noise margin high possible. When failures detected, defective wire disabled switching affected termination output stage. Simultaneously multiplexing output receiver circuit switched unaffected single ended comparator. Table Failure line failure cases (according 11519-2) Failure Description CANL line interrupted CANH line interrupted CANL shorted Vbat, CANL CANH shorted CANL shorted CANH shorted Vbat; CANH CANL shorted CANH
failure) CANL shorted Vcc; CANL
failure) CANH shorted Vcc; CANH
reduce radiated electromagnetic emission (EME) dynamic slopes CANL CANH signals both limited symmetric. This allows unshielded twisted parallel pair wires bus. During single-wire transmission (one
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lines affected line failure) performance system degraded from differential mode. case transmission data input permanently dominant, both, CANH CANL transmitting stage disabled after certain delay time tTxD. This necessary prevent from being blocked defective protocol unit short input. CANH CANL pins protected against electrical transients which occur severe conditions automotive environments. order protect transceiver output stages from being damaged shorts lines, current limiting circuits integrated. CANL CANH output stage respectively protected additional temperature sensor, that disables them soon junction temperature exceeds maximum value. temperature shutdown condition output stages receiving messages from lines still possible. thermal shutdown CAN-transceiver circuit monitored output Table OBIT output bits failure diagnosis Failure Failure Failure Failure Failure Failure Failure Failure Dropout Voltage Regulator
TLE6266 able drive external loads output voltage tolerance less than addition regulator circuit drives internal loads like CANtransceiver circuit. cyclic wake operation mode voltage regulator switched control mechanism (see Figure current limitation typ. 180mA, grant that external capacitor charged quickly. normal operating mode external current should less then 45mA. This guaranteed system architecture. external reverse current protection recommended prevent output capacitor from being discharged negative transients input voltage.
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Stability output voltage guaranteed output capacitors CVCC Nevertheless applications require much larger output capacitance buffer output voltage case input voltage negative transients. Furthermore function e.g. reset 3V-supervisor circuit supported larger output capacitance because their reaction times. Therefore output capacitance CVCC recommended. During cyclic wake mode, switched off, depending output voltage level. Figure shows detailed flowchart control loop also graph voltage thresholds this mode.
Monitor Cyclic wake Mode
tCHARGE Charge Diagram VRESET
load threshold
Vcc< reset threshold VRESET
Charge (Switch LDO)
RESET after filteringtime
Figure
Cyclic wake flowchart
(serial peripheral interface)
16-bit wide programming word input word (see Table read data input this synchronized with clock input supplied diagnosis word appears synchronously data output (see Table transmission cycle begins when chip selected chip select input After input returns from word that been read becomes control word. output switches tristate status this point, thereby releasing other usage.
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output wiring failure read without transmission directly (CSN=LOW). transition signal from HIGH resets diagnosis 6266 offers feature monitor clock signal (CLK pin) during cyclic wake mode. there edges this signal, performs reset LOW. This feature activated HIGH. details timing please refer Figure Table IBIT Input Data Protocol Table OBIT Output Data Protocol
Input Data Disable Reset Comparator used Cyclic Wake Time Bit2 Cyclic Wake Time Bit1 Enable Mode Mode used Supervisor Enable LS-Switch LS-Switch Timebase Test HS-Switch HS-Switch HS-Switch Watchdog Trigger
H=ON L=OFF
Output Data Thermal Shutdown Transceiver Thermal Shutdown Switches Failure Failure Failure Failure Failure Failure Supervisor (Vcc Status Status Temperature Prewarning Switches Undervoltage Lockout Window Watchdog Reset Overcurrent Failure
H=ON L=OFF
Oscillator
6266 internal oscillator +/-15% accuracy. frequency oscillator measured within normal, Vbat stand-by RxD-only mode. This
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timebase test, activated input During this test, HS3-switch will activated cyclically. Window Watchdog Reset
When output voltage exceeds reset threshold voltage reset output switched HIGH after delay time tRD. This necessary defined start microcontroller when application switched soon under-voltage condition output voltage (VCC VRT) appears, reset output switched again. signal guaranteed down output voltage Please refer Figure reset timing diagram. After delayed reset (LOW HIGH transition window watchdog circuit started opening long open window. long open window allows microcontroller set-up trigger watchdog afterwards. Within long open window period watchdog trigger alternating detected "rising" "falling edge" sampling HIGH input trigger accepted when input becomes HIGH after transmission word. After each reset well after power condition default value input LOW. After every reset condition (watchdog reset, undervoltage reset) well transition cyclic wake mode from watchdog starts long open window. correct watchdog trigger immediately results starting window watchdog opening closed window followed open window (see Figure 14). From microcontroller service watchdog trigger inverting input alternating. "negative" "positive" edge meet open window time. correct watchdog service immediately results starting next closed window. Please refer Figure watchdog timing diagram. trigger signal does meet open window watchdog reset created setting reset output tWDR. Then watchdog starts again opening long open window. addition, output HIGH until next successful watchdog trigger, monitor watchdog reset. output also HIGH until watchdog correctly triggered after power-up/start-up. fail safe reasons TLE6266 automatically switched Vbat stand-by mode watchdog trigger failure occurs. cyclic wake mode, watchdog circuit automatically disabled.Both, undervoltage reset watchdog reset input bits LOW. 3V-Supervisor
output voltage falls below 3V-supervisor threshold VST, internal flip-flop LOW. output monitors this. normal operation this flip-flop
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activated input This feature useful e.g. monitor that data microcontroller might damaged application connected first time. supervisor uses comparator monitor voltage. Additional, there possibility disable this comparator order reduce current consumption. this, input first next step input High Side Switch
high side output OUTH1 able switch loads on-resistance typ. 25°C. This switch controlled either input input When input used enabled setting input HIGH. case both control inputs being active signal masked signal (see Figure High Side Switch Timing Diagram). output monitors thermal shutdown switches, whereas output flags thermal prewarning. this, microcontroller able reduce power dissipation 6266 switching functions minor priority before temperature threshold thermal shutdown reached. Further OUTH1 protected against short circuit overload. output indicates overload OUTH1. soon under-voltage condition supply voltage VUVOFF), switches automatically disabled under-voltage lockout circuit. This flagged output Moreover switches disabled when reset occurs. High Side Switch
high side output OUTH2 able switch loads on-resistance typ. 25°C. This switch controlled input output monitors thermal shutdown switches, whereas output flags thermal prewarning. this microcontroller able reduce power dissipation 6266 switching functions minor priority before temperature threshold thermal shutdown reached. soon under-voltage condition supply voltage VUVOFF), switches automatically disabled under-voltage lockout circuit. This flagged output Moreover switches disabled when reset occurs. 6.10 High Side Switch
high side output OUTH3 able switch loads ON-resistance typ. 25°C. This switch controlled input bits supply external wake-up circuits power mode (cyclic wake mode Vbat-standby mode), output OUTH3 periodically activated entering cyclic wake mode. autotiming period programable (see Table 2).This done, minimize current consumption depending cyclic wake time (see Figure 17).
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cyclic wake mode, signal used switches from cyclic cyclic state, correctly triggered within long open window (see Table 13). This called output monitors thermal shutdown switches, whereas output flags thermal prewarning. this microcontroller able reduce power dissipation 6266 switching functions minor priority before temperature threshold thermal shutdown reached. soon under-voltage condition supply voltage VUVOFF), switches automatically disabled under-voltage lockout circuit. This flagged output Moreover switches disabled when reset occurs. 6.11 Side Switches
side outputs OUTL1 OUTL2 able switch loads Their on-resistance typ. 25°C. This switches controlled input bits case high inrush currents built zener circuit (typ. activates switches protect them. diagnosis monitors thermal shutdown switches, whereas flags thermal prewarning. this microcontroller able reduce power dissipation 6266 switching functions minor priority before temperature threshold thermal shutdown reached. output bits giving feedback about current status OUTL1/OUTL2. soon under-voltage condition supply voltage VUVOFF), switches automatically disabled under-voltage lockout circuit. This flagged diagnosis addition outputs OUTL1 OUTL2 disabled when reset occurs. After second correct triggered watchdog, switches released usage. 6.12 Wake
This used wake 6266 with external signal from feature active during cyclic mode switch transceiver into cyclic mode before starting 6.13 Timebase Test
This test useful measure internal cycle time 6266. this information activate special functions routines (e.g. switch on/off LED) after certain number cyclic conditions cyclic wake mode, that depends timing. measure internal cyclic timing, input HIGH. Then switch automatically enabled times during closed window watchdog (see Figure
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closed window cycles)
2cycl. 2cycl. 2cycl.
2cycl.
2cycl.
2cycl.
Figure Timebase Test Diagram
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Electrical Characteristics Absolute Maximum Ratings Symbol Limit Values min. max. Unit Remarks
Parameter
Voltages Supply voltage Supply voltage Regulator output voltage input voltage (CANH, CANL) input voltage (CANH, CANL) Transient voltage CANH CANL
VCANH/L VCANH/L VBUS
-0.3 -0.3 -0.3 -0.3
human body model; 100pF, 1.5k human body model; 100pF, 1.5k 0.5s; tp/T 7637 0.5s; tp/T
Logic input voltages CLK, CSN, PWM, TxD) Logic output voltage (DO, RxD) Termination input voltage (RTH, RTL) Electrostatic discharge voltage CANH, CANL Electrostatic discharge voltage other Currents Output current; Output current; OUTH1 Output current; OUTH2 Output current; OUTH3 Output current; OUTL1 Output current; OUTL2
+0.3
VDO/RO/RD -0.3 VESD VESD
-0.3 -4000 -2000
+0.3
+0.3 4000 2000
IOUTH1 IOUTH2 IOUTH3 IOUTL1 IOUTL2
-0.7 -0.7 -0.2 -0.2
internally limited internally limited 0.5s; tp/T 0.5s; tp/T 0.5s; tp/T 0.5s; tp/T
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Absolute Maximum Ratings (cont'd) Symbol Limit Values min. max. Unit Remarks
Parameter
Temperatures Junction temperature Storage temperature
Tstg
Note: Maximum ratings absolute ratings; exceeding these values cause irreversible damage integrated circuit.
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Operating Range Symbol Limit Values min. max. V/µs
Outputs tristate Outputs tristate After rising above
Parameter Supply voltage Supply voltage slew rate Supply voltage increasing Supply voltage decreasing Logic input voltage (DI, CLK, CSN, PWM, Output current Output capacitor clock frequency Junction temperature Thermal Resistances Junction Junction ambient
Unit
Remarks
-0.5 -0.3 -0.3 -0.3
fCLK
Rthj-pin Rthj-a
measured
Thermal Prewarning Shutdown (junction temperatures) Thermal prewarning temperature Thermal shutdown temp. Ratio temp.
TjPW TjSD
diagnosis word; hysteresis 30°K (typ.) hysteresis 30°K (typ.)
TjSD TjPW 1.05
Thermal shutdown temp. TjSD
hysteresis 10°K (typ.)
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Electrical Characteristics
-100 normal mode; outputs open; CANtransceiver circuitry: voltages with respect ground; positive current defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values min. typ. max.
Unit Test Condition
Quiescent current Current consumption Quiescent current
ISSB1
Static quiescent current Voltage Regulator; Output voltage Output voltage Line regulation Load regulation
ISSB1 ISTAT
normal mode cycl. wake 48ms; VS=12V; Tj=25°C
0.1mA ICC< 30mA 100µA 10mA 0.1mA ICC< 30mA; Vss; 22µF; 100Hz< <100kHz note
Power supply ripple rejection PSRR Output current limit Dropvoltage
0.15 0.45
Wake-up Input Input current H-input voltage threshold L-input voltage threshold Hysteresis input voltage Input filtering time
ICCmax
VIHY tIFT
measured when output voltage dropped from nom. value obtained 13.5 inp. voltage
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Electrical Characteristics (cont'd)
-100 normal mode; outputs open; CANtransceiver circuitry: voltages with respect ground; positive current defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values min. typ. max.
Unit Test Condition
Reset Generator; Reset threshold voltage Reset output voltage
4.65
(VCC VRT) (IRO
Reset high output voltage Reset pull current Reset reaction time Reset reaction time Reset delay time cyl.)
VCC+
10.2
normal, RxD, stand-by mode cyclic wake mode
Supervisor; (bit output word) Supervisor threshold voltage Supervisor reaction time
diagnosis
Watchdog Generator
Closed window time cyl.) Open window time cyl.) tWDR Watchdog reset-puls time
Watchdog trigger time cyl.) Long open window (128 cyl.) tLOW
10.2
12.3 12.7
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Electrical Characteristics (cont'd)
-100 normal mode; outputs open; CANtransceiver circuitry: voltages with respect ground; positive current defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values min. typ. max.
Unit Test Condition
Switches Under-Voltage Lockout (bit output word) UV-Switch-ON voltage UV-Switch-OFF voltage UV-ON/OFF-Hysteresis
4.50
5.35 4.85
6.00 5.20
increasing decreasing
High Side Output OUTH1; (controlled input word) Static Drain-Source ON-Resistance; IOUTH1 -0.25 Active zener voltage
RDSON
-0.5 -0.3 -0.5
IOUTH1 0.25 IOUTH1 0.25 VOUTH1 OUTH1; OUTH1;
VOUTH1 Clamp diode forward voltage VOUTH1 Leakage current IOLH1 Switch delay time tdONH1
Switch delay time Overcurrent shutdown threshold Shutdown delay time Current limit
-5.0 -100
-3.0
tdOFFH1 ISDH1 tdSDH1 IOCLH1
-1.0 -2.0
-0.6 -1.0
Input control OUTH1; (high active) H-input voltage threshold L-input voltage threshold
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Electrical Characteristics (cont'd)
-100 normal mode; outputs open; CANtransceiver circuitry: voltages with respect ground; positive current defined flowing into pin; unless otherwise specified.
Parameter Hysteresis input voltage Pull down current Input capacitance
Symbol
Limit Values min. typ. max.
Unit Test Condition
5.25
VIHY
High Side Output OUTH2; (controlled input word) Static Drain-Source ON-Resistance; IOUTH2 -0.25 Active zener voltage
RDSON
-0.5
IOUTH2 0.25 IOUTH2 0.25 VOUTH2 high OUTH2; high OUTH2;
VOUTH2 Clamp diode forward voltage VOUTH2 Leakage current IOLH1 Switch delay time tdONH1
Switch delay time
-5.0 -100
-3.0
tdOFFH1
High Side Output OUTH3; (controlled input word) Static Drain-Source ON-Resistance; IOUTH3 -0.25 Active zener voltage
RDSON
-0.5
IOUTH3 0.25 IOUTH3 0.25 VOUTH3 high OUTH3; high OUTH3;
VOUTH3 Clamp diode forward voltage VOUTH3 Leakage current IOLH3 Switch delay time tdONH3
Switch delay time
-5.0 -100
-3.0
tdOFFH3
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Electrical Characteristics (cont'd)
-100 normal mode; outputs open; CANtransceiver circuitry: voltages with respect ground; positive current defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values min. typ. max.
Unit Test Condition
Side Output OUTL1 input word) Static Drain-Source ON-Resistance; IOUTL1 Active zener clamp voltage Leakage current Switch delay time Switch delay time
RDSON
IOUTL1 VOUTL1 85°C high OUTL1; high OUTL1;
VOUTL1 IOLL1 tdONL1 tdOFFL1
Side Output OUTL2 input word) Static Drain-Source ON-Resistance; IOUTL2 Active zener clamp voltage Leakage current Switch delay time Switch delay time
RDSON
IOUTL2 VOUTL2 85°C high OUTL2; high OUTL2;
VOUTL2 IOLL2 tdONL2 tdOFFL2
Timebase Test TBT(bit input word) timing timing activations
tTBON tTBOFF nTBT
cycl. cycl.
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Electrical Characteristics (cont'd)
-100 normal mode; outputs open; CANtransceiver circuitry: voltages with respect ground; positive current defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values min. typ. max.
Unit Test Condition
CAN-Transceiver Receiver Output HIGH level output voltage level output voltage Transmission Input HIGH level input voltage threshold level input voltage threshold HIGH level input current level input current Lines CANL, CANH Differential receiver recessive-to-dominant threshold voltage Differential receiver dominant-to-recessive threshold voltage CANH recessive output voltage CANL recessive output voltage CANH dominant output voltage
VdRxD(rd)
250µA
1.25mA
-0.3
-200
-200 -800
VdRxD(dr)
VCANH,r VCANL,r
0.10
0.15
0.30
VCC; RRTH VCC; RRTL ICANH
VCANH,d
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Electrical Characteristics (cont'd)
-100 normal mode; outputs open; CANtransceiver circuitry: voltages with respect ground; positive current defined flowing into pin; unless otherwise specified.
Parameter CANL dominant output voltage CANH output current
Symbol
VCANL,d ICANH
Limit Values min. typ. max.
Unit Test Condition
ICANL VCANH cycl. wake mode; VCANH VCANL cycl. wake mode; VCANL
CANL output current
ICANL
Voltage detection threshold Vdet(th) short-circuit battery voltage CANH CANL Voltage detection threshold short-circuit battery voltage CANH CANH wake-up voltage threshold CANL wake-up voltage threshold Wake-up voltage threshold hysteresis
Vdet(th)
VBAT VBAT
VBAT
stand-by/ cycl. wake mode
VCANH,w
VCANL,wu VCANH,wu failure cases failure case
VCANL,w
CANH single-ended receiver VCANH threshold CANL single-ended receiver threshold CANL leakage current CANH leakage current
VCANL ICANL,lk ICANH,lk
VCANL VCANH
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Electrical Characteristics (cont'd)
-100 normal mode; outputs open; CANtransceiver circuitry: voltages with respect ground; positive current defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values min. typ. max.
Unit Test Condition
Termination Outputs RTL, switch-on resistance output voltage switch series resistance ground switch-on resistance output voltage pull-down current pull-up current leakage current
RRTL VoRTL RoRTL RRTH VoRTH IRTH,pd IRTL,pu IRTH,lk
|Io| VBAT stand-by cycl. wake mode power mode failure cases failure cases VRTH VRTL
leakage current
IRTL,lk
CAN-Transceiver Dynamic Characteristics CANH CANL output transition time recessive-todominant CANH CANL output transition time dominant-torecessive
90%; 90%;
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Electrical Characteristics (cont'd)
-100 normal mode; outputs open; CANtransceiver circuitry: voltages with respect ground; positive current defined flowing into pin; unless otherwise specified.
Parameter Minimum dominant time wake-up CANL CANH Minimum wake-up time (wake-up) Failure cases detection time Failure case detection time Failure cases recovery time Failure cases recovery time Failure cases detection time Failure cases detection time Failure cases detection time Failure cases recovery time
Symbol
Limit Values min. typ. max.
Unit Test Condition
stand-by mode; power mode; normal operating mode normal operating mode normal operating mode normal operating mode normal operating mode stand-by mode; stand-by mode; stand-by mode; failures failure cases failure failure cases failure cases =100 failure cases
twu(min)
tWK(min)
tfail
Propagation delay tPD(L) TxD-to-RxD (recessive dominant)
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Electrical Characteristics (cont'd)
-100 normal mode; outputs open; CANtransceiver circuitry: voltages with respect ground; positive current defined flowing into pin; unless otherwise specified.
Parameter Propagation delay TxD-to-RxD HIGH (dominanat recessive)
Symbol
Limit Values min. typ. max.
Unit Test Condition
=100 failures failure cases failure failure cases failure cases failure cases
tPD(H)
Minimum hold time sleep command
th(min)
Edge-count difference (falling edge) between CANH CANL failure cases detection Edge-count difference (rising edge) between CANH CANL failure cases recovery permanent dominant disable time
normal operating mode
tTxD
normal mode
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Electrical Characteristics (cont'd)
-100 normal mode; outputs open; CANtransceiver circuitry: voltages with respect ground; positive current defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values min. typ. max.
Unit Test Condition
SPI-Interface Logic Inputs H-input voltage threshold L-input voltage threshold Hysteresis input voltage Pull current Pull down current Input capacitance CSN, Logic Output H-output voltage level L-output voltage level Tri-state leakage current Tri-state input capacitance
VIHY IICSN IICLK/DI
VCSN 5.25
-100
VDOH VDOL IDOLK
IDOH IDOL VCSN VCSN 5.25
Data Input Timing Clock period Clock high time Clock time Clock before setup time
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tpCLK tCLKH tCLKL tbef tlead
1000
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Electrical Characteristics (cont'd)
-100 normal mode; outputs open; CANtransceiver circuitry: voltages with respect ground; positive current defined flowing into pin; unless otherwise specified.
Parameter setup time Clock after high setup time hold time Input signal rise time Input signal fall time Data Output Timing rise time fall time enable time disable time valid time
Symbol
Limit Values min. typ. max.
Unit Test Condition
tlag tbeh tDISU tDIHO trIN tfIN
trDO tfDO tENDO tDISDO tVADO
impedance high impedance VCC; 0.7VCC;
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Timing Diagrams
High rising edge CLK: enabled. Status information transfered Output Shift Register
time High: Data from Shift-Register transfered Output Power Switches
actual Data
Data
Data will accepted falling edge CLK-Signal previous Status actual Status
State will change rising edge CLK-Signal
Data
actual Data
Figure
Data Transfer Timing
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Figure
SPI-Input Timing
Figure
Turn OFF/ON Time
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Figure
Valid Data Delay Time Valid Time
Figure
Enable Disable Time
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input
(SPI input
HSSwitch1
Figure
High Side Switch1 Timing Diagram
Vbat stand-by mode Cyclic Vbat stand-by mode Cyclic
Cyclic Wake Mode Cyclic
Cyclic Wake
Correct Trigger
Trigger
HSSwitch3
Cyclic Wake Time
Long Open Window tLOW
tWDR
Figure
Version 1.04
Cyclic Wake Timing Diagram
31Oktober 2001
6266
closed window
open window
Figure
Watchdog Timeout Definitions
Trigger
tCW+tOW tCW+tOW
Reset
tWDR
Watchdog timer reset
normal operation
timeout long)
normal operation
timeout short)
normal operation
Figure
Watchdog Timing Diagram
Version 1.04
31Oktober 2001
6266
Trigger
tCW+tOW
tCW+tOW
Reset
tWDR
output
Watchdog timer reset
normal operation undervoltage start
start
HIGH
activation microcontroller
Figure
Reset Timing Diagram
Current Consumption (typ.)
Current (µA) Current (µA) typ. 1000 10000 Cyclic Wake Time (ms) "Static" Current
Figure
Version 1.04
Current Consumption during Cyclic Wake Mode
31Oktober 2001
6266
Application
Vbat
CANH CANL
OUTL2 OUTL1 OUTH3 OUTH2 OUTH1
e.g. Infineon C164
6266
Figure
Application Circuit
Version 1.04
31Oktober 2001
6266
Package Outlines
P-DSO-28-6 (Plastic Dual Small Outline Package)
Figure
P-DSO-28-6 package
Sorts Packing Package outlines tubes, trays etc. contained Data Book "Package Information". Dimensions Version 1.04 31Oktober 2001
GPS05123
6266
Edition 1999-10-12 Published Infineon Technologies St.-Martin-Strasse D-81541 Infineon Technologies AG1999 Rights Reserved.
Attention please! information herein given describe certain components shall considered warranted characteristics. Terms delivery rights technical change reserved. hereby disclaim warranties, including limited warranties non-infringement, regarding circuits, descriptions charts stated herein. Infineon Technologies approved CECC manufacturer. Information further information technology, delivery terms conditions prices please contact your nearest Infineon Technologies Office Germany Infineon Technologies Representatives worldwide (see address list). Warnings technical requirements components contain dangerous substances. information types question please contact your nearest Infineon Technologies Office. Infineon Technologies Components only used life-support devices systems with express written approval Infineon Technologies, failure such components reasonably expected cause failure that life-support device system, affect safety effectiveness that device system. Life support devices systems intended implanted human body, support and/or maintain sustain and/or protect human life. they fail, reasonable assume that health user other persons endangered.
Version 1.04
31Oktober 2001

Features Standard Fault Tolerant differential CAN-Transceiver failure

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