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Incorporated Partnership Future Family ADM6326 10/100M+


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ADMtek
Incorporated
Partnership Future
Family ADM6326
10/100M+2G 10/100/1000M Ethernet Switch Controller
Overview
ADM6326 twenty-six ports switch controller. controller contains twenty-four RMII ports plus MII/GMII/TBI ports. Twenty-six MACS, non-blocking switch fabric, address table packet buffer. This allow simple system cost solution high port count layer-2 switch product. also support EEPROM interface which implemented smart application, such port enable/disable, VLAN setting setting. controller, switch engines data buffer memories built-in. chip desktop SOHO applications, each 10/100M port directly connects either 10BASE 100BASE devices. Additionally, ADM6326 breaks distance limitation 10BASE class 100BASE repeaters, increases throughput.
Features
24-port 10/100 Fast Ethernet plus Giga Ethernet switch controller. 10/100 ports support full half duplex. ports only support full duplex. Giga Giga ports 10/100/1000 speed, base auto-negotiation. MDC/MDIO monitor auto-negotiation status ports. memories embedded SSRAM. Ultra-high switch fabric provides non-blocking, full line speed blocking unicast broadcast traffic (patent pending). Support CoS, output queues/port, high normal priorities. Provide high priority (can pin), include VLAN TCP/IP TOS/DS (set EEPROM interface). Weighted round robin high priority frames normal frames. Intelligently turn on/off back-pressure follow control port with priority frames (patent pending) Support 24-port grouping VLAN, Giga port configured trunk ports (set pin) Flow control full duplex: supports 802.3x pause frame. half duplex: supports back pressure, include carrier mode. Broadcast storming prevention. Embedded (2K-4layers) address table. Hashing scheme: direct mode. Aging time: programmable, default 300sec. EEPROM: 93C46 interface. Support shift function reduce traces. 324-ball package. 1.8V/3.3V, 0.18u CMOS process.
ADMtek Incorporated 2001/10/23
Industrial Road, SBIP, Hsin-Chu (03)578-8879 (03)578-8871 Version 1.01 ADMtek Incorporated Confidential
ADM6326 Specification
Page
Block Diagram
N-WAY Monitor EEPROM Configuration Embedded Data Buffer/Address-Table 32Kx128 Embedded Link Table Embedded Table
Memory Control/ BIST Internal Memory
Port Port Port Port Port Port Port Port
Link Control/ BIST
Port
Port
Tx/Rx
Tx/Rx
Tx/Rx
Tx/Rx
Tx/Rx
Tx/Rx
Tx/Rx
Tx/Rx
Tx/Rx
GMII RMII RMII RMII RMII RMII RMII RMII RMII GMII
Hardware block diagram
Example System Diagram
6326 24+2G Switch Controller EEPROM (Option)
10/100PHY
10/100PHY Transformer
10/100PHY
Giga
Giga
Transformer
Example system diagram
ADMtek Incorporated 2001/10/23 Industrial Road, SBIP, Hsin-Chu Version 1.01 886-3-578-8879 :886-3-578-8871 ADMtek Incorporated Confidential
Tx/Rx
ADM6326 Specification
Page
Pins Assignment
G_TXD1[2] G_TXD1[3] G_TXD1[7] G_RXD061] G_RXD0[2] G_RXD0[0] G_RX_ER0 G_TX_ER0 G_TXE0 G_TXD0[3] G_TXD0[6] G_TXD0[7] RXD23[0] RXD22[1] RXD22[0] RXD21[0] TXE21 TXD20[0] RXD19[1] RXDV19 G_TXD1[1] G_TXD1[5] G_RXD0[7] G_RXD0[4] G_RXD0[1] G_RXDV0 G_CRS0 G_TXD0[0] G_TXD0[2] G_TXD0[5] RXD23[1] RXDV23 RXDV22 RXD21[1] RXDV21 TXD21[1] TXE20 RXD19[0] TXE18 G_LINK1 G_TXD1[0] G_TXD1[4] G_TXD1[6] G_RXD0[5] G_RXD0[3] G_COL0 G_LINK0 G_TXD0[1] G_TXD0[4] TXD23[1] TXE22 TXD22[1] RXD20[0] TXD21[0] TXD20[1] TXE19 TXD18[0] TXD18[1] G_COL1 G_CRS1 TXD19[0] TXD19[1] RXD17[1] G_RXD1[0] G_RX_ER1 G_TX_ER1 G_TXE1 G_RXC0 VDDi G_TXC0 TXE23 TXD23[0] TXD22[0] RXD20[1] RXDV20 VDDi VDDo VDDi VDDo VDDi RXD18[1] RXD17[0] RXDV17 G_RXD1[2] G_RXD1[1] G_RXC1 RXDV18 RXD18[0] TXD17[0] RXD16[1] G-RXD1[5] G-RXD1[4] G_RXDV1 G_TXC1 TXD17[1] TXE17 RXD16[0] RXDV16 G-RXD1[7] G-RXD1[6] G_RXD1[3] G_REFCLK VDDi VDDi TXE16 TXD16[1] TXDE0 TXD0[0] TXD0[1] TXD1[1] RXD0[0] RXDV0 RESET_N VDDo VDDo TXD16[0] HIGH_PORT[21] RXDV1 TXE1 TXD1[0] RXD0[1] HIGH_PORT[14] VDDi RXD1[0] RXD1[0] TXD2[1] TXD2[0] VDDi RXD2[1] RXDV2 TXE2 TXD3[1] VDDo VDDo RECALL TEST[2] SCAN_EN SCAN_MODE VDDi EESK TEST[0] TEST[1] RXD2[0] RXD3[1] TXE3 TXD3[0] VDDi RXDV3 RXD3[0] TXD4[0] EEDI SHIFT_LED LED_CLK RXDV14 RXD14[0] EECS EEDO TXD4[1] TXE4 TXD5[1] TXD5[0] VDDi VDDo VDDi VDDo VDDi RXD14[1] TXE15 QFLED_N RXDV4 RXD4[0] TXE5 HIGH_PORT[0] HIGH_PORT[2] HIGH_PORT[8] HIGH_PORT[11] RXD13[0] RXD4[1] RXD6[1] TXE6 RXD7[0] REFCLK MDIO TXD15[1] TXD15[0] RXD15[1] HIGH_PORT[5] HIGH_PORT[9] TXE12 RXD13[0] RXDV15 RXD13[1] TXE13 RXD15[0] RXDV5 RXD5[0] RXD6[0] TXD7[0] RXDV7 RXD7[1] TXD9[1] TXE9 TXD10[1] RXDV10 TXD11[0] RXD11[1] RXDV13 RXDV6 RXD5[1] TXD7[1] TXD8[1] TXE8 RXDV8 TXD9[0] RXD9[0] TXD10[0] RXD10[0] TXE11 RXD11[0] HIGH_PORT[3] HIGH_PORT[6] TXD12[1] TXD12[0] RXD12[0] RXD13[1] TXE14 HIGH_PORT[1] HIGH_PORT[4] HIGH_PORT[7] HIGH_PORT[10] RXDV12 RXD12[1] TXD14[1] TXD14[0] RXD6[0] RXD6[1] TXE7 TXD8[0] RXD8[0] RXD8[1] RXDV9 RXD9[1] TXE10 RXD10[1] TXD11[1] RXDV11
HIGH_PORT[25]] HIGH_PORT[24] HIGH_PORT[23] HIGH_PORT[22] HIGH_PORT[20] HIGH_PORT[19] HIGH_PORT[18] HIGH_PORT[17] HIGH_PORT[13] HIGH_PORT[16] HIGH_PORT[15] HIGH_PORT[12]
Pins assignment
Descriptions
Name Type Descriptions
EEPROM Interface
EEDO NA16# EEDI EESK XFC# EECS EEDO: Data Output serial EEPROM. Inputs configuration information ADM6326. Internally pull down (50K Ohm). EEDI: Data Input serial EEPROM. ADM6326 outputs data EEPROM. Internally pull down (50K Ohm). EESK: Clock input serial EEPROM. ADM6326 outputs clock signal EEPROM. Internally pull Chip Select serial EEPROM. EECK/s:50ns, h:0ns Internally pull down.
GMII Interface
ADMtek Incorporated 2001/10/23
Industrial Road, SBIP, Hsin-Chu Version 1.01
886-3-578-8879 :886-3-578-8871 ADMtek Incorporated Confidential
ADM6326 Specification
G_TXD0[0] G_TXD0[1] G_TXD0[2] G_TXD0[3] G_TXD0[4] G_TXD0[5] G_TXD0[6] G_TXD0[7] G_TXD1[0] G_TXD1[1] G_TXD1[2] G_TXD1[3] G_TXD1[4] G_TXD1[5] G_TXD1[6] G_TXD1[7] G_RXD0[0] G_RXD0[1] G_RXD0[2] G_RXD0[3] G_RXD0[4] G_RXD0[5] G_RXD0[6] G_RXD0[7] G_RXD1[0] G_RXD1[1] G_RXD1[2] G_RXD1[3] G_RXD1[4] G_RXD1[5] G_RXD1[6] G_RXD1[7] G_TXE0 TXD0[8] G_TXE1 TXD1[8] G_RXDV0 RXD0[8] G_RXDV1 RXD1[8] G_TXC0 G_TXC1
Page
G_TXD0[7:0] presents data byte transmitted from Giga port0 1000BASE-T mode. G_TXD0[3:0] presents data nibble transmitted from Giga port0 100BASE-TX 10BASE-T mode. mode, G_TXD0[7:0] used TXD0[7:0].
G_TXD1[7:0] presents data byte transmitted from Giga port1 1000BASE-T mode. G_TXD1[3:0] presents data nibble transmitted from Giga port1 100BASE-TX 10BASE-T mode. mode, G_TXD1[7:0] used TXD1[7:0].
G_RXD0[7:0] presents data received byte Giga port0 1000BASE-T mode. G_RXD0[3:0] presents data nibble received Giga port0 100BASE-TX 10BASE-T mode. mode, G_RXD0[7:0] used RXD0[7:0].
G_RXD1[7:0] presents data received byte Giga port1 1000BASE-T mode. G_RXD1[3:0] presents data nibble received Giga port1 100BASE-TX 10BASE-T mode. mode, G_RXD1[7:0] used RXD1[7:0].
Transmit enable. mode, G_TXE0 used TXD0[8]. Transmit enable. mode, G_TXE1 used TXD1[8]. Receive data valid. mode, G_RXDV0 used RXD0[8]. Receive data valid. mode, G_RXDV1 used RXD1[8]. GMII transmit clock from Giga port0, provide 125Mhz 1000BASE-T mode. GMII transmit clock from Giga port1, provide 125Mhz 1000BASE-T mode.
ADMtek Incorporated 2001/10/23
Industrial Road, SBIP, Hsin-Chu Version 1.01
886-3-578-8879 :886-3-578-8871 ADMtek Incorporated Confidential
ADM6326 Specification
G_RXC0 RBC0_0 Receive clock. Receive 125Mhz clock Giga port0 1000BASE-T mode, 25Mhz clock 100BASE-TX mode, 2.5Mhz clock 10BASE-T mode. mode, G_RXC0 used RBC0_0. G_RXC1 RBC1_0 Receive clock. Receive 125Mhz clock Giga port1 1000BASE-T mode, 25Mhz clock 100BASE-TX mode, 2.5Mhz clock 10BASE-T mode. mode, G_RXC1 used RBC1_0. G_TX_ER0 TXD0[9] G_TX_ER1 TXD1[9] G_RX_ER0 RXD0[9] G_RX_ER1 RXD1[9] G_LINK0 G_LINK1 G_CRS0 G_CRS1 G_COL0 RBC0_1 G_COL1 RBC1_1 G_REFCLK Transmit error. mode, G_TX_ER0 used TXD0[9]. Transmit error. mode, G_TX_ER1 used TXD1[9]. Receive error. mode, G_RX_ER0 used RXD0[9]. Receive error. mode, G_RX_ER1 used RXD1[9]. transmit clock TXCLK Giga port0 100BASE-TX 10BASE-T mode. transmit clock TXCLK Giga port1 100BASE-TX 10BASE-T mode. Carrier sense. Carrier sense. Collision 100BASE-TX 10BASE-T mode. mode, G_COL0 used RBC1_0. Collision 100BASE-TX 10BASE-T mode. mode, G_COL1 used RBC1_1. 125Mhz reference clock.
Page
ADMtek Incorporated 2001/10/23
Industrial Road, SBIP, Hsin-Chu Version 1.01
886-3-578-8879 :886-3-578-8871 ADMtek Incorporated Confidential
ADM6326 Specification Reduced Interface
TXE0 TXE1 TXE2 TXE3 TXE4 TXE5 TXE6 TXE7 TXE8 TXE9 TXE10 TXE11 TXE12 TXE13 TXE14 TXE15 TXE16 TXE17 TXE18 TXE19 TXE20 TXE21 TXE22 TXE23 V15, W20, H17, B20, B18, C13,
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Transmit Enable. TXE0~23 shows that ADM6326 presenting recovered decoded data TXD0~23[1:0]. TXE0~23 indicates that presenting di-bits TXD0~23[1:0] Reduced transmission. TXE0~23 shall asserted synchronously with first nibble preamble shall remain asserted while di-bits transmitted presented Reduced MII. TXE0~23 shall negative prior first REFCLK rising edge following final di-bit frame. TXE0~23 shall transition synchronously with REFCLK. TXE22 G_LED_SEL configure display mode Giga port. Default internal pull down. Show information 10M_Link_Act. 100M_Link_Act. 1000M_Link_Act. Duplex_Col. ADM6326 provide VLAN grouping TXE23 (pin D11) pull Default internal pull down. TXE21 should pull-up when Giga ports connected with Giga PHY. Default internal pull down.
ADMtek Incorporated 2001/10/23
Industrial Road, SBIP, Hsin-Chu Version 1.01
886-3-578-8879 :886-3-578-8871 ADMtek Incorporated Confidential
ADM6326 Specification
TXD0[1:0] TXD1[1:0] TXD2[1:0] TXD3[1:0] TXD4[1:0] TXD5[1:0] TXD6[1:0] TXD7[1:0] TXD8[1:0] TXD9[1:0] TXD10[1:0] TXD11[1:0] TXD12[1:0] TXD13[1:0] TXD14[1:0] TXD15[1:0] TXD16[1:0] TXD17[1:0] TXD18[1:0] TXD19[1:0] TXD20[1:0] TXD21[1:0] TXD22[1:0] TXD23[1:0]
Page
H3,H2 Transmit Data. These bundle signals output from ADM6326 Reduced connecting device. These signals transited synchronously with rising edge TXE0~23. When TXE0~23 being asserted, each period TXE0~23, ADM6326 drives recovered encoded data into TXD0~23[1:0] transmission. While TXE0~23 de-asserted, TXD0~23[1:0] will have effect upon Reduced connecting device. TXD0~23[1:0] shall transition synchronously with REFCLK. When TXE0~23 being asserted, TXD0~23[1:0] accepted transmission PHY. TXD0~23[1:0] shall "00" indicate idle when TXE0~23 de-asserted. Values TXD0~23[1:0] other than "00" when TXE0~23 de-asserted reserved out-of-band signaling defined). Values other than "00" TXD0~23[1:0] while TXE0~23 de-asserted shall ignored PHY. Giga port[1:0] will provide interface TXD20[1:0] pull Default internal pull low. Y11, TXD21[1:0] pull down Giga ports connected with Giga PHY. W15, Default internal pull V16, Y19, TXD22[1:0] configure display mode 10/100M port. Default internal pull low. U18, H18, Giga port[1:0] will provide trunk function TXD23[0] pull G17, Default internal pull low. C20, TXD23[1]: Default internal pull low. D19, C17, B17, C14, C12,
ADMtek Incorporated 2001/10/23
Industrial Road, SBIP, Hsin-Chu Version 1.01
886-3-578-8879 :886-3-578-8871 ADMtek Incorporated Confidential
ADM6326 Specification
RXDV0 RXDV1 RXDV2 RXDV3 RXDV4 RXDV5 RXDV6 RXDV7 RXDV8 RXDV9 RXDV10 RXDV11 RXDV12 RXDV13 RXDV14 RXDV15 RXDV16 RXDV17 RXDV18 RXDV19 RXDV20 RXDV21 RXDV22 RXDV23
Page
Carrier Sense Receive Data Valid. RXDV0~23 shall asserted when receiver idle. specific definition idle 10BASE-T 100BASE-X contained IEEE 802.3 IEEE 802.3u. RXDV0~23 also shows that receiving data presented RXD0~23[1:0] from Reduced connecting device. RXDV0~23 being asserted asynchronous detection carrier criteria relevant operating mode. That 10BASE-T mode, when squelch passed 100BASE-X mode, non-contiguous zeroes bits detected, carrier detected. Loss carrier shall result de-assertion RXDV0~23 synchronous cycles REFCLK which presents first di-bit nibble onto RXD0~23[1:0]. additional bits presented RXD0~23[1:0] following initial de-assertion RXDV0~23, then shall assert RXDV0~23 cycles REFCLK which present second di-bit each nibble, deassert RXDV0~23 cycles REFCLK which present first di-bit nibble. During false carrier event, RXDV0~23 shall remain asserted duration carrier activity. data RXD0~23[1:0] considered valid once RXDV0~23 being asserted. However, since assertion RXDV0~23 asynchronous relative REFCLK, data RXD0~23[1:0] shall "00" until proper receive signal decoding takes place.
ADMtek Incorporated 2001/10/23
Industrial Road, SBIP, Hsin-Chu Version 1.01
886-3-578-8879 :886-3-578-8871 ADMtek Incorporated Confidential
ADM6326 Specification
RXD0[1:0] RXD1[1:0] RXD2[1:0] RXD3[1:0] RXD4[1:0] RXD5[1:0] RXD6[1:0] RXD7[1:0] RXD8[1:0] RXD9[1:0] RXD10[1:0] RXD11[1:0] RXD12[1:0] RXD13[1:0] RXD14[1:0] RXD15[1:0] RXD16[1:0] RXD17[1:0] RXD18[1:0] RXD19[1:0] RXD20[1:0] RXD21[1:0] RXD22[1:0] RXD23[1:0] Y10, V12, Y18, W19, T18, U20, F20, D20, E18, A19, D14, B15, A14, B12,
Page
Receive Data. These bundle signals input from Reduced connecting device. RXD0~23[1:0] shall transition synchronously REFCLK. each clock period which RXDV0~23 being asserted, RXD0~23[1:0] transfers bits recovered data from PHY. some cases (e.g. before data recovery during error conditions) pre-determined value RXD0~23[1:0] transferred instead recovered data. RXD0~23[1:0] shall "00" indicate idle when RXDV0~23 de-asserted. Values RXD0~23[1:0] other than "00" when RXDV0~23 recovered from RXDV0~23 de-asserted reserved out-of-band signaling defined). Values other than "00"on RXD0~23[1:0] while RXDV0~23 recovered from RXDV0~23 deasserted shall ignored MAC. Upon assertion RXDV0~23, shall ensure that RXD0~23[1:0]="00"until proper receive decoding takes place. These pins will high impedance, ignore input when RXDV0~23 negative.
Management Data Clock. Provides reference clock MDIO signal
MDIO
Management Data Input/output. This provides channels ADM6326 Transceivers transfer control information status.
Display
QFLED# Buffer Full Faulty Display. This occurs when packet lost flow control disabled. flow control enabled PAUSE frames sent, buffer full will flash. found faulty, will always (See function description) Clock serial output. Data serial output.
LED_CLK SHIFT_LED
ADMtek Incorporated 2001/10/23
Industrial Road, SBIP, Hsin-Chu Version 1.01
886-3-578-8879 :886-3-578-8871 ADMtek Incorporated Confidential
ADM6326 Specification High Priority Frame
High_Port[0] High_Port[1] High_Port[2] High_Port[3] High_Port[4] High_Port[5] High_Port[6] High_Port[7] High_Port[8] High_Port[9] High_Port[10] High_Port[11] High_Port[12] High_Port[13] High_Port[14] High_Port[15] High_Port[16] High_Port[17] High_Port[18] High_Port[19] High_Port[20] High_Port[21] High_Port[22] High_Port[23] High_Port[24] High_Port[25] Priority setting port0~port23. High high priority. Internally pull down.
Page
Configuration
Back Pressure Mode. Internally pull down. Back Pressure Disable reserved jam. Carrier mode aborted after continuous times collision pull down. Full Duplex Flow Control. When 802.3 flow control disable, PAUSE frame will sent.
NA16# XFC#
Miscellaneous
REFCLK RESET# Clock reference input 50MHz Reduced MII. Synchronous clock reference receiving, transmitting, control interface. RESET#. Active low. power reset initiate ADM6326 state machines statuses enter initial default state. Besides, will turned when power testing failed. Whenever rising edge asserted, ADM6326 will recall EEPROM 886-3-578-8879 :886-3-578-8871 ADMtek Incorporated Confidential
RECALL
ADMtek Incorporated 2001/10/23
Industrial Road, SBIP, Hsin-Chu Version 1.01
ADM6326 Specification
TEST[0] TEST[1] TEST[2] SCAN_MODE SCAN_EN
Page
Power
VDDi E10, E13, H16, 1.8V L16, N16, T11, T13, E12, J16, M16, 3.3V T12, D16, D17, E11, E14, E17, G16, H10, H11, H12, H13, J10, J11, J12, J13, K10, K11, K12, K13, K16, Table Pins description
VDDo
ADMtek Incorporated 2001/10/23
Industrial Road, SBIP, Hsin-Chu Version 1.01
886-3-578-8879 :886-3-578-8871 ADMtek Incorporated Confidential
ADM6326 Specification
Page
EEPROM Content
EEPROM setting must 16-bit mode.
EEPROM
Function
Control
[15:8]
017C Bit[15]: Softw_reset dft=0 Bit[14]: dft=0 Bit[13]: dft=0 Bit[12]: Hash algorithm: direct (dft), hashing, Bit[11]: 16-col-abort disable: enable abort (dft=1) (May by-pin), Bit[10:9]: length: 1536 (dft), 1522, 1518, reserved, Bit[8]: Cascade mode: cascade, normal,
[7:0]
Bit[7:4]: Aging time: 0000 disable aging 1000 fast aging 0001 300sec 600sec (dft) 0010 600sec 1200sec Bit[3:0]: Half-duplex defer time (IPG): bit[3]: sign-bit: add, bit[2:0] nibble bit-time: 0000 (dft)
Suggest
017C
0810
Control
Bit[15]: Reserved filtered: forward (dft) Bit[14] Bit[13:12]: mode: disable jam, all, carrier (dft pin) Bit[11:8]: number mode: 1010 time (dft)
Bit[7:4]: weight round-robin 6A28 number between high priority packets 0000 unlimited, 0001 0010 (dft.), 1111 Bit[3]: Priority enable, disable, enable (dft) Bit[2]: Bit[1]:
Giga_phy[1] Giga_phy[0] Led_mode1 Led_mode[1:0]
Bit[0]: Reserved Bit[15] =1:giga port1 giga_phy, 0:giga_port use10/100 phy.(def Bit[14] =1:giga port0 giga_phy, 0:giga_port use10/100 phy.(def Bit[13]: Reserved Bit[12]: giga_port led_mode (dft) Bit[11:10]: port23~0 mode: (dft) Bit[9:0]: port disable, port 25~16, enable (dft) Bit[15:0]: port disable, port 15~0, enable (dft)
C000
Port disable Port disable
0000
ADMtek Incorporated 2001/10/23
Industrial Road, SBIP, Hsin-Chu Version 1.01
886-3-578-8879 :886-3-578-8871 ADMtek Incorporated Confidential
ADM6326 Specification
NWAY monitor disable NWAY monitor disable Bit[9:0]: Disable MDIO monitor status, port25~16, 0000 enable (dft) Bit[15:0]: Disable MDC/MDIO monitor status, port15~0, 0000 enable (dft) Bit[15:14]: Dis_sync P25~24, Disable Bit[7:0]: port23~16 speed setting, only CAFF giga logic, function NWAY monitor Only valid giga mode. disable mode (dft), (dft), 100M Bit[13:12]: enable port25 (G1)~port24 (G0), GMII (dft), PCS, Bit[11:10]: port25 (G1) speed 10M, 100M, 1000M (dft) reserved Bit[ port24 (G0) speed 10M, 100M, 1000M (dft) reserved Bit[15:0]: Port 15~0, (dft), 100M, Bit[15:13]: 111b. Bit[12:10]: 111b. Duplex setting Bit[ Port25 duplex setting, only function NWAY monitor disable mode, half duplex (dft), FFFF full duplex Note: port24 (G0), port25 (G1) must full duplex(def) mode when speed 1000M. Bit[15:0]: Port15~0 duplex setting, only function NWAY monitor disable mode, half duplex, full duplex, Bit[9:0]: VLAN port-grouping1, 03ffh (dft) Bit[15:0]: VLAN port-grouping1, ffffh (dft) Bit[9:0]: VLAN port-grouping 0000h (dft) Bit[15:0]: VLAN port-grouping 0000h (dft) Bit[9:0]: VLAN port-grouping 0000h (dft) Bit[15:0]: VLAN port-grouping 0000h (dft) Bit[9:0]: VLAN port-grouping 0000h (dft) Bit[15:0]: VLAN port-grouping 0000h (dft) Bit[9:0]: VLAN port-grouping 0000h (dft) Bit[15:0]: VLAN port-grouping 0000h (dft) Bit[9:0]: VLAN port-grouping 0000h (dft) Bit[15:0]: VLAN port-grouping 0000h (dft) Bit[9:0]: VLAN port-grouping 0000h (dft) Bit[15:0]: VLAN port-grouping 0000h (dft) Bit[9:0]: VLAN port-grouping 0000h (dft) Bit[15:0]: VLAN port-grouping 0000h (dft)
Page
Speed setting
FFFF
Duplex setting
FFFF 03FF FFFF 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Port group Port group Port group Port group Port group Port group Port group Port group Port group Port group Port group Port group Port group Port group Port group VIII Port group VIII
ADMtek Incorporated 2001/10/23
Industrial Road, SBIP, Hsin-Chu Version 1.01
886-3-578-8879 :886-3-578-8871 ADMtek Incorporated Confidential
ADM6326 Specification
802.3ab pause enable (From link partner with dis_nway) 802.3ab pause enable (From link partner with dis_nway) 802.3x write enable 802.3x write enable 803.3ab asymmetric direction (toward link partner with dis_nway) 803.3ab asymmetric direction (toward link partner with dis_nway) back pressure enable Bit[9:0]: port25~16, 802.3x flow control enable, disable (dft setting). enable NWAY enable, will follow NWAY monitor result. NWAY disable, will force from link partner which means device receive frame. Bit[15:0]: port15~0, 802.3x flow control enable,0 disable (dft setting). enable NWAY enable, will follow NWAY monitor result. NWAY disable, will force from link partner which means device receive frame. Bit[9:0]: port25~16, write FC-bit (register4, bit10, enable, enable (dft). Bit[15:0]: port15~0, write FC-bit (register4, bit10, enable, enable (dft). Bit[9:0]: Asymetric direction port 25~16. (dft setting) NWAY enable, will follow NWAY monitor result. When NWAY enabled. will force toward link partner which means device transmit frrame.
Page
03FF FFFF
03FF FFFF 03FF
Bit[15:0]: Asymetric direction port 15~0.(dft setting) FFFF nway enable, will follow NWAY monitor result. When nway enabled. will force toward link partner which means device transmit frame.
Bit[9:0]: port23~16, back pressure enable, disable, (dft setting). Note: back pressure back pressure Bit[15:0]: port15 back pressure enable, disable, (dft setting). enable Note: back pressure VLAN threshold bit[12:10]: VLAN priority threshold, (dft 04h) VLAN priority enable bit[9:0]: port25~16, VLAN priority enable, disable (dft). VLAN threshold bit[15:0]: port15~0, VLAN priority enable, disable (dft). VLAN priority enable TOS/DS priority bit[9:0]: port25~16, TCP/IP TOS/DS priority enable, disable (dft). enable TOS/DS priority bit[15:0]: port15~0, TCP/IP TOS/DS priority enable, disable (dft). enable bit-map bit[15:0]: bit-map[63:49], (dft bit-map bit[15:0]: bit-map[48:32], (dft bit-map bit[15:0]: bit-map[31:16], (dft bit-map bit[15:0]: bit-map[15:0], (dft Auto-turn-off bit[9:0]: Port25~16, automatically turn down flow-control back-pressure, priority enable receive priority packets, disable (dft) Auto-turn-off bit[15:0]: Port15~0, automatically turn down flow-control back-pressure, priority enable receive priority packets, disable (df) 03AE 0416 0276 02DE 03AE 0416 0003 0003 02C4 032C 800C 4C17 Reserve Reserved
03FF FFFF 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 03AE 0416 0276 02DE 03AE 0416 0003 0003 02C4 032C 800C 4C17 0000
ADMtek Incorporated 2001/10/23
Industrial Road, SBIP, Hsin-Chu Version 1.01
886-3-578-8879 :886-3-578-8871 ADMtek Incorporated Confidential
ADM6326 Specification
written Bit[10]: Extra written enable after reset, disable (dft) done, clear Bit[9:5]: written register address Bit[4:0]: written GPHY regester data Bit[15:0]: written data Bit[15:0]: GPHY written data Bit[10]:High_Port_cfg_enable ,eeprom prioritize outside pins 0=disable (dft)
Page
0000
address GPHY address data GPHY data High_Port_cfg_en
0000 0000 0000 0000
High_Port[25:16] 0=disable (dft) High_Port[15:0] 0=disable
Table EEPROM content
ADMtek Incorporated 2001/10/23
Industrial Road, SBIP, Hsin-Chu Version 1.01
886-3-578-8879 :886-3-578-8871 ADMtek Incorporated Confidential
ADM6326 Specification
Page
Function Description
ADM6326 high performance, cost, quality assurance 26-port Fast Ethernet Controller dedicated 24+2G-port switch solutions. This chip operates 50MHz fully complies with IEEE series specifications. switch operations include forwarding scheme, packet filtering, address learning, buffer management, display, etc. Packets from Reduced interface should stored memory. Then, source address learning, packet filtering, retransmission known unknown port(s) implemented based real application.
Reset Restart
When ADM6326 starts embedded memory self-test mode.
Port Interface
8.2.1 10/100Mbps Reduced Interface Each port ADM6326 supports Reduced interfaces, which uses TXE0~23, TXD0~23[1:0], RXDV0~23, RXD0~23[1:0]. Feature setting chosen configuration pin. RMII specification following characteristics: supports 10Mbps 100Mbps data rates provides independent 2-bit wide (di-bit) transmit receive data paths Table 8.2.1 RMII Specification Signals Direction with respect Usage REFCLK Input Output Synchronous clock reference receive, transmit control interface RXDV Output Input Carrier Sense RXD[1:0] Output Input Receive Data Input Output Transmit Enable TXD[1:0] Input Output Transmit Data detail description (please assignment). Signal Name Direction with respect Input
Buffer Management
buffer memory embedded ADM6326 24+2G switch operations, which designed based output queuing dynamic shared memory management architecture.
Media Access Control
ADM6326 implements functions IEEE 802.3 protocol such frame formatting, collision handling, etc. ADM6326 generates 56-bit preamble Start Frame delimiter while packet being sent. half-duplex mode, listening before transmitting allows prevent traffic jam. Whenever collision occurs, packet will delayed random time, then re-sent.
EEPROM Dynamic configured 8051
EEPROM configuration option switch setting. This setting also called through Recall triggered controller like 8051. EEPROM recall after power-on reset. configuration changed without reset. Toggling "recall" will read EEPROM again, while 8051 will emulate signal like EEPROM
ADMtek Incorporated 2001/10/23
Industrial Road, SBIP, Hsin-Chu Version 1.01
886-3-578-8879 :886-3-578-8871 ADMtek Incorporated Confidential
ADM6326 Specification Operation Modes
Page
Reduced interface PHYs transceivers operate 10/100Mbps full half-duplex mode. GMII interface PHYs transceivers operate 10/100/1000 full-duplex mode. keep consistent operation speed, these parts (PHY switching controller) will automatically adjusted mode through MDC/MDIO pins. ADM6326 also provides fixed speed operation mode configured EEPROM, dynamic configuration controller like 8051. modes support full wire speed operations without interference.
Automatic Address Learning, Forwarding, Filtering Function
8.7.1 Address Recognition ADM6326 provides embedded address table implement address recognition. Self-learning bridge function based source address packets field. Look-up table different hashing algorithms strengthen bridge ability with high performance assurance. Configurable aging time also supported. entry hashing table calculated 32-bit polynomial (called hashing function) direct mapping (called simple hashing function), well address (called input data). Direct mapping function allocated lowest bits SA/DA address buffer address entry. Hashing function selection offset EEPROM. Each (Destination Address) passes through hashing function gets entry point embedded SRAM. record empty, packet broadcast, treated unknown frame. Otherwise, record read, then address storage from current packet compared. addresses same, port number decided, packet forwarded assigned port. addresses different, incoming packet also treated unknown packet. broadcast packet will pass through other ports without address recognition. 8.7.2 Learning Process Address learning process composed packets hashing function described above. each incoming packet, ADM6326 will check whether packet errorless whether content entry address SRAM assigned. packet will compared source address, port number. both fields match packet information, aging status revised learnt address. addresses matches, port number different, port number reassigned. When entry collides, address ignored record keeps one. Last possibility, record free, address port number incoming packet stored. following diagram describes general operations address learning recognition.
Address Entry Point Direct Mapping Hashing Function AAA-1 AAA+1 Address Look-up Table Fig. 8.7.2 Address Learning Recognition 8.7.3 Forwarding Scheme ADM6326 forwarding scheme adopts store-and-forward method. Each determined outgoing packet buffer incoming port directly sent assigned port. forwarding scheme unknown packets treated same broadcast packet. ADM6326 also requires first- in-first-out service, prevent packets disorder.
IEEE 802.3 Congestion Control
half duplex operation, ADM6326 supports back pressure feature. When buffer full, packet 802.3x control frame sent connected segment, which called back pressure. ADM6326 implements Alternative back pressure based either three algorithms described EEPROM section. free blocks buffer memory match below threshold, packet directly transmitted regardless routing decision.
ADMtek Incorporated 2001/10/23
Industrial Road, SBIP, Hsin-Chu Version 1.01
886-3-578-8879 :886-3-578-8871 ADMtek Incorporated Confidential
ADM6326 Specification
Page
Full duplex flow control, ADM6326 follows IEEE 802.3x standard. delay time PAUSE frame zero maximum value. feature allows ADM6326 handle remote-side PAUSE frame. full duplex flow control, state machine threshold values described EEPROM, too. octets octets octets octets 2octets octets
Destination Address
Source Address
Type Opcode
Pause Time
IEEE 802.3x PAUSE Frame Format diagram shown above IEEE 802.3x Pause frame format. fields listed below. Destination Address: destination address Source Address: source address Type: PAUSE frame type 0x8808 Opcode value fixed, 0x0001 (PAUSE operation) Pause Time: Number slot-time PAD: zeroes ADM6326, PAUSE frame received, ADM6326 will stop ports transmission packets timer until timeout another PAUSE frame with zero time. buffer full full duplex mode, ADM6326 will send PAUSE frame with maximum delay time, defer receiving packet. When enough buffer released, PAUSE frame with zero delay sent.
Auto-negotiation Operations
When MDC/MDIO pins communicate with transceivers, ADM6326 10/100Mbps half/full duplex mode independently. Otherwise, ADM6326 adjust speed itself according auto-negotiation with PHYceiver.
8.10 Priority Frame (CoS) Operations
ADM6326 packets high priority follows: Port Number (set pin), VLAN tag, TCP/IP TOS/DS (both EEPROM 8051-like controller) scheme weighted round robin. priority setting port means that packets received port will priority frames; ADM6326 also judge priority frames checking specific bits VLAN TCP/IP TOS/DS included frame format. ADM6326 will check specific bits recorded type field packet format ensure VLAN TCP/IP TOS/DS status packets, then threshold VLAN TCP/IP TOS/DS declare priority packets. addition, scheme weighted round robin used judging high priority frames, which utilizes notion weighted ratio priority frame normal frame decide frame priority level.
8.11 VLAN Broadcast Storming Prevention
ADM6326 supports VLAN function ease administration logical groups stations that communicate they were same LAN, move, change numbers these groups. ADM6326 also supports port-groups scheme effectively prevent broadcast storming from interfering with whole transmission efficiency between ports. ports divided into groups while broadcast storming starting, then broadcast frames transmitted destination port belonging other groups will prohibited. During this time, ports belonging different groups independent. Only destination port broadcast frames same group will allowed. Furthermore, scheme port-group dividing very flexible. overlapped port-groups allowed during some operations, example, port shared groups, other operations between these groups remain independent except overlapped port. Only overlapped port could same different VLAN port-groups.
ADMtek Incorporated 2001/10/23
Industrial Road, SBIP, Hsin-Chu Version 1.01
886-3-578-8879 :886-3-578-8871 ADMtek Incorporated Confidential
ADM6326 Specification 8.12 Inter-Frame
Page
idle time between continuous packets from same port. default value 10Mbps 9.6usec 0.96usec 100Mbps. mode only from TXE.
8.13 MDC, MDIO Interface
ADM6326
MDIO
MDIO
Fig. 8.13 specific application Serial Management Interface There pins Serial Management Interface ADM6326. (Management Data Clock) input pin. functions interface device. MDIO bi-directional interface device. following conditions true, ADM6326 will register register connected transceiver. First, IEEE 802.3x flow control enabled. Then, port number Flow Control Write EEPROM offset enabled. Then, ADM6326 full duplex simultaneously with Transceiver. After write operation through MDIO, auto-negotiation restarted ADM6326 gain information remote 802.3x flow control. Finally, ultimate operation flow control set.
8.14 Interface
ADM6326 supports only assigned T20, which represents buffer full test fault. When ADM6326 reset, off. While testing mode, test embedded data buffer address table fails, will flash once, about sec, then stay Next, testing other embedded memory fails, will flash twice, about 1.6sec. After tests successful, status down, about 3.2sec. minimum. back -pressure full duplex flow control set, buffer full will flash every 200ms, then stay 3.2sec based packet PAUSE frame sent. arrival packet dropped, will flash every 50ms, then stay 3.2sec.
ADMtek Incorporated 2001/10/23
Industrial Road, SBIP, Hsin-Chu Version 1.01
886-3-578-8879 :886-3-578-8871 ADMtek Incorporated Confidential
ADM6326 Specification
Page
Absolute Maximum Ratings
Supply Voltage(Vcc) Input Voltage Output Voltage Storage Temperature Ambient Temperature Protection -0.5V 1.9V -0.5 3.3V -0.5 3.3V °C(-85°F 302°F) 70°C(32°F 158°F) 2000V
Specifications
Parameter
Cinp Lpinp
Description
Condition
-0.5
Typical
Units
Supply Voltage Power Supply 1.8V Input Voltage Input HIGH Voltage Input Leakage Current 0.8V Input HIGH Leakage Current 2.0V Output Voltage Iout =2~8mA Output HIGH Voltage Iout =-2~-8mA Input Capacitance Inductance
Table Specification
Specifications
11.1 EEPROM Timing
EECK
EECS EEDI
EEDO
11.1 EEPROM Timing
Parameter
Description
EECK (50% duty cycle) EECS/EEDI delay from falling EECK
Condition
Clock 50MHz Clock 50MHz
Units
idle time EECS EEDO valid before rising EECK EEDO hold after rising EECK
Clock 50MHz
4000
Table 11.1 EEPROM Timing ADMtek Incorporated 2001/10/23 Industrial Road, SBIP, Hsin-Chu Version 1.01 886-3-578-8879 :886-3-578-8871 ADMtek Incorporated Confidential
ADM6326 Specification 11.2 RMII Transmit Receive Timing
Page
REF_CLK TX_EN
TXD(1)
TXD(0)
Preamble
Data
REF_CLK CRS_DV
RXD(1)
RXD(0)
Preamble
Data
11.2 RMII Transmit Receive Timing
Symbol
Thold
Parameter
REF_CLK Frequency REF_CLK Duty Cycle TXD[1:0], TX_EN, RXD[1:0], CRS_DV, Data setup REF_CLK rising edge TXD[1:0]. TX_EN, RXD[1:0], CRS_DV, Data hold from REF_CLK rising edge
Type
Units
Table 11.2 RMII Transmit Receive Timing
ADMtek Incorporated 2001/10/23
Industrial Road, SBIP, Hsin-Chu Version 1.01
886-3-578-8879 :886-3-578-8871 ADMtek Incorporated Confidential
ADM6326 Specification
Page
Package size
ADMtek Incorporated 2001/10/23
Industrial Road, SBIP, Hsin-Chu Version 1.01
886-3-578-8879 :886-3-578-8871 ADMtek Incorporated Confidential

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