LC876764A Single Chip Microcontroller incorporating 64KB 1536 byt

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LC876764A Single Chip Microcontroller incorporating 64KB 1536 byt

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8-Bit Single Chip Microcontroller LC876764A/48A
LC876764A
Single Chip Microcontroller incorporating 64KB 1536 byte chip
LC876748A
Single Chip Microcontroller incorporating 48KB 1536 byte chip
Overview
LC876764A/LC876748A single chip microcomputers with following on-chip functional blocks: CPU: operable minimum cycle time 100ns On-chip Maximum Capacity LC876764A bytes LC876748A bytes On-chip RAM: 1536 bytes automatic display controller driver timer counter (can divided into timers) timer (can divided into timers) four timer with prescaler timer date time clock High speed clock counter System clock divider function synchronous serial port (with automatic block transmit receive function) asynchronous synchronous serial port 14-channel 8-bit converter Weak signal detector 21-source 10-vectored interrupt system above functions fabricated single chip.
Ver:1.01 80901
SYSTEM-BIZ Div. Kubota
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LC876764A/48A
Features
Read-Only Memory (ROM): LC876764A 65536 bits LC876748A 49152 bits Random Access Memory (RAM): LC876764A/48A Minimum Cycle Time: 100ns (10MHz) Note: cycle time indicates read time. Minimum Instruction Cycle Time: 300ns (10MHz) Ports Input/output ports Data direction programmable each individually withstand input/output ports Data direction programmable nibble units (When N-channel open drain output selected, data Data direction programmable each individually Input ports output ports Large current outputs digits Large current outputs digits segments digit segment outputs segment outputs Other functions Input/output ports Input ports Oscillator pins Reset Power supply 1536 bits
(P1n, P73, P8n) (P0n) input units.) (P3n) (XT1,XT2)
T15) (S16 S23) (S24 S51) 12(PFn, (PCn, PDn, PEn) (CF1,CF2) (RES#) (VSS1 VDD1
automatic display controller Programmable segment/digit output pattern Output switched between digit/segment waveform output (pins used output digit waveforms). parallel-drive available large current VFD. 16-step dimmer function available Weak signal detection (MIC signals etc) Counts pulses with width greater than preset value counter Timers Timer timer counter with capture register Mode channel 8-bit timer with programmable prescaler capture register Mode timer with programmable prescaler capture register Counter with 8-bit capture register Mode timer with programmable prescaler capture register Mode counter with capture register
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LC876764A/48A Timer timer toggle output Mode channel timer (with toggle output) Mode channel Mode timer (with toggle output) Toggle output also possible using lower order bits. Mode timer (with toggle output) Lower order bits used output. Timer timer with prescaler Timer timer with prescaler Timer timer with prescaler Timer timer with prescaler Base Timer clock signal selected from following. Sub-clock (32.768kHz crystal oscillator), system clock, prescaler output from timer Interrupts selected occur five different times. High speed clock counter Capable counting maximum: 20MHz clock (Using main clock 10MHz) Real time output (10) Serial-interface synchronous serial Interface first first function available Internal baud-rate generator (maximum transmit clock period Tcyc) Continuous automatic data communication (1-256 bits) asynchronous synchronous serial interface Mode Synchronous serial (2-wire 3-wire, transmit clock 2-512 Tcyc) Mode Asynchronous serial (half duplex, data bits, stop bit, baud rate 8-2048Tcyc) Mode mode (start bit, data bits, transmit clock 2-512 Tcyc) Mode mode (start detection, data bits, stop detection) (11) converter bits channels (12) Remote control receiver circuit (connected INT3 T0IN terminal) -Noise rejection function (noise rejection filter time constant selected from Tcyc) (13) Watchdog timer watching timer period using external Watchdog timer produce interrupt, system reset
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LC876764A/48A (14) Interrupts: 21-source, 10-vectored interrupts Three priority (low, high highest) multiple interrupts supported. During interrupt handling, equal lower priority interrupt request refused. interrupt requests more vector addresses occur once, higher priority interrupt takes precedence. case equal priority levels, vector with lowest address takes precedence. Vector Selectable Level 00003H 0000BH 00013H 0001BH 00023H 0002BH 00033H 0003BH 00043H 0004BH Priority Level: X>H>L equal priority levels, vector with lowest (15) Subroutine stack levels: levels max. (16) Multiplication division (executed cycles) cycles) cycles) cycles) (17) Oscillation circuits On-chip oscillation circuit system clock use. On-chip oscillation circuit system clock use. built On-chip Crystal oscillation circuit speed system clock use. (Rd, external) On-chip frequency -variable oscillation circuit system clock (18) System clock divider function Able reduce current consumption Available minimum instruction cycle time: 300ns, 600ns, 1.2µs, 2.4µs, 4.8µs, 9.6µs, 19.2µs, 38.4µs, 76.8µs. (Using 10MHz main clock) (19) Standby function HALT mode HALT mode used reduce power consumption. Program execution stopped. Peripheral circuits still operate display some serial transfer operations stop. Oscillation circuits stopped automatically. Release occurs system reset interrupt. Interrupt signal INT0 INT1 INT2/ T0L/ INT4 INT3/ Base timer/ INT5 T1L/ SI00 SI01 ADC/ MIC/ automatic display controller/ Port0/ address takes precedence.
Stack located RAM.
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LC876764A/48A -HOLD mode HOLD mode used reduce power consumption. Both program execution peripheral circuits stopped. 1)CF, RCand crystal oscillation circuits stop automatically. Release occurs following conditions. input reset goes specified level input least INT0, INT1, INT2, INT4, INT5 interrupt condition arises port -X'tal HOLD made X'tal HOLD mode used reduce power consumption. Program execution stopped. peripheral circuits except base timer stopped. oscillation circuits stop automatically. Crystal oscillator maintained state HOLD mode inception. Release occurs following conditions input reset goes specified level input least INT0, INT1, INT2, INT4, INT5 interrupt condition arises port interrupt condition arises base-timer (20) Factory shipment -delivery form QIP100E (21) Development tools Evaluation chip: LC876093 Emulator: EVA62S ECB876600 (Evaluation chip board) SUB876700 POD100QFP ICE-B877300 SUB876700 POD100QFP Flash version: LC87F67C8A
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Assignment
S48/PG0 S49/PG1 S50/PG2 S51/PG3 VSS2 VDD2 P10/SO0 P11/SI0/SB P12/SCK0 P13/SO1 P14/SI1/SB
LC876764A/48A
P16/T1PWML P17/T1PWMH/BUZ P30/INT4/T1IN P31/INT4/T1IN P32/INT4/T1IN P33/INT4/T1IN P34/INT5/T1IN P35/INT5/T1IN P36/INT5/T1IN P37/INT5/T1IN XT1/AN10 XT2/AN11 VSS1 VDD1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7/MICIN P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN/NKIN/AN12 P73/INT3/T0IN/AN13 S0/T0
S47/PF7 S46/PF6 S45/PF5 S44/PF4 S43/PF3 S42/PF2 S41/PF1 S40/PF0 VDD4 S39/PE7 S38/PE6 S37/PE5 S36/PE4 S35/PE3 S34/PE2 S33/PE1 S32/PE0 S31/PD7 S30/PD6 S29/PD5 S28/PD4 S27/PD3 S26/PD2 S25/PD1 S24/PD0 S23/PC7 S22/PC6 S21/PC5 S20/PC4 FIX0
S19/PC3 S18/PC2 S17/PC1 S16/PC0 VDD3 S15/T15 S14/T14 S13/T13 S12/T12 S11/T11 S10/T10 S9/T9 S8/T8 S7/T7 S6/T6 S5/T5 S4/T4 S3/T3 S2/T2 S1/T1
SANYO: QIP100E
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System Block Diagram
Interrupt Control
Stand-by Control
Flash
X'tal Clock Generator
Interface
SIO0
Port
Register
SIO1
Port
Register
Timer
(High speed clock counter)
Port
Timer
Port
Base Timer
Port
Controller
Noise Rejection
Weak Signal
Timer
Timer
Stack Pointer
Timer
Timer
Watch Timer
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Assignment
name VSS1 VSS2 VDD1 VDD2 VDD3 VDD4 FIX0 PORT0 Power supply Power supply Function Option
Test with user's option. (see Note 8bit input/output port data direction programmable nibble units pull-up resistor specified nibble units Input HOLD release Input port interrupt withstand N-channel open drain output 8bit input/output port data direction programmable each pull-up resistor specified each Other functions SIO0 data output SIO0 data input/bus input/output SIO0 clock input/output SIO1 data output SIO1 data input/bus input/output SIO1 clock input/output P16: Timer PWML output P17: Timer PWMH output/Buzzer output
PORT1
PORT3
8bit Input/output port Data direction specified each pull-up resistor specified each withstand N-channel open drain output Other functions: P33: INT4 input/ HOLD release input/ Timer event input/ Timer capture input/ Timer capture input P37: INT4 input/ HOLD release input/ Timer event input/ Timer capture input/ Timer capture input following types interrupt detection possible: Rising INT4 INT5 Falling Rising/ Falling level level
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name PORT7 Function 4bit Input/output port Data direction specified each pull-up resistor specified each Other functions P70: INT0 input/HOLD release input/Timer0L capture Input/output watchdog timer P71: INT1 input/HOLD release input/Timer0H capture input P72: INT2 input/HOLD release input/timer event input/Timer0L capture input/High speed clock counter input P73: INT3 input(noise rejection filter attached input)/timer event input/Timer capture input input port: AN8(P70), AN9(P71), AN12(P72), AN13(P73) following types interrupt detection possible: Rising INT0 INT1 INT2 INT3 PORT8 Falling Rising/ Falling level level Option
S0/T0 S8/T8 S9/T9 S15/T15
8bit Input/output port Input/output specified unit Other functions: input port: Weak signal detector input port: MICIN(P87) Large current output display controller digit (can used segment) Large current output display controller segment/digit Output display controller segment/digit Other functions: High voltage input port: Output display controller segment Other functions: High voltage input port: Output display controller segment Other functions High voltage input port: Output display controller segment Other functions: High voltage input/output port: Output display controller segment Other functions: High voltage input/output port: Reset terminal Input 32.768kHz crystal oscillation Other functions: General purpose input port When use, connect VDD1. input port: AN10
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name Function Output 32.768kHz crystal oscillation Other functions: General purpose input port When use, oscillation mode leave open circuit. input port: AN11 Input terminal ceramic oscillator Output terminal ceramic oscillator Option
Note LC876700 series mounted onto circuit board intended 876500 LC876600 series. this case, minus voltage power supply supplied FIX0 pin. Using negative voltage does alter FIX0 pin's operation.
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Port Output Configuration
Output configuration pull-up/pull-down resistor options shown following table. Input /output possible even when port output mode.
Terminal Option applies Options units each each S0/T0 S15/T15 None None None High voltage Pch-open drain Input only Output 32.768kHz crystal oscillation None None None None None None CMOS voltage Nch-open drain CMOS Nch-open drain CMOS Nch-open drain Nch-open drain CMOS Nch-open drain Output Format Pull-up resistor Programmable (Note None Programmable Programmable Programmable None Programmable Programmable None Pull-down resistor
Note Programmable pull-up resisters Port attached nibble units (P00-03, P04-07). Note Connect follows reduce noise increase back-up time. VSS1, VSS2 must connected together grounded. *Note power supply internal memory VDD1 uses VDD2 power supply ports. When VDD2 backed port level does become even port latch level. Therefore, when VDD2 backed port latch level, port level unstable HOLD mode, back time becomes shorter because through current runs from input buffer. VDD2 backed output program pull port external circuit HOLD mode that port level becomes level unnecessary current consumption prevented.
VDD1 Back-up capacitors
Power Supply
VDD2 VDD3 VDD4 VSS1 Powers VSS2
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Absolute maximum ratings Ta=25°C VSS1=VSS2=0V
Limits Parameter Supply voltage Input voltage Output voltage Input/Output voltage Symbol Pins Conditions VDD1=VDD2= VDD3=VDD4
min. -0.3 -0.3 VDD-45 VDD-45 -0.3
typ.
max. +7.0 VDD+0.3 VDD+0.3 VDD+0.3 VDD+0.3
unit
VDDMAX VDD1,VDD2, VDD3,VDD4 VI(1) VI(2) VO(1) VIO(1) XT1,XT2,CF1, S0/T0 S15/T15 CMOS output option CMOS output option open drain open drain Port
VIO(2) VIO(3) High Peak IOPH(1) level output output current current IOPH(2) IOPH(3) IOPH(4)
-0.3 VDD-45 output selected each Current each Current each Current each Total pins Total pins Total pins Total pins Total pins Total pins Total pins each each each each each to+70°C
VDD+0.3
Port71,72,73 S0/T0 S15/T15
IOAH(1) Port Total output IOAH(2) Port current IOAH(3) Port IOAH(4) S0/T0 S15/T15 IOAH(5) IOAH(6) IOAH(7) Port level output Total IOAL(1) Port 00,01,02,03 current output IOAL(2) 04,05,06,07 current IOAL(3) Ports Maximum power dissipation Operating temperature range Storage temperature range Pdmax QIP100E Peak IOPL(1) output IOPL(2) current Port 0,1,3
Topr
Tstg
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Recommended operating range Ta=-30°C +70°C, VSS1=VSS2=0V
Parameter Symbol Pins VDD1=VDD2=VDD3 =VDD4 VDD1 Conditions 0.294µs Tcyc 200µs register data kept HOLD mode. Output disable Limits min. typ. max. unit
Operating VDD(1) supply voltage range Hold voltage
Input high voltage
VIH(1)
0,3: CMOS output option Port 0,3: N-ch open drain output port input/ interrupt Weak signal input Port Watchdog timer XT1, XT2, CF1, 0,3: CMOS output option Port 0,3: N-ch open drain output 71,72,73 port input /interrupt Port weak signal input Port Watchdog timer XT1,XT2,CF1,
4.5-6.0 0.3VDD +0.7 4.5-6.0 0.3VDD +0.7 4.5-6.0 0.3VDD +0.7
VIH(2) VIH(3)
Output disable Output disable
13.5
VIH(4) VIH(5) VIH(6) VIH(7) Input voltage VIL(1)
Output P-channel Output disable Output disable
4.5-6.0 0.3VDD +1.0 4.5-6.0 0.75VDD 4.5-6.0 0.9VDD 4.5-6.0 0.75VDD
0.15VDD +0.4 0.15VDD +0.4 0.1VDD +0.4
Output disable
4.5-6.0
VIL(2) VIL(3)
Output disable Output disable
4.5-6.0 4.5-6.0
VIL(4) VIL(5) VIL(6) VIL(7) Operation cycle time External system clock frequency
Output P-channel Output disabled Output disabled
4.5-6.0 4.5-6.0 4.5-6.0 4.5-6.0 4.5-6.0
0.294
0.2VDD 0.25VDD 0.8VDD -1.0 0.25VDD
fEXCF(1)
open circuit 4.5-6.0 clock divider clock DUTY 50±50% open circuit 4.5-6.0 clock divider
Continued
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Parameter Oscillation stabilizing time period (Note
Symbol FmCF(1) FmCF(2)
Pins CF1, CF1,
Conditions 10MHz ceramic resonator oscillation
Refer figure
VDD[V] 4.5-6.0 4.5-6.0
Limits min. typ.
max.
unit
4MHz ceramic resonator oscillation
Refer figure
FmRC FmMRC FsX'tal XT1,
oscillation Frequency variable oscillation 32.768kHz crystal resonator oscillation
Refer figure
4.5-6.0 4.5-6.0 4.5-6.0
32.768
(Note oscillation constant shown table table
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Electrical characteristics Ta=-30°C +70°C, VSS1=VSS2=0V
Parameter Input high current Symbol IIH(1) Pins Ports 0,3: N-ch open drain output Conditions disabled (including state leak current output Tr.) disabled resister OFF. (including state leak current output Tr.) When configured input port VIN=VDD VIN=VDD When configured input port VIN=VDD VIN=VDD VIN=VBIS+0.5V (VBIS Bias voltage) disabled (including state leak current output Tr.) VIN=VSS When configured input port VIN=VSS VIN=VSS VIN=VBIS-0.5V (VBIS Bias voltage) IOH=-1.0mA IOH=-0.1mA IOH=-0.4mA IOH=-20.0mA IOH=-1.0mA single over 1mA. IOH=-5.0mA IOH=-1.0mA single over 1mA. Port 0,1,3 Port Port 0,1,3,7 IOL=10mA IOL=1.6mA IOL=1mA VOH=0.9VDD Limits VDD[V] 4.5-6.0 min. typ. max. unit
IIH(2)
Port 0,1,3,7,8
4.5-6.0
IIH(3)
(Port C,D,E,F,G) XT1,XT2
4.5-6.0
IIH(4) IIH(5)
4.5-6.0 4.5-6.0
IIH(6) IIH(7) Input current IIL(1)
P87/AN7/MICIN weak signal input Port 0,1,3,7,8
4.5-6.0 4.5-6.0 4.5-6.0
IIL(2) IIL(3)
XT1,XT2
4.5-6.0 4.5-6.0
IIL(4) IIL(5) Output high VOH(1) voltage VOH(2) VOH(3) VOH(4) VOH(5)
P87/AN7/MICIN weak signal input Port 0,1,3: CMOS output option Port S0/T0-S15/T15
4.5-6.0 4.5-6.0 4.5-6.0 4.5-6.0 4.5-6.0
VDD-1 VDD-1 VDD-1 -8.5 -4.2
4.5-6.0 VDD-0.5 4.5-6.0 VDD-1.8
VOH(6) VOH(7)
4.5-6.0 VDD-1.8 4.5-6.0 VDD-1
Output voltage Pull-up resistor
VOL(1) VOL(2) VOL(3)
4.5-6.0 4.5-6.0 4.5-6.0 4.5-6.0
Continued
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Parameter Output offleak current
Symbol IOFF(1) IOFF(2)
Pins S0/T0 S15/T15,
Conditions P-ch P-ch P-ch
VDD[V] 4.5-6.0 4.5-6.0 4.5-6.0
Limits min.
typ.
Max. unit
Resistance Rinpd level hold Hysteresis VHIS(1) voltage VHIS(2) capacitance
Port weak signal input pins
4.5-6.0 4.5-6.0 other terminals connected VSS. =25°C 4.5-6.0
0.1VDD 0.1VDD
Input sensitivity
Vsen
Port weak signal input
4.5-6.0
0.12VDD
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Serial input/output characteristics Ta=-30°C +70°C, VSS1=VSS2=0V
Parameter Cycle Time Level pulse width High Level pulse width Cycle Time Symbol tSCK(1) tSCKL(1) tSCKLA(1) tSCKH(1) tSCKHA(1) tSCK(2) tSCKL(2) tSCKH(2) tSCK(3) tSCKL(3) tSCKLA(2) tSCKH(3) tSCKHA(2) tSCK(4) tSCKL(4) tSCKH(4) tdDO SI0(P11), SI1(P14), SB0(P11), SB1(P14) SO0(P10), SO1(P13), SB0(011), SB1(P14) with respect SI0CLK leading edge. figure with respect SI0CLK trailing edge. port open drain: Time delay from SI0CLK trailing edge data change. figure 4.5-6.0 0.03 0.03 4.5-6.0 tCYC +0.05 SCK1(P15) output option figure 4.5-6.0 SCK0(P12) output option figure 4.5-6.0 SCK1(P15) Refer figure 4.5-6.0 Pins Conditions VDD[V] 4.5-6.0 min. tCYC tSCK tSCK Limits typ. max. unit
SCK0(P12) Refer figure
Serial clock Serial input
Output clock
Input clock
Level pulse width High Level pulse width Cycle Time Level pulse width High Level pulse width Cycle Time Level pulse width High Level pulse width Data set-up time Data hold time Output time delay
Serial output
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Pulse input conditions Ta=-30°C +70°C, VSS1=VSS2=0V
Parameter High/low level pulse width Symbol Pins Conditions VDD[V] tPIH(1) INT0(P70), tPIL(1) INT1(P71), INT2(P72) INT4(P30 P33) INT5(P34 P37) tPIH(2) INT3(P73) tPIL(2) (Noise rejection ratio 1/1.) tPIH(3) INT3(P73) tPIL(3) (Noise rejection ratio 1/32.) tPIH(4) INT3(P73) tPIL(4) (Noise rejection ratio 1/128.) tPIH(5) MICIN(P87) tPIL(5) tPIH(6) NKIN(P72) tPIL(6) tPIL(7) acceptable 4.5-6.0 timer input. Limits min. typ. max. unit
acceptable 4.5-6.0 timer input. acceptable 4.5-6.0 timer input. acceptable 4.5-6.0 timer input. signal detection counter enabled speed clock counter countable possible 4.5-6.0
4.5-6.0 4.5-6.0
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converter characteristics Ta=-30°C 70°C, VSS1=VSS2=0V
Parameter Resolution Absolute precision Conversion time Symbol TCAD Pins AN0(P80) AN7(P87), AN8(P70), AN9(P71), AN10(XT1), AN11(XT2), AN12(P72), AN13(P73) Conditions Limits VDD[V] 4.5-6.0 (Note2) conversion time tCYC (ADCR2=0) (Note conversion time tCYC (ADCR2=1) (Note 4.5-6.0 VAIN=VDD VAIN=VSS 4.5-6.0 4.5-6.0 4.5-6.0 4.5-6.0 15.62 (tCYC= 0.488µs) 18.82 (tCYC= 0.294µs) min. typ. ±1.5 97.92 (tCYC= 3.06µs) 97.92 (tCYC= 1.53µs) max. unit
Analog input voltage range
VAIN
Analog port input IAINH current IAINL
(Note Absolute precision including quantizing error (±1/2 LSB). (Note Conversion time means time from executing conversion instruction loading complete digital value register.
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Current dissipation characteristics Ta=-30°C +70°C, VSS1=VSS2=0V
Parameter Current dissipation during basic operation (Note Symbol IDDOP(1) Pins Conditions Limits VDD[V 4.5-6.0 min. typ. unit
IDDOP(2)
IDDOP(3)
IDDOP(4)
IDDOP(5)
IDDOP(6)
VDD1 Ceramic resonator VDD2 oscillation VDD3 crystal oscillation clock: VDD4 oscillation oscillation stopped. variable oscillation stopped. external clock crystal oscillation clock: oscillation oscillation stopped. variable oscillation stopped. Ceramic resonator oscillation crystal oscillation clock: oscillation oscillation stopped. variable oscillation stopped. oscillation) crystal oscillation variable oscillation stopped. clock: oscillation oscillation) crystal oscillation oscillation stopped. clock: 1MHz with frequency variable oscillation oscillation) crystal oscillation clock: 32.768KHz variable oscillation stopped.
4.5-6.0
4.5-6.0
4.5-6.0
4.5-6.0
Continued
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LC876764A/48A
Parameter Current dissipation HALT mode (Note
Symbol
Pins
Conditions HALT mode Ceramic resonator oscillation crystal oscillation clock oscillation oscillation stopped. variable oscillation stopped. HALT mode external clock crystal oscillation clock oscillation oscillation stopped. variable oscillation stopped. HALT mode Ceramic resonator oscillation crystal oscillation clock 4MHz oscillation stopped. variable oscillation stopped. HALT mode (When oscillation stops.) crystal oscillation clock oscillation HALT mode (When oscillation stops.) crystal oscillation oscillation stopped. clock: 1MHz with frequency variable oscillation
IDDHALT(1) VDD1= VDD2= VDD3= VDD4
VDD[V] min.
Limits typ. max.
unit
IDDHALT(2)
IDDHALT(3)
IDDHALT(4)
1600
IDDHALT(5)
1500
3600
Continued
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LC876764A/48A
Parameter Current dissipation HALT mode (Note
Symbol
Pins
Conditions HALT mode (When oscillation stops.) crystal oscillation clock 32.768kHz oscillation stopped. variable oscillation stopped.
IDDHALT(6) VDD1= VDD2= VDD3= VDD4
VDD[V] min.
Limits typ. max.
unit
Current IDDHOLD(1) dissipation HOLD mode Current IDDHOLD(2) dissipation Date/time clock HOLD mode
VDD1
VDD1
HOLD mode open circuit (when using external clock) Date/time clock HOLD mode open circuit (when using external clock) crystal oscillation
0.05
(Note currents output transistors pull-up transistors ignored.
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LC876764A/48A Main system clock oscillation circuit characteristics characteristics table bellow based following conditions: standard evaluation board SANYO provided. peripheral parts with indicated value externally. peripheral parts value recommended value oscillator manufacturer Table Main system clock oscillation circuit characteristics using ceramic resonator
Frequenc Manufacture Oscillator Circuit parameters Operating Oscillation supply stabilizing time voltage range Notes
10MHz
4MHz
oscillation stabilizing time period until oscillation becomes stable after becomes higher than minimum operating voltage. (Refer Figure4) Subsystem clock oscillation circuit characteristics characteristics table bellow based following conditions: standard evaluation board SANYO provided. peripheral parts with indicated value externally. peripheral parts value recommended value oscillator manufacturer Table Subsystem clock oscillation circuit characteristics using crystal oscillator
Frequency Manufacturer Oscillator 32.768kHz Circuit parameters Operating supply voltage range Oscillation stabilizing time Notes
oscillation stabilizing time period until oscillation becomes stable after executing instruction which starts sub-clock oscillation after releasing HOLD mode. (Refer Figure4) (Notes) Since circuit pattern affects oscillation frequency, place oscillation-related parts close oscillation pins possible with shortest possible pattern length.
X'tal
Figure
Ceramic oscillation circuit
Figure
Crystal oscillation circuit
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LC876764A/48A
0.5VDD
Figure
timing measurement point
Power Reset time limit
Internal Resonator tmsCF CF1,CF2 tmsXtal XT1,XT2
Operation mode
Unfixed
Reset
Instruction execution mode
Reset time oscillation stable time
HOLD release
Without HOLD Release
HOLD release signal VALID
Internal Resonator tmsCF CF1,CF2 tmsXtal XT1,XT2
Operation mode
HOLD
HALT
HOLD release signal oscillation stable time
Figure
Oscillation stablization time
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LC876764A/48A
(Note) values such that reset time exceeds 200µs.
Figure
Reset circuit
SIOCLK
DATAIN
DATAOUT
Data transmission period (only SIO0)
tSCK tSCKL SIOCLK tsDI DATAIN tdDO DATAOUT thDI tSCKH
Data transmission period (only SIO0) tSCKLA SIOCLK tsDI DATAIN tdDO DATAOUT thDI tSCKHA
Figure
Serial input output test condition
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LC876764A/48A
tPIL
tPIH
Figure
Pulse input timing condition
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This catalog provides information August 2001. Specifications information herein subject change without notice
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LC876764A Single Chip Microcontroller incorporating 64KB 1536 byt

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