KASEI [AK2305] AK2305 Dual CODEC ISDN TERMINAL ADAPTER

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KASEI [AK2305] AK2305 Dual CODEC ISDN TERMINAL ADAPTER

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ASAHI
KASEI
[AK2305]
AK2305
Dual CODEC ISDN TERMINAL ADAPTER
GENERAL DESCRIPTION
AK2305 dual CODEC-Filter most suitable ISDN Terminal Adapter. A-law/ulaw selected internal register. addition CODEC, this device dual DTMF receiver External Tone Input pin. Input/output operational amplifiers included this device used transmit/receive gain adjustment. AK2305 internal volume control attenuate signal from -12dB step control which defined internal register written through serial interface. interface AK2305 accepts several clock formats, which Long Frame, Short Frame, GCI, IDL. 64k-4096kHz clock input available interface.
FEATURE
Dual CODEC Filtering systems ISDN Terminal Adapter Dual DTMF Receiver External Tone Input(AUX) Independent functions each channel Frame Sync Signal(8kHz) Power Down Mode(Pin/Register operation) Mute(Pin/Register operation) Gain Adjustment: -12dB (3dB step) Selectable Data Interface Timing: Long Frame Short Frame Variable Data Rate: [Hz] (64k 4.096 Operational Amplifier Gain Adjustment A-law/u-law Register Selectable Serial Interface Power Reset Single CMOS technology Power Consumption (85mW typ)
PACKAGE
48LQFP (0.5mm pitch)
C0029-E-02
1999/8
ASAHI
KASEI
[AK2305]
CONTENTS
ITEMS
PAGE
BLOCK DIAGRAM. ASSIGNMENT. CONDITION. FUNCTION. CIRCUIT DESCRIPTION. FUNCTIONAL DESCRIPTION. INTERFACE. LONGFRAME/SHORTFRAME. GCI. IDL. RESET. POWER DOWN. MUTE. GAIN ADJUSTMENT. DTMF RECEIVER. TONE GENERATOR. INPUT. SERIAL INTERFACE. REGISTER. ABSOLUTE MAXIMUM RATINGS. RECOMMENDED OPERATING CONDITIONS. ELECTRICAL CHARACTERISTICS. APPLICATION CIRCUIT EXAMPLE.39 PACKAGE INFORMATION.
C0029-E-02
1999/8
ASAHI
KASEI
[AK2305]
BLOCK DIAGRAM
GSX0 VFX0
AMPT0
VR0T
AAF0
CODEC
VRX0 VFR0 GSR0
VR0R
AMPR0
SMF0
BCLK
GSX1 VFX1
AMPT1
VR1T
AAF1
SMF1
CODEC
VRX1 VFR1 GSR1 TNOUT VREF
VR1R
AMPR1
TONEGEN0
TNOE0 TNOE1 MUTE0 MUTE1 DTO00-03 DTO10-13
VRTN
TONEGEN1
BGREF
37-40
DTIN0
DTMF Receiver0 DTMF Receiver1
STD0 41-44
DTIN1 AVDD AVSS DVDD DVSS
STD1 DTOE
Internal Register
Serial
SCLK DATA
TST1 TST2
C0029-E-02
1999/8
ASAHI
KASEI
[AK2305]
ASSIGNMENT
BCLK DVSS DVDD DATA SCLK
DTO00 DTO01 DTO02 DTO03 DTO10 DTO11 DTO12 DTO13 TST1 DTIN0 GSX0 VFX0 STD0 STD1 TNOE0 TNOE1 DTOE MUTE0 MUTE1 TST2 DTIN1 GSX1 VFX1
VRX1 VFR1 GSR1 TNOUT AVSS AVDD VREF GSR0 VFR0 VRX0
C0029-E-02
1999/8
ASAHI
KASEI
[AK2305]
CONDITION
Pin# Name type load (MAX.) load (MIN.)
Outout status (Power down mode) Output status (Reset)
Remarks
VRX0 50pF Analog Hi-Z Hi-Z VFR0 Analog GSR0 50pF Analog Hi-Z Hi-Z (*1) VREF Analog external Analog external AVDD AVSS Analog TNOUT 50pF Analog Hi-Z Hi-Z GSR1 50pF Analog Hi-Z Hi-Z (*1) VFR1 Analog VRX1 50pF Analog Hi-Z Hi-Z VFX1 Analog GSX1 50pF Analog Hi-Z Hi-Z (*1) DTIN1 Analog TST2 Factory only MUTE1 MUTE0 DTOE TNOE1 TNOE0 STD1 15pF CMOS STD0 15pF CMOS (*2) BCLK 15pF CMOS Hi-Z Hi-Z 15pF CMOS Hi-Z Hi-Z DVSS DVDD (*3) DATA 15pF TTL/CMOS Input Input SCLK DTO00 15pF CMOS Hi-Z Hi-Z DTO01 15pF CMOS Hi-Z Hi-Z DTO02 15pF CMOS Hi-Z Hi-Z DTO03 15pF CMOS Hi-Z Hi-Z DTO10 15pF CMOS Hi-Z Hi-Z DTO11 15pF CMOS Hi-Z Hi-Z DTO12 15pF CMOS Hi-Z Hi-Z DTO13 15pF CMOS Hi-Z Hi-Z TST1 Factory only DTIN0 Analog GSX0 50pF Analog Hi-Z Hi-Z (*1) VFX0 Analog load(MIN.) includes feedback resistance input/output op-amp. Pulled down GCI/IDL mode. Pulled down Multiplex mode.
C0029-E-02
1999/8
ASAHI
KASEI
[AK2305]
FUNCTION
Pin# Name VFX0 GSX0 VRX0 VFX0 GSR0 GSR1 VFR1 VRX1 GSX1 VFX1 Function Transmit analog input. Inverting input transmit gain adjustment amplifier channel Output transmit gain adjustment amplifier channel Receive analog output channel This output drive 50pF. Transmit analog input. Inverting input transmit gain adjustment amplifier channel Output receive gain adjustment amplifier channel Output receive gain adjustment amplifier channel Inverting input receive gain adjustment amplifier channel Receive analog output channel This output drive 50pF. Output transmit gain adjustment amplifier channel Transmit analog input. Inverting input transmit gain adjustment amplifier channel Serial output data ch0. Long Frame Short Frame mode, output data ch0. mode, output data multiplexed with ch1. data rate synchronized with BCLK. "PCM INTERFACE" from page This output remains high impedance state except period transmitting data. Serial input data ch0. Long Frame Short Frame mode, input data ch0. mode, input data multiplexed with ch1. data rate synchronized with BCLK. "PCM INTERFACE" from page Serial output data ch1. Long Frame Short Frame mode, output data ch1. data rate synchronized with BCLK. "PCM INTERFACE" from page This output remains high impedance state except period transmitting data. multiplexd mode, this remains high impedance state. Serial input data ch1. Long Frame Short Frame mode, input data ch1. data rate synchronized with BCLK. "PCM INTERFACE" from page mode, this pulled down VSS. Frame sync input channel must 8KHz clock synchronized BCLK.
C0029-E-02
1999/8
ASAHI
Pin#
KASEI
Name
[AK2305]
Function Frame sync input channel must 8KHz clock synchronized BCLK. mode, this pulled down VSS. clock data interface. This clock apply both ch1. BCLK should synchoronized with kHz(FSn kHz). DTMF tone input Output DTMF receiver DTO00 LSB.
BCLK DTIN0 DTO00 DTO01 DTO02 DTO03 STD0 DTIN1 DTO10 DTO11 DTO12 DTO13 STD1 DTOE TNOE0 TNOE1 TNOUT DATA SCLK
Steering delay output ch0. After DTMF decoding, latch renewed this output alters high level. DTMF tone input. Output DTMF receiver DTO10 LSB.
output
MUTE0 MUTE1 VREF DVDD DVSS AVDD AVSS TST1 TST2
Steering delay output ch0. After DTMF decoding, output latch renewed this output alters high level. Output enable DTMF receiver. Output enable tone generator Output enable tone generator External tone input pin. Input signal should through more than 0.1uF external capacitance. Tone output pin. Data input serial interface. Clock input serial interface. Read write enable serial interface. Active high input mute. Active high input mute. Active high input power down. loop filter. Connect AVSS with 0.22uF larger. Analog ground output. stabilize analog ground, connect AVSS with 0.1uF larger. Digital positive supply voltage. System digital supply. Digital negative supply voltage. System digital ground. Analog positive supply voltage. Systems analog supply. Analog negative supply voltage. System analog ground. Only factory use. Should fixed DVSS.
C0029-E-02
1999/8
ASAHI
KASEI
[AK2305]
CIRCUIT DESCRIPTION
Block AMPT0,1 Function Op-amp input gain adjustment. This op-amp used inverting amplifier. Adjusting gain with external resistors. resistor larger than recommended feedback resistor. <NOTE> AMP0(1) becomes automatically power down, when both CODEC ch0(1) DTMFR0(1) power down. Op-amp output gain adjustment. This op-amp used inverting amplifier. Adjusting gain with external resistors. resistor larger than recommended feedback resistor. Integrated anti-aliasing filter which prevents signals around sampling rate from folding back into voice band. order low-pass filter. Converts analog signal 8bit data according companding schemes recommendation G.711; A-law u-law. band limiting filter also integrated. selection companding schemes ALAWN register follows: "H": u-Law "L": A-Law Expands 8bit data according A-law u-law. selection companding schemes ALAWN register follows: "H": u-Law "L": A-Law Extracts inband signal from output. also corrects sinx/x effect output. Provides stable analog ground voltage (2.4V) using on-chip band-gap reference circuit which temperature compensated. Generates kinds tone; 400Hz 1300Hz. Tone selection defined registers. ON/OFF tone output controlled TNOE0/1. Controls output signals from VRX0, VRX1, TNOUT pins. Each switch controlled register. Detects decodes DTMF tone. ON/OFF decoded output controlled DTOE. Gain selects analog signals. posibble select gain from -12dB (3dB/step* 5steps). Gain defined register. Interface internal register using SCLK, DATA, pins. 1word=14bit; Instruction code: 2bit, address: 3bit, data: 9bit(1dummy included). generates system clock AK2305. Reference clock (8KHz). More than 0.22uF external capacitance should connected between AVSS. data rate available 64xN(N 64)kHz which synchronizes with BCLK. Data format selected four types(Long Frame, Short Frame, GCI, IDL). data interfaced through DR0,1 DX0,1 multiplexed mode multiplexed mode.
AMPR0,1
BGREF TONE TONE SWITCH Sn(n=1-9) DTMF Receiver0,1 VR0T/R VR1T/R VRTN SERIAL
C0029-E-02
1999/8
ASAHI
KASEI
[AK2305]
FUNCTIONAL DESCRIPTION
INTERFACE
AK2305 supports following types format. those selected PCMIF0 PCMIF1 registers. Long Frame Sync(LF) Short Frame Sync(SF) data both channels multiplexed interfaced through common pins (DR0, DX0) Multiplex mode. Independent mode also available interface through independent pin(DR0/1,DX0/1) channel. Register interface mode selection PCMIF1 PCMIF0 Interface LF/SF (Non multiplex) LF/SF (2ch multiplex) (2ch multiplex) (2ch multiplex)
Frame sync FS0,FS1 FS0,FS1
Input DR0,DR1
Output DX0,
Remarks
Reset
FRAME SYNC SIGNAL(Frame Sync Frame sync signal should 8kHz clock. 8bits data accommodated frame (125us). Though only required (FS1 isn't required) mode IDL, both required mode FIRST used input clock PLL. generates timing this from this signal. assigned First mode IDL, mode assigned first register. 1stFS register First Remarks
Reset
Note Keep supplying first except state power down(PD="H"). first supplied, AK2305 loses timing; result, DTMFR TONE become guaranteed work normally. BCLK This clock decides data rate. following table relation between BCLK data rate. mode LF/SF/IDL BCLK Rate data
C0029-E-02
1999/8
ASAHI
KASEI
[AK2305]
Long Frame Sync(LF) Short Frame Sync(SF)
AK2305 automatically decides whether Long Frame Short Frame should selected, monitoring high level period First Period First ="H" more than clock BCLK clock BCLK INTERFACE TIMING <2ch Multiplex> data both channel interfaced DR0(DX1 used) format 8bits period frame(125us) which synchronizes with FSn(n=0,1). period 1frame, time slots assigned maximum case BCLK=4.096MHz). number time slots BCLK/64k. time slot assignment decided FS1. mode second FS(not first must delayed fast least (8/BCLK) (n=1 from first LongFrame
BCLK
Don't care
Frame type
Don't care
ShortFrame
BCLK
Don't care
Don't care
BCLK=4096kHz First
SLOT
output input
output input
output input
output input
C0029-E-02
1999/8
ASAHI
KASEI
[AK2305]
INTERFACE TIMING <Non Multiplex> data each channel interfaced each pins(DX0 DR0/DX1 DR1) format 8bits period frame(125us) which synchronizes with FSn(n=0,1). timing optionally they synchronize with BCLK. NOTE) First Second Only when BCLK=64kHz, possible input same clock first second Except 64kHz BCLK, clock BCLK (n=1-63 integral numbers) intervals slots needed. BCLK=4096kHz First
SLOT
output input output input
output input
output input
BCLK=64kHz(LF) same timing, First
FS0,FS1 BCLK
BCLK=64kHz(LF) First
BCLK
C0029-E-02
1999/8
ASAHI
KASEI
[AK2305]
GCI(General Circuit Interface)
Interface used ISDN. This data format below. data channel assignment defined SEL2B register. CH0,1selection SEL2B
Remarks Reset
Note: BCLK twice data rate. BCLK acceptable from 512kHz 4096kHz.
INTERFACE TIMING <2ch Multiplex> data each channel interfaced through DR0/DX0 8bits format. They accommodated frame(125us) which synchronizes with FS0.
BCLK
Don't care
Don't care
B1-CHANNEL(CH0) <SEL2B="0">
B2-CHANNEL(CH1) <SEL2B="0">
<Non Multiplex> supported.
C0029-E-02
1999/8
ASAHI
KASEI
[AK2305]
IDL(Interchip Digital Link)
Interface used ISDN. This data format below. data channel assignment channel defined SEL2B register. CH0,1selection SEL2B
Remarks Reset
Note: BCLK same data rate. BCLK acceptable from 256kHz 4096kHz.
INTERFACE TIMING <2ch Multiplex> data each channel interfaced through DR0/DX0 8bits format. They accommodated frame(125us) which synchronizes with FS0.
BCLK
Don't care
Don't care
Don't care
B1-CHANNEL(CH0) <SEL2B="0">
B2-CHANNEL(CH1) <SEL2B="0">
<Non Multiplex> supported.
C0029-E-02
1999/8
ASAHI RESET
KASEI
[AK2305]
POWER RESET AK2305 automatically generates internal reset pulse time power Then circuits reset internal registers initialized. After reset operation, CODEC CH0/CH1 circuits start initialized. takes 150ms(typ.), 330ms(max) from power completion initialization. *)Output pins remain Hi-Z during period which internal reset pulse high(See page period reset pulse about 20ms(typ), 200ms(max).
POWER-UP TIME POWER RESET When power-up time longer than 50ms(=5tau:tau time constant), Power Reset works normally. When time longer than 50ms, Power Reset available internal registers initialized. registers must written.
RECOMMENDED START PROCEDURE following start procedure recommended when AK2305 going power
Power
Wait 200ms case rising time =50ms(=5tau)
TNOE0,1=" FSn=" BCLK=" When 1stFS BCLK CODEC ch0,ch1 dose interface with external devices.
Write data internal register through serial
Write data internal register before CODEC starts working.
Supply BCLK CODEC Initialization starts. Wait 130ms CODEC Initialization complete. CODEC starts working
C0029-E-02
1999/8
ASAHI
KASEI
[AK2305]
POWER DOWN
Power consumption reduced power down mode. power down mode, supply current analog circuits clock digital circuits, stopped, relating circuits halted. There power down modes. Power down circuits Power down block power down mode, output pins corresponded blocks turn Hi-Z.(See page POWER DOWN MODE SETTING Mode Circuits Pin/Registers Operation "0"/"1" Normal Power down Note Registers reset. Serial available. need supply FSn(n=0,1),BCLK. Keep supplying first even when CODEC CH0,1 power down mode (see page8). Even when CODEC CHn(n=0,1) power down mode, functions below available: AMPTn(n=0,1) Input/Output TONEGEN0,1 Output From VRXn(n=0,1), TNOUT Even when these blocks power down mode; AMPT0/1, VR0/1R, AMPR0/1, VRTN, TONEGEN0/1, BGREF, Serial operate normally time.
circuits
CODEC CODEC Block DTMF Receiver0 DTMF Receiver1
PDCH0
PDCH1 Normal Power down PDDT0
Note) Initial value PDCHn, PDDTn(n=0,1) "0".
CANCELLATION POWER DOWN CODEC When power down mode CODEC CH0/CH1 cancelled, CODEC starts initialized. takes 130mS(typ.).
Registers
PDDT1
C0029-E-02
1999/8
ASAHI
KASEI
[AK2305]
POWER DOWN MODE SETTING POWER DOWN BLOCK POWER DOWN BLOCK REGISTER AMPT0 VR0T Channel AAF0 CODEC SMF0 VR0R AMPR0 AMPT1 VR1T Channel AAF1 CODEC SMF1 VR1R AMPR1 TONEGEN TONEGEN VRTN DTMFR DTMFR BGREF SERIAL BLOCK CODEC PDCH0 CODEC PDCH1 CODEC CH0&1 PDCH0 PDCH1 CODEC CH0, DTMFR0 PDCH0 PDDT0 CODEC CH1, DTMFR1 PDCH1 PDDT1
DTMFR0 PDDT0
DTMFR1 PDDT1
C0029-E-02
1999/8
ASAHI MUTE
KASEI
[AK2305]
CONTROL output each channel muted independently control. MUTEn (n=0,1) Operation Normal Mute (n=0,1) data output High-Impedance VRXn (n=0,1) CODEC analog output AGND*
*)TONE circuits avialable even mute operates.
Remarks
REGISTER CONTROL output each channel muted independently register control. MTDXn (n=0,1) Operation Normal Mute (n=0,1) data output High-Impedance VRXn (n=0,1) CODEC analog output* (MUTE0,1pin="0") Remarks Reset
MUTEn given priority over MTDXn. Therefore, instance, even when MTDXn "1," output VRXn AGND MUTEn="1." <Example> muted (MUTE0="1," MUTE1="0," MTDX0,1="0" mode)
BCLK
Don't care B1-CHANNEL(CH0) <SEL2B="0">
Don't care
B2-CHANNEL(CH1) <SEL2B="0">
VRX0 VRX1
CODEC analog output always AGND level. TONEGEN0,1output controlled TNOE0,1 pin. CODEC analog output signal converted from data input through pin. TONEGEN0,1 output controlled TNOE0,1 pin.
C0029-E-02
1999/8
ASAHI
KASEI
[AK2305]
GAIN ADJUSTMENT
Analog input/output gain adjusted range from0 -12dB (3dB/step*5steps) register. register VRnT2 VRnR2 VRTN2
VRnT1 VRnR1 VRTN1
VRnT0 VRnR0 VRTN0
Gain
Remarks Reset
This table applicable VR0T,VR0R,VR1T, VR1R ,and VRTN registers.
C0029-E-02
1999/8
ASAHI
KASEI
[AK2305]
DTMF RECEIVER
This circuit detects decodes DTMF signal outputs 4bits code. following table. Output code table Tone [Hz] (n=0,1)
High Tone [Hz] 1209 1336 1477 1209
1336 1477 1209
1336 1477 1336
DECODED OUTPUT
1209 1477 1633 1633 1633 1633
Decoded DTMF signals output DTO00-03,10-13 pins through tri-state buffers. outputs enabled DTOE pin. DTOE Input DTO00-03, DTO10-13 Output Hi-Impedance Decoded Output
GUARD TIME SETTING Input Signal Available Time(tREC) Inter Digit Pause Time(tID) settled adjusting Guard Time follows. Guard Time adjusted GTPn, GTAn(n=0-3.) Input Signal Available Time(tREC) Inter Digit Pause Time(tID) Detecting Signal Time(tDP) Guard Time(tGTP) Detecting Signal-stop Time(tDA) Guard Time(tGTA)
Range adjusting Guard Time(tGTP, tGTA) Step adjusting Guard Time(tGTP, tGTA)
Regarding relation between GTPn GTAn(n=0-3) Guard Time, next page. Also relation between Input Signal Available Time(tREC) Inter Digit Pause Time(tID) shown. C0029-E-02 1999/8
ASAHI
KASEI
[AK2305]
Relation between GTPn(n=0- Register GUARD TIME(tGTP) Input Signal Available Time(tREC) Register tGTP[ms] tREC[ms]=tGTP+tDP
tDP[ms]
tGTP default
Relation between GTAn(n=0- Register GUARD TIME(tGTA) Inter Digit Pause Time(tID Register tGTA[ms] tID[ms]=tGTA+tDA 17.5 17.5 25.5 25.5 33.5 33.5 41.5 41.5 49.5 49.5 57.5 57.5 65.5 65.5 73.5 73.5 81.5 81.5 89.5 89.5 97.5 97.5 105.5 105.5 113.5 113.5 121.5 121.5 129.5 tDA[ms]
tGTA default
NOTE tGTA tables above typical value. Regard margin ±1ms.
C0029-E-02
1999/8
ASAHI
KASEI
[AK2305]
TONE GENERATOR
Generates kinds tone, 400Hz 1300Hz. them selected TMDn register.
SELECTION TONE Selects tone from 400Hz/1300Hz TMDn register. Tone selection register TMDn (n=0,1)
Tone frequency 400Hz 1300Hz
Remarks Reset
SELECTION OUTPUT VRX0, VRX1, TNOUT available Tone output S1-S9 switch. S1-S9 switch controlled each register. Tone output switch controlling Output VRX0 circuits TONEGEN0 TONEGEN1
VRX1
TNOUT
Register setting
Remarks
when reset
TONE OUTPUT ENABLE Inputting TNOEn, defined tone output. Tone Output Enable TONEn Output States AGND Tone
INPUT
Input signal from external CPU/Tone generators. Signals output VRXn, TNOUT VRnR, VRTN. Output signals switched onto each which controlled registers. (See "SELECTION OUTPUT PIN" above.) Must input with external cap(>0.1uF.) Input impedance 200k±25%. C0029-E-02 1999/8
ASAHI
KASEI
[AK2305]
SERIAL INTERFACE
internal registers read/written with SCLK, DATA, pins. 1word consists 14bits. first 2bits instruction code which specifies read/write. following 3bits specify address. rest 8bits setting registers. Address (3bit)
Instruction code (2bit)
Data setting internal registers (8bit)
*)Dummy adjusting timing when reading data.
INSTRUCTION CODE Read/Write Read Write action
Other codes
SCLK WRITE READ Input data loaded into internal shift register rising edge SCLK. rising edge SCLK counted after falling edge When more than SCLK pulses: [WRITE] Data loaded into internal register rising edge SCLK 14th pulse. [READ] DATA switched input falling edge SCLK 14th pulse.
WRITE READ CANCELLATION WRITE cancelled when goes before rising edge SCLK 14th pulse. READ cancelled when goes before falling edge SCLK 14th pulse.
SERIAL WRITE READ (SERIAL ACCESS) must before next access successive access. When next access going done remains "L", successive access done.
C0029-E-02
1999/8
ASAHI
WRITE
KASEI
[AK2305]
Must goes once
SCLK DATA
Goes anytime after SCLK14th pulse
Address "000"
WRITE data address"000"
Instruction code
WRITE rising edge SCLK 14th pulse
Instruction Address code "010"
WRITE data address"010" DATApin Input Status (Hi-Z)
WRITE CANCELLATION WRITE cancellation
SCLK DATA
Address "000"
WRITE data address"000"
Instruction code
WRITE executed
Instruction code
Address "010"
WRITE data address"010"
WRITE SERIAL ACCESS SCLK DATA
Address "000"
WRITE data address"000"
Instruction code
Instructi code Execute
Address "010"
WRITE data address"010" Execute
C0029-E-02
1999/8
ASAHI
READ
KASEI
[AK2305]
Must goes once
DATA
Instruction code
Address "000"
READ data from address"000"
Instruction code
Address "010"
READ data from address"010"
READ OUTPUT PERIOD DATA SCLK DATA
Instruction code
Address "000"
READ data from address"000"
Instruction code
Address "010"
READ data from address"010"
READ PERIOD: Till earlier edge either rising SCLK 14th pulse falling.
READ SERIAL ACCESS SCLK DATA
READ data from address"010" Execute
Address "000"
READ data from address"000"
Instruction code
Instruction code Execute
Address "010"
DISCORD INSTRUCTION CODE
SCLK DATA
WRITE/READ executed
Other codes (not Instruction code)
Address "000"
WRITE/READ executed
Other codes (not Instruction code)
Address "010"
C0029-E-02
1999/8
ASAHI
KASEI REGISTER
[AK2305]
REGISTER
VR0T2
VR0T1
VR0T0
VR0R2
VR0R1
VR0R0
VR1T2
VR1T1
VR1T0
VR1R2
VR1R1
VR1R0
VRTN2
VRTN1
VRTN0
PCMIF1
PCMIF0
SEL2B
1stFS
PDDT1
PDDT0
PDCH1
PDCH0
ALAWN
MTDX1
MTDX0
TMD1
TMD0
GTA3
GTA2
GTA1
GTA0
GTP3
GTP2
GTP1
GTP0
Dummy Note) registers available write/read.
INITIALIZATION REGISTERS Only POWER RESET, registers initialized. When POWER RESET used, registers should through serial interface.
C0029-E-02
1999/8
ASAHI
KASEI
Default Function Receive gain adjustment -12dB 3dBstep 000: 1xx: -12dB used Transmit gain adjustment -12dB 3dBstep 000: 1xx: -12dB used Dummy Receive gain adjustment -12dB 3dBstep 000: 1xx: -12dB used Transmit gain adjustment -12dB 3dBstep 000: 1xx: -12dB used Dummy Gain adjustment tone output -12dB 3dBstep 000: 1xx: -12dB used Switch regulation tone output Tone Tone used Dummy Switch regulation tone output Tone Tone used Switch regulation tone output Tone Tone used Dummy
[AK2305]
Refer
FUNCTION REGISTER Address Name VR0R0 VR0R1 VR0R2 VR0T0 VR0T1 VR0T2 VR1R0 VR1R1 VR1R2 VR1T0 VR1T1 VR1T2 VRTN0 VRTN1 VRTN2
C0029-E-02
1999/8
ASAHI
KASEI
Name PDCH0 PDCH1 PDDT0 PDDT1 1stFS SEL2B PCMIF0 PCMIF1 TMD0 TMD1 MTDX0 MTDX1 ALAWN GTP0 GTP1 GTP2 GTP3 GTA0 GTA1 GTA2 GTA3 Default Function CODEC ch0,1 Power down control Power Power DTMF Receiver Power down control Power Power First select data channel assignment CH0->B1 interface select Multiplex/Non Multiplex Dummy TONEGEN tone frequency select 400Hz 1300Hz output(DX0,1pin) Mute MUTE A-law/u-law select 0:A-law 1:u-law used Dummy DTMF Receiver Guard Time tGTP setting
[AK2305]
Refer
Address
DTMF Receiver Guard Time tGTA setting Dummy
C0029-E-02
1999/8
ASAHI
KASEI
[AK2305]
BSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltages Digital Power Supply DVDD AVDD DVSS
Digital Input Voltage Analog Input Voltage Input current (except power supply pins) Storage Temperature Tstg Note voltages with respect ground. AVSS=
-0.3 -0.1 -0.3 -0.3
Normal operation guaranteed these extremes.
OPERATING ONDITIONS
Units
Parameter Power Supplies Analog power supply 4.75 Digital power supply DVDD Ambient Operating Temperature Frame Sync Frequency FS0,FS1 Note DVDD greater than AVDD, then will increase voltages reference ground AVSS=
AVDD
LECTRICAL
Unless otherwise noted, guaranteed AVDD=DVDD=+5V Characteristics Parameter Power Consumption FS0,FS1=8kHz
Conditions
78.8
Units
Output High Voltage1
Output Voltage (CMOS level) (TTL level) (TTL level) Input Capacitance Current
outp unloaded PDCH0,1 PDDT0,1=1,0 unload Except DTOn0-n3(n=0,1) =1.6mA
C0029-E-02
1999/8
ASAHI
CODEC
KASEI
[AK2305]
Absolute Gain Conditions Input: 0dBm0@1020Hz -0.6 Input: 0dBm0@1020Hz -0.6 3.14dBm0 Units Vrms Vrms Vrms
Parameter Transmit Gain Tracking Error 1020Hz Tone Receive Gain Tracking Error -10dBm0
-55dBm0 -50dBm0 -40dBm0 -55dBm0 -50dBm0 -40dBm0 3dBm0
-1.2 -0.2 -0.4
Parameter Transmit Frequency Response
0.05kHz 0.2kHz 3.0kHz 3.4kHz Relative 3.4kHz 4.0kHz
0.15
-0.15
Distortion Conditions 1020Hz Tone -30dBm0 -40dBm0 -30dBm0 -40dBm0 -6dBm@860Hz,1380Hz -Law, Psophometric Weighted A-Law Units
1020Hz Tone
Transmit Receive
C0029-E-02
1999/8
ASAHI
KASEI
Conditions =1600Hz =500Hz 600Hz =600Hz 1000Hz =1000Hz 2600Hz =2600Hz =2800Hz 3000Hz =500Hz =1000Hz =1600Hz ~2800Hz ~3000Hz
[AK2305]
Parameter Transmit Delay, Absolute Transmit Delay, Relative
Receive Delay, Absolute
Relative f=1600Hz
Parameter Idle Channel Noise Idle Channel Noise Noise, Single Frequency PSRR, Transmit
Conditions A-law, Psophometric A-law, Psophometric 100kHz
dBrnC0 dBrnC0
50kHz AVDD=DVDD=5V 100mVop Spurious Out-of-Band Signal 7.6kHz Output 3.4kHz 100kHz Note Analog Input Analog Ground Note tested production. Parameters guaranteed design.
Parameter Transmit Receive Receive Transmit Transmit Transmit Receive Receive
Intrachannel Crosstalk Conditions 0dBm0@VFXIN, Idle code 0dBm0 code level, VFXIN Vrms Units
C0029-E-02
1999/8
Parameter Input Leakage Current Input Resistance Load Resistance Load Capacitance Output
-100
+100
Parameter Output Voltage Load Resistance Load Capacitance Output
Parameter Input Leakage Current Input Resistance Load Resistance Load Capacitance Output
-100
+100
VR0T,VR0R,VR1T,VR1R,VRTN Step margin
Volume
-0.5
Parameter TNOUT Abcolute gain (Relative output signal 1kHz input) TNOUT TNOUT
Conditions VRTN=0dB
Unit
VRTN=0dB VRTN=0dB
C0029-E-02
Tone Generator Conditions Signal 1300Hz band noize level 4k-8kHz P-40 P-60 Note) decibels above below reference power into output level band transmit signal. 1300 Units
Parameter Valid Input Signal Levels signal) Note3,6,8 Frequecy Deviation accept Frequecy Deviation Reject Third Tone Tolerance Noise Tolerance Dial Tone Tolerance Input Impeedance Note2)Both tones composite signal have equal amplitudes. Note4)Bandwidth limited 3kHz Gaussian noise. Note6)For error rate better than 10,000. Note8)Twist high tone tone decibels above below reference power into
C0029-E-02
ASAHI
KASEI
[AK2305]
Parameters Tone Absent Detection Time Tone Duration Reject(*1) Interdigit Pause Accept(*1)
Condition
Units
DTOE=5V,unloaded DTOE=5V,unloaded DTOE=5V,unloaded =10k, =50pF
GPAn
Output Data Disable(DTOE DTO) GTPn, (n=0-3) default. Adjustable setting p.19 p.20.
tREJ
DTINx RegisterGTP Internal Counter tGTP ,tGTA
tREC
TONE
TONE #n+1
tGTP
RegisterGTA
tGTA
DTOxx STDx DTOE DECODED TONE #n-1 DECODED TONE
Hi-Z
DECODED TONE #n+1
tPSTD tQSTD tPTD tPTE
Figure DTMF Receiver Timing
1999/8
ASAHI
KASEI
[AK2305]
Timing Specification Unless otherwise noted, specification applies +85oC, DVDD AVDD 5V±5%,DVSS AVSS FS0,FS1 8kHz. timing parameters measured 2.0V =0.7V. Lomg Frame,Short Frame,GCI, Timing Parameter Frequency BCLK Frequency BCLK Pulse Width High BCLK Pulse Width Rising Time: (BCLK,FS0,FS1,DX0,DX1,DR0,DR1) Falling Time: (BCLK,FS0,FS1,DX0,DX1,DR0,DR1) Hold Time: BCLK High Setup Time: High BCLK Setup Time: BCLK Hold Time: BCLK Delay Time: BCLK High valid Long Frame Hold Time: period BCLK tHBFL
BCLK Symbol
4096
Unit
1/tPF 1/tPB tWBH tWBL tHBF tSFB tSDB tHBD (Note1) tDBD
Fig.2 Fig.3 Fig.4 Fig.5
Delay Time: BCLK High, whichever later,to valid (Note1) DZFL Delay Time: BCLK Low, whichever later, HightDZCL (Note1) Pulse Width Short Frame Hold Time: BCLK Setup Time: BCLK Delay Time: BCLK High-Z BCLK Frequency Delax Time: Second BCLK High-Z Setup Time: Second BCLK High Hold Time: Second BCLK High BCLK Frequency Note1) When with 150pF cap, LSTTL operating. C0029-E-02 1/tPB 1/tPB tDZCG tSDBG tHBDG tHBFS tSFBS (Note1) tDZCS tWFSL
Fig.2
Fig.3
4096
Fig.4
4096
Fig.5
1999/8
ASAHI
KASEI
[AK2305]
tWBL
tWBH
BCLK
tSFB tHBFL
(n=0
tHBF
tDZFL
tDBD
tDZCL
tDZCL
tSDB
tHBD
(n=0
tWFSL
Figure2
Interface Timing Long Frame
tWBL
tWBH
BCLK
tHBFS
(n=0
tSFBS tDBD tSDB tHBD
tDBD
tDZCS
Figure3
Interface Timing Short Frame
C0029-E-02
1999/8
ASAHI
KASEI
[AK2305]
tPBG tWBH
BCLK
tDBD tDZCG tHBDG tSDBG tWBL
BCLK
tSFB tHBFS
tHBF tDZFL
Figure4
Interface Timing
tPBI
tWBH
BCLK
tWBL
tHBF tHBFS tDBD tDZCS tHBD tSDB
Figure5
Interface Timing
C0029-E-02
1999/8
ASAHI
KASEI
[AK2305]
Serial Interface Timing Parameter SCLK Frequency SCLK Pulse Width High SCLK Pulse Width
Pulse Width Symbol
Unit SCLK Fig.6
1/tPSCLK tWCL tHCS tSCS
Hold Time: SCLK High Setup Time: SCLK High Rising Time: ,SCLK Falling Time: ,SCLK Setup Time: DATA SCLK High Hold Time: SCLK High DATA Hold Time: SCLK High Delay Time: SCLK DATA drive Delay Time: SCLK DATA valid Delay Time: SCLK DATA High-Z Delay Time: High DATA High-Z
Pulse Width High
tSDC tHDC tHCS2
Fig.6
tDVD tDDD tDZSD tDZCD tWCH
Fig.7
Fig.8
C0029-E-02
1999/8
ASAHI
KASEI
tWCL
[AK2305]
tWSH tWSL tPSCLK tHCS2
tHCS
SCLK
tSCS tSDC
DATA
Figure6
Serial Interface Timing WRITE
tWCL
tWSH tWSL tPSCLK tHCS2
tHCS
SCLK
tSCS tSDC tDDD tDVD
DATA
Figure7
tWCH
Serial Interface Timing READ
SCLK
tDZSD tDZCD
DATA
Figure8
Serial Interface Timing READ
C0029-E-02
1999/8
ASAHI KASEI
APPLICATION CIRCUIT EXAMPLE
[AK2305]
Analog input circuit(AMPT0,1) AK2305 op-amp analog input each channel. Each op-amp used gain adjustment. Op-amp used inverting amplifier. Feedback resistor must larger.
AK2305 GSXn VFXn (n=0,1)
C1=0.47uF R1=R2=33kOhm
BGREF
Analog output circuit(AMPR0,1) AK2305 op-amp analog input each channel. Each op-amp used gain adjustment. Op-amp used inverting amplifier. Feedback resistor must larger.
AK2305 GSRn VFRn VRXn SMFn BGREF (n=0,1)
R1=R2=33kOhm
INPUT external tone input through external capacitance more than 0.1uF.
AK2305
C0029-E-02
1999/8
ASAHI KASEI
DTIN0, DTIN1 INPUT There following cases case that DTMF tone input through DTIN0,DTIN1. (1)DTMF tone output from AMPT0,AMPT1 included AK2305 Connect GSXn with DTINn directly.
AK2305 GSXn
[AK2305]
DTINn
DTMF tone output from external amplifier DTMF tone input DTIN0,DTIN1 through external capacitance more than 0.1uF.
AK2305 DTIN0 DTIN1
Analog ground stabilization capacitor external capacitor more than 0.1uF should connected between VREF AVSS stabilize analog ground (VREF).
AK2305 VREF
Loop filter capcitor external capacitor more than 0.22uF should connected between AVSS.
AK2305
C0029-E-02
1999/8
ASAHI KASEI
[AK2305]
Power Supply attenuate power supply noise, connect capacitors between AVDD AVSS, DVDD DVSS, shown below.
AK2305 AVDD AVSS C1=C3=0.1uF C2=C4=10uF
DVDD DVSS
same supply both digital analog power supply (DVDD AVDD), insert resistor between AVDD DVDD. AVSS DVSS must separated board, connected them power supply unit. AK2305 AVDD AVSS DVDD DVSS Ground Power Supply Unit C1=C3=0.1uF C2=C4=10uF R1=10
C0029-E-02
1999/8
ASAHI KASEI
[AK2305]
PACKAGING INFOMATION
48pin LQFP Marking Pin#1 indication Date Code: digit XXXXX Marketing Code: AK2305 Logo
AK2305
XXXXX JAPAN
Outline Dimensions
9.0±0.2 1.7MAX
0.10 0.10±0.07
0.19±0.05
9.0±0.2
0.50
0.17±0.05
0.50±0.2
0°~10°
C0029-E-02
1999/8
ASAHI KASEI
[AK2305]
IMPORTANT NOTICE These products their specifications subject change without notice. Before considering application, consult Asahi Kasei Microsystems Co., Ltd. (AKM) sales office authorized distributor concerning their current status. assumes liability infringement patent, intellectual property, other right application information contained herein. export these products, devices systems containing them, require export license other official approval under regulations country export pertaining customs tariffs, currency exchange, strategic materials. products neither intended authorized critical components safety, life support, other hazard related device system, assumes responsibility relating such use, except with express written consent Representative Director AKM. used here: hazard related device system designed intended life support maintenance safety applications medicine, aerospace, nuclear energy, other fields, which failure function perform reasonably expected result loss life significant injury damage person property. critical component whose failure function perform reasonably expected result, whether directly indirectly, loss safety effectiveness device system containing which must therefore meet very high standards performance reliability. responsibility buyer distributor product distributes, disposes otherwise places product with third party notify that party advance above content conditions, buyer distributor agrees assume responsibility liability hold harmless from claims arising from said product absence such notification.
C0029-E-02
1999/8

KASEI [AK2305] AK2305 Dual CODEC ISDN TERMINAL ADAPTER

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