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ASAHI

KASEI

ASAHI
KASEI
AK2305
Dual PCM CODEC for ISDN TERMINAL ADAPTER
GENERAL DESCRIPTION
AK2305 is a dual PCM CODEC-Filter most suitable for ISDN Terminal Adapter. A-law / ulaw is selected by the internal register. In addition to CODEC, this device has dual DTMF receiver and External Tone Input pin. Input / output operational amplifiers included in this device are used for transmit / receive gain adjustment. AK2305 has internal volume control to attenuate signal from 0dB to -12dB by 3dB step control which is defined by an internal register written through the serial interface. PCM interface of AK2305 accepts several clock formats, which are Long Frame, Short Frame, GCI, IDL. 64k-4096kHz clock input is available for PCM interface.
FEATURE
PACKAGE
- 48LQFP 9.0 x 9.0 mm (0.5mm pin pitch)
C0029-E-02
ASAHI
KASEI
AK2305
CONTENTS
ITEMS
- BLOCK DIAGRAM....................... 3 - PIN ASSIGNMENT....................... 4 - PIN CONDITION........................ 5 - PIN FUNCTION......................... 6 - CIRCUIT DESCRIPTION................... 8 - FUNCTIONAL DESCRIPTION............... 9 - PCM INTERFACE................... 9 LONGFRAME / SHORTFRAME........ 10 GCI.......................... 12 IDL........................... 13 RESET........................ 14 - POWER DOWN.................... 15 - MUTE.......................... 17 - GAIN ADJUSTMENT................. 18 - DTMF RECEIVER.................. 19 - TONE GENERATOR................. 21 - AUX INPUT....................... 21 - SERIAL INTERFACE................ 22 - REGISTER............................ 25 - ABSOLUTE MAXIMUM RATINGS............. 28 - RECOMMENDED OPERATING CONDITIONS.... 28 - ELECTRICAL CHARACTERISTICS............ 28 - APPLICATION CIRCUIT EXAMPLE............39 - PACKAGE INFORMATION................. 42
C0029-E-02
ASAHI
KASEI
AK2305
BLOCK DIAGRAM
GSX0 47 VFX0 48
AMPT0
CODEC CH0
VRX0 VFR0 GSR0
AMPR0
S1 SMF0 S2 S3
DX0 DR0 26 FS0
GSX1 14 VFX1 13
AMPT1
S4 S5 SMF1 S6
CODEC CH1
VRX1 12 VFR1 11 GSR1 10 TNOUT 9 VREF
AMPR1
DX1 DR1 FS1
TONEGEN0
TNOE0 TNOE1 AUX MUTE0 MUTE1 DTO00-03 DTO10-13
TONEGEN1
BGREF
DTIN0
DTMF Receiver0 DTMF Receiver1
24 STD0 41-44
DTIN1 15 AVDD 6 AVSS 7 DVDD 31 DVSS 30
23 STD1 20 DTOE
Internal Register
Serial I / F
35 SCLK 34 DATA 36 CS 19 PD
TST1 TST2
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ASAHI
KASEI
AK2305
PIN ASSIGNMENT
FS1 FS0 BCLK DX1 DX0 DVSS DVDD DR1 DR0 DATA SCLK CS 25 26 27 28 29 30 31 32 33 34 35 36
DTO00 DTO01 DTO02 DTO03 DTO10 DTO11 DTO12 DTO13 TST1 DTIN0 GSX0 VFX0 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 STD0 STD1 TNOE0 TNOE1 DTOE PD MUTE0 MUTE1 TST2 DTIN1 GSX1 VFX1
12 11 10 9 8 7 6 5 4 3 2 1 VRX1 VFR1 GSR1 TNOUT AUX AVSS AVDD LPC VREF GSR0 VFR0 VRX0
C0029-E-02
ASAHI
KASEI
AK2305
PIN CONDITION
Pin# Name I / O Pin type AC load (MAX.) DC load (MIN.)
Outout status (Power down mode) Output status (Reset)
Remarks
VRX0 50pF 1 O Analog Hi-Z Hi-Z 10k VFR0 2 I Analog GSR0 50pF 3 O Analog Hi-Z Hi-Z 10k (1) VREF 4 O Analog external cap LPC 5 O Analog external cap AVDD 6 AVSS 7 AUX 8 I Analog TNOUT 50pF 9 O Analog Hi-Z Hi-Z 10k GSR1 50pF 10 O Analog Hi-Z Hi-Z 10k (1) VFR1 11 I Analog VRX1 50pF 12 O Analog Hi-Z Hi-Z 10k VFX1 13 I Analog GSX1 50pF 14 O Analog Hi-Z Hi-Z 10k (1) DTIN1 15 I Analog TST2 I TTL Factory use only 16 MUTE1 17 I TTL MUTE0 18 I TTL PD 19 I TTL DTOE 20 I TTL TNOE1 21 I TTL TNOE0 22 I TTL STD1 15pF 23 O CMOS L L STD0 15pF 24 O CMOS L L FS1 25 I TTL (2) FS0 26 I TTL BCLK 27 I TTL DX1 15pF 28 O CMOS Hi-Z Hi-Z DX0 15pF 29 O CMOS Hi-Z Hi-Z DVSS 30 DVDD 31 DR1 32 I TTL (3) DR0 33 I TTL DATA 15pF 34 I / O TTL / CMOS Input Input SCLK 35 I TTL CSN 36 I TTL DTO00 15pF 37 O CMOS Hi-Z Hi-Z DTO01 15pF 38 O CMOS Hi-Z Hi-Z DTO02 15pF 39 O CMOS Hi-Z Hi-Z DTO03 15pF 40 O CMOS Hi-Z Hi-Z DTO10 15pF 41 O CMOS Hi-Z Hi-Z DTO11 15pF 42 O CMOS Hi-Z Hi-Z DTO12 15pF 43 O CMOS Hi-Z Hi-Z DTO13 15pF 44 O CMOS Hi-Z Hi-Z TST1 I TTL Factory use only 45 DTIN0 46 I Analog GSX0 50pF 47 O Analog Hi-Z Hi-Z 10k (1) VFX0 48 I Analog 1) DC load(MIN.) includes a feedback resistance of input / output op-amp. 2) Pulled down to VSS in GCI / IDL mode. 3) Pulled down to VSS in 2ch Multiplex mode.
C0029-E-02
ASAHI
KASEI
AK2305
PIN FUNCTION
Pin# 48 47 1 2 3 10 11 12 14 13 29 Name VFX0 GSX0 VRX0 VFX0 GSR0 GSR1 VFR1 VRX1 GSX1 VFX1 DX0 I / O I O O I O O I O O I O Function Transmit analog input. Inverting input of transmit gain adjustment amplifier for channel 0. Output of transmit gain adjustment amplifier for channel 0. Receive analog output of SMF for channel 0. This output can drive 10k and 50pF. Transmit analog input. Inverting input of transmit gain adjustment amplifier for channel 0. Output of receive gain adjustment amplifier for channel 0. Output of receive gain adjustment amplifier for channel 1. Inverting input of receive gain adjustment amplifier for channel 1. Receive analog output of SMF for channel 1. This output can drive 10k and 50pF. Output of transmit gain adjustment amplifier for channel 1. Transmit analog input. Inverting input of transmit gain adjustment amplifier for channel 1. Serial output of PCM data of ch0. In Long Frame / Short Frame mode, output PCM data of ch0. In GCI / IDL mode, output PCM data of ch0 is multiplexed with ch1. The PCM data rate is synchronized with BCLK. See "PCM INTERFACE" from page 9. This output remains in the high impedance state except for the period of transmitting PCM data. Serial input of PCM data of ch0. In Long Frame / Short Frame mode, input PCM data of ch0. In GCI / IDL mode, input PCM data of ch0 is multiplexed with ch1. The PCM data rate is synchronized with BCLK. See "PCM INTERFACE" from page 9. Serial output of PCM data of ch1. In Long Frame / Short Frame mode, output PCM data of ch1. The PCM data rate is synchronized with BCLK. See "PCM INTERFACE" from page 9. This output remains in the high impedance state except for the period of transmitting PCM data. In 2ch multiplexd mode, this pin remains in the high impedance state. Serial input of PCM data of ch1. In Long Frame / Short Frame mode, input PCM data of ch1. The PCM data rate is synchronized with BCLK. See "PCM INTERFACE" from page 9. In GCI / IDL mode, this pin is pulled down to VSS. Frame sync input for channel 0. FS0 must be 8KHz clock synchronized in BCLK.
C0029-E-02
ASAHI
Pin# 25
KASEI
AK2305
Function Frame sync input for channel 1. FS1 must be 8KHz clock synchronized in BCLK. In GCI / IDL mode, this pin is pulled down to VSS. Bit clock of PCM data interface. This clock is apply for both ch0 and ch1. BCLK should be synchoronized with 8 x N kHz(FSn x N kHz). DTMF tone input of ch 0. Output of DTMF receiver 0. DTO00 is LSB.
BCLK DTIN0 DTO00 DTO01 DTO02 DTO03 STD0 DTIN1 DTO10 DTO11 DTO12 DTO13 STD1 DTOE TNOE0 TNOE1 AUX TNOUT DATA SCLK
Steering to delay output of ch0. After the DTMF decoding, latch is renewed and this output alters to high level. DTMF tone input. Output of DTMF receiver 1. DTO10 is LSB.
the output
MUTE0 MUTE1 PD LPC VREF DVDD DVSS AVDD AVSS TST1 TST2
Steering to delay output of ch0. After the DTMF decoding, the output latch is renewed and this output alters to high level. Output enable pin for the DTMF receiver. Output enable pin for the tone generator 0. Output enable pin for the tone generator 1. External tone input pin. Input signal should be through more than 0.1uF of an external capacitance. Tone output pin. Data input of serial interface. Clock input of serial interface. Read and write enable of serial interface. Active high input for ch0 mute. Active high input for ch0 mute. Active high input for all power down. Pin for PLL loop filter. Connect to AVSS with 0.22uF or larger. Analog ground output. To stabilize the analog ground, connect to AVSS with 0.1uF or larger. Digital positive supply voltage. System digital +5V supply. Digital negative supply voltage. System digital ground. Analog positive supply voltage. Systems analog +5V supply. Analog negative supply voltage. System analog ground. Only for factory use. Should to be fixed to DVSS.
C0029-E-02
ASAHI
KASEI
AK2305
CIRCUIT DESCRIPTION
AMPR0, 1
C0029-E-02
ASAHI
KASEI
AK2305
FUNCTIONAL DESCRIPTION
PCM INTERFACE
AK2305 supports the following types of format. One of those is selected by PCMIF0 and PCMIF1 registers. - Long Frame Sync(LF) - Short Frame Sync(SF) - GCI - IDL PCM data of both channels are multiplexed and interfaced through the common pins (DR0, DX0) in 2ch Multiplex I / F mode. But in 2ch Independent I / F mode of LF or SF, it is also available to interface through the independent pin(DR0 / 1, DX0 / 1) by channel. Register of PCM interface mode selection PCMIF1 PCMIF0 Interface 0 0 1 1 0 1 0 1 LF / SF (Non multiplex) LF / SF GCI IDL (2ch multiplex) (2ch multiplex) (2ch multiplex)
Frame sync FS0, FS1 FS0, FS1 FS0 FS0
Input pin DR0, DR1 DR0 DR0 DR0
Output pin DX0, DX1 DX0 DX0 DX0
Remarks
Reset
C0029-E-02
ASAHI
KASEI
AK2305
Long Frame Sync(LF) Short Frame Sync(SF)
FS0 BCLK DX0 DR0
Frame type LF SF
ShortFrame
FS0 BCLK DX0 DR0
FS0 FS1 SLOT DX0 DR0 1
ch0 output ch0 input
ch1 output ch1 input
ch0 output ch0 input
ch1 output ch1 input
C0029-E-02
ASAHI
KASEI
AK2305
FS0 FS1 SLOT DX0 DR0 DX1 DR1 1
ch0 output ch0 input ch1 output ch1 input
ch0 output ch0 input
ch1 output ch1 input
C0029-E-02
ASAHI
KASEI
AK2305
GCI(General Circuit Interface)
Interface used for ISDN. This data format is as below. PCM data channel assignment for B1 and B2 is defined by SEL2B register. CH0, 1selection SEL2B 0 1
CH0 B1 B2
CH1 B2 B1
Remarks Reset
Note: BCLK is twice the PCM data rate. BCLK is acceptable from 512kHz to 4096kHz.
FS0 BCLK DX0 DR0
C0029-E-02
ASAHI
KASEI
AK2305
IDL(Interchip Digital Link)
Interface used for ISDN. This data format is as below. PCM data channel assignment for B1 and B2 channel is defined by SEL2B register. CH0, 1selection SEL2B 0 1
CH0 B1 B2
CH1 B2 B1
Remarks Reset
Note: BCLK is same as the PCM data rate. BCLK is acceptable from 256kHz to 4096kHz.
FS0 BCLK DX0 DR0
C0029-E-02
ASAHI RESET
KASEI
AK2305
POWER ON RESET AK2305 automatically generates the internal reset pulse at the time of power on. Then all circuits are reset and internal registers are initialized. After reset operation, CODEC CH0 / CH1 circuits start to be initialized. It takes 150ms(typ.), 330ms(max) from power on to completion of initialization. )Output pins remain Hi-Z during the period in which the internal reset pulse is high(See page 5). The period of the reset pulse is about 20ms(typ), 200ms(max).
RECOMMENDED START UP PROCEDURE The following start up procedure is recommended when AK2305 is going to power up.
Power up
Write data to the internal register through serial I / F
- Write data to the internal register before CODEC starts working.
Supply FSn and BCLK - CODEC Initialization starts. Wait 130ms - CODEC Initialization complete. CODEC starts working
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KASEI
AK2305
POWER DOWN
All circuits
CODEC CH0 CODEC CH1 Block DTMF Receiver0 DTMF Receiver1
PDCH0
PDCH1 "0" : Normal "1" : Power down PDDT0
CANCELLATION OF POWER DOWN : CODEC When power down mode for CODEC CH0 / CH1 is cancelled, CODEC starts to be initialized. It takes 130mS(typ.).
Registers
PDDT1
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ASAHI
KASEI
AK2305
POWER DOWN MODE SETTING and POWER DOWN BLOCK POWER DOWN BLOCK PIN REGISTER AMPT0 VR0T Channel 0 AAF0 CODEC CH0 SMF0 VR0R AMPR0 AMPT1 VR1T Channel 1 AAF1 CODEC CH1 SMF1 VR1R AMPR1 PCM I / F TONEGEN 0 TONEGEN 1 VRTN DTMFR 0 DTMFR 1 PLL BGREF SERIAL I / F ALL BLOCK PD OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF CODEC CH0 PDCH0 CODEC CH1 PDCH1 CODEC CH0&1 PDCH0 PDCH1 CODEC CH0, DTMFR0 PDCH0 PDDT0 OFF OFF OFF OFF OFF CODEC CH1, DTMFR1 PDCH1 PDDT1
DTMFR0 PDDT0
DTMFR1 PDDT1
C0029-E-02
ASAHI MUTE
KASEI
AK2305
)TONE circuits are avialable even if the mute operates.
Remarks
FS0 BCLK DX0 DR0
VRX0 : VRX1 :
CODEC CH0 analog output is always at AGND level. TONEGEN0, 1output can be controlled by TNOE0, 1 pin. CODEC CH1 analog output is the signal converted from the PCM data of CH1 input through DR0 pin. TONEGEN0, 1 output can be controlled by TNOE0, 1 pin.
C0029-E-02
ASAHI
KASEI
AK2305
GAIN ADJUSTMENT
Analog input / output gain can be adjusted at the range from0 to -12dB (3dB / step5steps) by register. VR register VRnT2 VRnR2 VRTN2 0 0 0 0 1
VRnT1 VRnR1 VRTN1 0 0 1 1 -
VRnT0 VRnR0 VRTN0 0 1 0 1 -
Gain 0 dB -3 dB -6 dB -9 dB -12 dB
Remarks Reset
) This table is applicable to VR0T, VR0R, VR1T, VR1R , and VRTN registers.
C0029-E-02
ASAHI
KASEI
AK2305
DTMF RECEIVER
High Tone Hz 1209 1336 1477 1209
941 697 770 852 941 DECODED OUTPUT
Decoded DTMF signals are output at DTO00-03, 10-13 pins through tri-state buffers. The outputs are enabled by DTOE pin. DTOE Input 0 1 DTO00-03, DTO10-13 Output Hi-Impedance Decoded Output
Range of adjusting Guard Time(tGTP, tGTA) Step of adjusting Guard Time(tGTP, tGTA)
ASAHI
KASEI
AK2305
tDPms
min 5 typ 11 max 14
tGTP default
min 0.5
tGTA default
C0029-E-02
ASAHI
KASEI
AK2305
TONE GENERATOR
Generates two kinds of tone, 400Hz and 1300Hz. One of them is selected by TMDn register.
Tone frequency 400Hz 1300Hz
Remarks Reset
SELECTION OF OUTPUT PIN VRX0, VRX1, TNOUT is available for Tone output pin by S1-S9 switch. S1-S9 switch is controlled by each register. Tone output by switch controlling Output VRX0 circuits TONEGEN0 TONEGEN1 AUX S1 S2 S3
VRX1 S4 S5 S6
TNOUT S7 S8 S9
Register setting
Remarks
"0" : OFF "1" : ON
All "0" when reset
TONE OUTPUT ENABLE Inputting "1" to TNOEn, defined tone is output. Tone Output Enable TONEn Output States 0 1 AGND Tone
AUX INPUT
ASAHI
KASEI
AK2305
SERIAL INTERFACE
The internal registers can be read / written with SCLK, DATA, and CS pins. 1word consists of 14bits. The first 2bits are the instruction code which specifies read / write. The following 3bits specify the address. The rest of 8bits are for setting registers. B13 I1 B12 I0 B11 A2 B10 A1 Address (3bit) B9 A0 B8 B7 D7 B6 D6 B5 D5 B4 D4 B3 D3 B2 D2 B1 D1 B0 D0
Instruction code (2bit)
Data for setting internal registers (8bit)
)Dummy bit for adjusting the I / O timing when reading data.
INSTRUCTION CODE I1 1 1 I0 0 1 Read / Write Read Write No action
Other codes
SCLK and WRITE / READ (1) Input data are loaded into the internal shift register at the rising edge of SCLK. (2) The rising edge of SCLK is counted after the falling edge of CS . (3) When CS is "L" and more than 14 SCLK pulses: WRITE Data are loaded into the internal register at the rising edge of the SCLK 14th pulse. READ DATA pin is switched to an input pin at the falling edge of the SCLK 14th pulse.
CS and WRITE / READ CANCELLATION (1) WRITE is cancelled when CS goes up before the rising edge of the SCLK 14th pulse. (2) READ is cancelled when CS goes up before the falling edge of the SCLK 14th pulse.
SERIAL WRITE / READ (SERIAL ACCESS) (1) CS must go up to "H" before the next access in successive access. (2) When the next access is going to be done , if CS remains to be "L", successive access can not be done.
C0029-E-02
ASAHI
WRITE
KASEI
AK2305
Must goes up once
CS SCLK DATA
Goes up anytime after SCLK14th pulse
0 Address "000"
D1 D0 WRITE data to address"000"
Instruction code
WRITE at the rising edge of SCLK 14th pulse
Instruction Address code "010" Z
WRITE data to address"010" DATApin : Input Status (Hi-Z)
WRITE - CANCELLATION WRITE cancellation
CS SCLK DATA
0 Address "000"
D1 WRITE data to address"000"
Instruction code
WRITE is not executed
Instruction code
Address "010"
WRITE data to address"010"
WRITE - SERIAL ACCESS CS SCLK DATA
0 Address "000"
D1 D0 WRITE data to address"000"
Instruction code
Instructi on code Execute
Address "010"
WRITE data to address"010" Not Execute
C0029-E-02
ASAHI
KASEI
AK2305
Must goes up once
1 Instruction code
0 Address "000"
D1 READ data from address"000"
0 Instruction code
1 Address "010"
D0 READ data from address"010"
READ - OUTPUT PERIOD OF DATA PIN CS SCLK DATA
Instruction code
Address "000"
READ data from address"000"
Instruction code
Address "010"
READ data from address"010"
READ PERIOD: Till the earlier edge of either CS rising up or SCLK 14th pulse falling.
READ - SERIAL ACCESS CS SCLK DATA
Z 1 2 3 4 13 14 1 Z 2 3 4 Z READ data from address"010" Not Execute 13 14
0 Address "000"
D1 D0 READ data from address"000"
Instruction code
Instruction code Execute
Address "010"
DISCORD OF INSTRUCTION CODE
CS SCLK DATA
Other codes (not Instruction code)
Address "000"
WRITE / READ is not executed
Other codes (not Instruction code)
Address "010"
C0029-E-02
ASAHI
KASEI REGISTER
AK2305
REGISTER MAP
Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
D6 VR0T2
D5 VR0T1
D4 VR0T0
D2 VR0R2
D1 VR0R1
D0 VR0R0
VR1T2
VR1T1
VR1T0
VR1R2
VR1R1
VR1R0
VRTN2
VRTN1
VRTN0
PCMIF1
PCMIF0
SEL2B
1stFS
PDDT1
PDDT0
PDCH1
PDCH0
ALAWN
MTDX1
MTDX0
) Dummy Bit Note) All registers are available for write / read.
INITIALIZATION OF REGISTERS Only at POWER ON RESET, registers are initialized. When POWER ON RESET is not used, all registers should be set through a serial interface.
C0029-E-02
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KASEI
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Function Receive gain adjustment on ch0 0 to -12dB by 3dBstep 000: 0dB 1xx: -12dB Not used Transmit gain adjustment on ch0 0 to -12dB by 3dBstep 000: 0dB 1xx: -12dB Not used Dummy bit Receive gain adjustment on ch1 0 to -12dB by 3dBstep 000: 0dB 1xx: -12dB Not used Transmit gain adjustment on ch1 0 to -12dB by 3dBstep 000: 0dB 1xx: -12dB Not used Dummy bit Gain adjustment of tone output 0 to -12dB by 3dBstep 000: 0dB 1xx: -12dB Not used Switch regulation for tone output 0: Tone OFF 1: Tone ON Not used Dummy bit Switch regulation for tone output 0: Tone OFF 1: Tone ON Not used Switch regulation for tone output 0: Tone OFF 1: Tone ON Not used Dummy bit
AK2305
Refer to
FUNCTION OF REGISTER Address Bit Name 000 0 VR0R0 1 VR0R1 2 VR0R2 3 4 VR0T0 5 VR0T1 6 VR0T2 7 8 001 0 VR1R0 1 VR1R1 2 VR1R2 3 4 VR1T0 5 VR1T1 6 VR1T2 7 8 010 0 VRTN0 1 VRTN1 2 VRTN2 3 4 S7 5 S8 6 S9 7 8 011 0 S1 1 S2 2 S3 3 4 S4 5 S5 6 S6 7 8 -
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KASEI
AK2305
Refer to 15 9 12 9
Address 100
DTMF Receiver Guard Time tGTA setting Dummy bit
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KASEI
AK2305
BSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltages Digital Power Supply Min DVDD AVDD DVSS Max 6.5 V V V V V C
Normal operation is not guaranteed at these extremes.
OPERATING ONDITIONS
Typ 5.0 5.0 8 Units V C
AVDD 85
LECTRICAL C
Conditions
Max 105 60 78.8
Units
PDD Output High Voltage1 VOH
Output Low Voltage V (CMOS level) V (TTL level) V (TTL level) Ii Input Capacitance Io Current
C0029-E-02
ASAHI
CODEC
KASEI
AK2305
Absolute Gain Conditions Input: 0dBm0@1020Hz -0.6 Input: 0dBm0@1020Hz -0.6 3.14dBm0 Typ Units Vrms dB Vrms dB Vrms
Parameter Transmit Gain Tracking Error 1020Hz Tone Receive Gain Tracking Error -10dBm0
-55dBm0 ~ -50dBm0 -40dBm0 ~ -55dBm0 -50dBm0 ~ -40dBm0 3dBm0
Min -1.2 -0.2 -0.4
Max 0.4 1.2 0.2 dB
Parameter Transmit Frequency Response
0.05kHz 0.2kHz 0.3 3.0kHz 3.4kHz Relative to: ~ 3.4kHz 4.0kHz
Max -26 0.15 0 -14
Distortion Conditions 1020Hz Tone ~ -30dBm0 -40dBm0 ~ ~ -30dBm0 -40dBm0 ~ 25 36 25 36 -6dBm@860Hz, 1380Hz -Law, Psophometric Weighted for A-Law Typ Units dB dB dB dB dB
1020Hz Tone
Transmit Receive
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AK2305
Max 560 220 145 75 us 155 450 -
Parameter Transmit Delay, Absolute Transmit Delay, Relative
Receive Delay, Absolute
us 125 175
Max 10 dBrnC0 -80 dBrnC0 -80 -53 dB
Parameter Transmit to Receive Receive to Transmit Transmit to Transmit Receive to Receive
Max -75 -75 -75 -75
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Parameter Input Leakage Current Input Resistance Load Resistance Load Capacitance Output
Min -100 -
Parameter Output Voltage Load Resistance Load Capacitance Output
Min 2.3
Parameter Input Leakage Current Input Resistance Load Resistance Load Capacitance Output
Min -100 -
VR0T, VR0R, VR1T, VR1R, VRTN Pin Step margin
Volume
Min -0.5
max dB
Parameter TNOUT AUX Abcolute gain (Relative to output signal 1kHz input) TNOUT TNOUT
Unit dBm
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min -19 10
Max dBm
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AK2305
Parameters t Tone Absent Detection Time t Tone Duration Reject(1) Interdigit Pause Accept(1) t t t t t
Condition 5
Units ms
10 GPAn
DTINx RegisterGTP Internal Counter tGTP , tGTA
tREC tDP
TONE #n
tID tDA
TONE #n+1
RegisterGTA
DTOxx STDx DTOE DECODED TONE #n-1 DECODED TONE #n
DECODED TONE #n+1
tPSTD tQSTD tPTD tPTE
Figure 1 : DTMF Receiver Timing
ASAHI
KASEI
AK2305
BCLK Symbol
Min 64 80 80
Max 4096
Unit Ref fig kHz kHz ns ns
1 / tPF 1 / tPB tWBH tWBL tR tF tHBF tSFB tSDB tHBD (Note1) tDBD
Fig.2 Fig.3 Fig.4 Fig.5
Delay Time: FS or BCLK High, whichever is later, to DX valid t (Note1) DZFL Delay Time: FS or BCLK Low, whichever is later, to DX HightDZCL Z (Note1) FS Pulse Width Low Short Frame Hold Time: BCLK Low to FS Low Setup Time: FS Low to BCLK Low Delay Time: BCLK Low to DX High-Z GCI BCLK Frequency Delax Time: Second BCLK Low to DX High-Z Setup Time: DR to Second BCLK High Hold Time: Second BCLK High to DR IDL BCLK Frequency Note1) When with 150pF cap, and two LSTTL operating. C0029-E-02 34 1 / tPB 1 / tPB tDZCG tSDBG tHBDG tHBFS tSFBS (Note1) tDZCS tWFSL
Fig.2
ns ns ns Fig.3
kHz ns ns ns Fig.4
Fig.5
ASAHI
KASEI
AK2305
tSFB tHBFL
tDZFL
tDZCL 7 8
tDZCL
3 tSDB
4 tHBD
tPF tWFSL
Figure2 :
t SFB tHBFS
tSFBS tDBD MSB 2 3 tSDB 4 tHBD 5
tDZCS
Figure3 :
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ASAHI
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AK2305
tDBD tDZCG 3 4 5 tHBDG tSDBG 6 7 8 MSB 2 3 4 tWBL
tSFB tHBFS
tHBF tDZFL
Figure4 :
8 tWBL
tHBF tHBFS tDBD tDZCS 3 4 5 tHBD tSDB 6 7 8 MSB 2 3 4 5 6 7 8
Figure5 :
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AK2305
Serial Interface Timing Parameter SCLK Frequency SCLK Pulse Width High SCLK Pulse Width Low
CS Pulse Width Low Symbol
Unit Ref fig MHz ns ns SCLK ns ns Fig.6
1 / tPSCLK tW SH tW SL tWCL tHCS tSCS tR tF 40 40 14 80 40
Hold Time: SCLK High to CS Low Setup Time: CS Low to SCLK High Rising Time: CS , SCLK Falling Time: CS , SCLK W R I T E Setup Time: DATA to SCLK High Hold Time: SCLK High to DATA Hold Time: SCLK Low to CS High R E A D Delay Time: SCLK Low to DATA pin drive Delay Time: SCLK Low to DATA valid Delay Time: SCLK Low to DATA High-Z Delay Time: CS High to DATA High-Z
CS Pulse Width High
tSDC tHDC tHCS2
ns ns ns Fig.6
tDVD tDDD tDZSD tDZCD tWCH
Fig.7
Fig.8
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ASAHI
KASEI
AK2305
tWSH tWSL tPSCLK tF tR tHCS2
tHD tSCS tSDC
Figure6 :
tWSH tWSL tPSCLK tF tR tHCS2
tHD tSCS tSDC tDDD Z I0 A2 A1 A0 D7 D6 - D1 D0 tDVD
Figure7 :
tDZSD tDZCD Z Z
Figure8 :
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ASAHI KASEI
APPLICATION CIRCUIT EXAMPLE
AK2305
Analog input circuit(AMPT0, 1) AK2305 has an op-amp at analog input of each channel. Each op-amp can be used as a gain adjustment. Op-amp can be used as an inverting amplifier. Feedback resistor must be 10k or larger.
BGREF
Analog output circuit(AMPR0, 1) AK2305 has an op-amp at analog input of each channel. Each op-amp can be used as a gain adjustment. Op-amp can be used as an inverting amplifier. Feedback resistor must be 10k or larger.
AUX INPUT An external tone is input to AUX through an external capacitance of more than 0.1uF.
AK2305 AUX C
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ASAHI KASEI
DTIN0, DTIN1 INPUT There are the following 2 cases in case of that DTMF tone is input through DTIN0, DTIN1. (1)DTMF tone is output from AMPT0, AMPT1 included AK2305 Connect GSXn with DTINn directly.
AK2305 GSXn
AK2305
DTINn
(2) DTMF tone is output from an external amplifier DTMF tone is input to DTIN0, DTIN1 through an external capacitance of more than 0.1uF.
AK2305 DTIN0 DTIN1 C
Analog ground stabilization capacitor An external capacitor of more than 0.1uF should be connected between VREF and AVSS to stabilize analog ground (VREF).
AK2305 VREF C +
PLL Loop filter capcitor An external capacitor of more than 0.22uF should be connected between LPC and AVSS.
AK2305 LPC C +
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ASAHI KASEI
AK2305
Power Supply To attenuate the power supply noise, connect capacitors between AVDD and AVSS, and DVDD and DVSS, as shown below.
DVDD C3 DVSS
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ASAHI KASEI
AK2305
PACKAGING INFOMATION
- 48pin LQFP Marking (1) Pin#1 indication (2) Date Code: 5 digit XXXXX (3) Marketing Code: AK2305 (4) AKM Logo
AK2305
XXXXX JAPAN
Outline Dimensions
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ASAHI KASEI
AK2305
IMPORTANT NOTICE · These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. · AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. · Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. · AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. · It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
C0029-E-02