SST34HF3223B SST34HF3243B SST34HF3223B SST24HF3243B32 Mbit Concur
|
|
|
Top Searches for this datasheet
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory
SST34HF3223B SST34HF3243B
SST34HF3223B SST24HF3243B32 Mbit Concurrent SuperFlash Mbit SRAM ComboMemories
FEATURES:
Flash Organization: Quad-Bank Architecture Concurrent Read-While-Write Operation Mbit Mbit Mbit Mbit SRAM Organization: Mbit: 256K 128K Mbit: 512K 256K Single 2.7-3.3V Read-While-Write Operations Superior Reliability Endurance: 100,000 Cycles (typical) Greater than years Data Retention Power Consumption: Active Current: (typical) Standby Current: (typical) Sector-Erase Capability Uniform KWord sectors Block-Erase Capability Uniform KWord blocks Read Access Time Flash: SRAM: Latched Address Data Fast Erase Word-Program: Sector-Erase Time: (typical) Block-Erase Time: (typical) Chip-Erase Time: (typical) Word-Program Time: (typical) Chip Rewrite Time: seconds (typical) Automatic Write Timing Internal Generation End-of-Write Detection Toggle Data# Polling CMOS Compatibility JEDEC Standard Command Packages Available 56-ball LFBGA (10mm 12mm 1.4mm)
PRODUCT DESCRIPTION
SST34HF3223B/3243B ComboMemory devices integrate four CMOS flash memory banks with 256K 128K 512K 256K CMOS SRAM memory bank Multi-Chip Package (MCP). These devices fabricated using SST's proprietary, high-performance CMOS SuperFlash technology incorporating split-gate cell design thick oxide tunneling injector attain better reliability manufacturability compared with alternate approaches. SST34HF3223B/3243B devices ideal applications such cellular phones, PDAs other portable electronic devices power small form factor system. SST34HF3223B/3243B features multiple flash memory bank architecture allowing concurrent operations between four flash memory banks SRAM. devices read data from either bank while Erase Program operation progress opposite bank. four flash memory banks partitioned Mbit Mbit storing boot code, program code, configuration/parameter data user data. SuperFlash technology provides fixed Erase Program times, independent number Erase/Program cycles that have occurred. Therefore, system software hardware does have modified de-rated necessary with alternative flash technologies, whose Erase
©2002 Silicon Storage Technology, Inc. S71197-00-000 1/02
Program times increase with accumulated Erase/Program cycles. SST34HF3223B/3243B devices offer typical endurance 100,000 cycles. Data retention rated greater than years. With high performance WordProgram, flash memory banks provide typical WordProgram time µsec. entire flash memory bank erased programmed word-by-word typically seconds SST34HF3223B/3243B, when using interface features such Toggle Data# Polling indicate completion Program operation. protect against inadvertent flash write, SST34HF3223B/3243B devices contain on-chip hardware software data protection schemes. flash SRAM operate independent memory banks with respective bank enable signals. memory bank selection done bank enable signals. SRAM bank enable signal, BES1# BES2, selects SRAM bank. flash memory bank enable signal, BEF# (BEF1# BEF2#), used with Software Data Protection (SDP) command sequence when controlling Erase Program operations flash memory bank. memory banks superimposed same memory address space where they share common address lines, data lines, which minimize power consumption area.
logo SuperFlash Trademarks registered Silicon Storage Technology, Inc. U.S. Patent Trademark Office. Concurrent SuperFlash, CSF, ComboMemory trademarks Silicon Storage Technology, Inc. These specifications subject change without notice.
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF3223B SST34HF3243B
Preliminary Information Designed, manufactured, tested applications requiring power small form factor, SST34HF3223B/ 3243B offered both commercial extended temperatures small footprint package meet board space constraint requirements. word address word data. During Word-Program operation, addresses latched falling edge either BEF# (BEF1# BEF2#) WE#, whichever occurs last. data latched rising edge either BEF# (BEF1# BEF2#) WE#, whichever occurs first. third step internal Program operation which initiated after rising edge fourth BEF# (BEF1# BEF2#), whichever occurs first. Program operation, once initiated, will completed (typically) within Figures BEF# (BEF1# BEF2#) controlled Program operation timing diagrams Figure flowcharts. During Program operation, only valid reads Data# Polling Toggle Bit. During internal Program operation, host free perform additional tasks. commands issued during internal Program operation ignored.
Device Operation
SST34HF3223B/3243B uses BES1#, BES2 BEF# (BEF1# BEF2#) control operation either flash SRAM memory bank. When BEF# (BEF1# BEF2#) low, flash bank activated Read, Program Erase operation. When BES1# low, BES2 high SRAM activated Read Write operation. BEF# (BEF1# BEF2#) BES1# cannot level, BES2 cannot high level same time. bank enable signals asserted, contention will result device suffer permanent damage. address, data, control lines shared flash SRAM memory banks which minimizes power consumption loading. device goes into standby when BEF# (BEF1# BEF2#) BES1# bank enables raised VIHC (Logic High) when BEF# (BEF1# BEF2#) high BES2 low.
Flash Sector/Block-Erase Operation
Sector/Block-Erase operation allows system erase device sector-by-sector block-by-block basis. SST34HF3223B/3243B offer both Sector-Erase Block-Erase mode. sector architecture based uniform sector size KWord. Block-Erase mode based uniform block size KWord. SectorErase operation initiated executing six-byte command sequence with Sector-Erase command (30H) sector address (SA) last cycle. Block-Erase operation initiated executing six-byte command sequence with Block-Erase command (50H) block address (BA) last cycle. sector block address latched falling edge sixth pulse, while command (30H 50H) latched rising edge sixth pulse. internal Erase operation begins after sixth pulse. Figures timing waveforms. commands issued during Sector- Block-Erase operation ignored.
Concurrent Read/Write Operation
Quadruple bank architecture SST34HF3223B/3243B devices allows Concurrent Read/Write operation whereby user read from bank while Program Erase other bank. This operation used when user needs read system code bank while updating data other bank. Figure Quad-Bank Memory Organization.
Flash Read Operation
Read operation SST34HF3223B/3243B controlled BEF# (BEF1# BEF2#) OE#, both have system obtain data from outputs. BEF# (BEF1# BEF2#) used device selection. When BEF# (BEF1# BEF2#) high, chip deselected only standby power consumed. output control used gate data from output pins. data high impedance state when either BEF# (BEF1# BEF2#) high. Refer Read cycle timing diagram further details (Figure
Flash Chip-Erase Operation
SST34HF3223B/3243B provide Chip-Erase operation, which allows user erase unprotected sectors/ blocks state. This useful when device must quickly erased. Chip-Erase operation initiated executing sixbyte command sequence with Chip-Erase command (10H) address 5555H last byte sequence. Erase operation begins with rising edge sixth BEF# (BEF1# BEF2#), whichever occurs first. selected flash bank, either BEF1# BEF2# will complete Chip-Erase operation. During Erase operation, only valid Read Toggle Data# Polling. Table
Flash Word-Program Operation
SST34HF3223B/3243B programmed wordby-word basis. Before Program operation, memory must erased first. Program operation consists three steps. first step three-byte load sequence Software Data Protection. second step load
©2002 Silicon Storage Technology, Inc.
S71197-00-000 1/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF3223B SST34HF3243B
Preliminary Information command sequence, Figure timing diagram, Figure flowchart. commands issued during Chip-Erase operation ignored. tion completed, will produce `1'. Data# Polling (DQ7) valid after rising edge fourth (BEF1# BEF2#) pulse Program operation. Sector-, Block-, Chip-Erase, Data# Polling (DQ7) valid after rising edge sixth (BEF1# BEF2#) pulse. Figure Data# Polling (DQ7) timing diagram Figure flowchart. There recovery time (TBR) required before valid data read data bus. commands entered immediately after becomes true data.
Flash Write Operation Status Detection
SST34HF3223B/3243B provide hardware software means detect completion Write (Program Erase) cycle, order optimize system Write cycle time. hardware detection uses Ready/Busy# (RY/BY#) pin. software detection includes status bits: Data# Polling (DQ7) Toggle (DQ6). End-of-Write detection mode enabled after rising edge WE#, which initiates internal Program Erase operation. actual completion nonvolatile Write asynchronous with system; therefore, either Ready/Busy# (RY/ BY#), Data# Polling (DQ7), Toggle (DQ6) Read simultaneous with completion Write cycle. this occurs, system possibly erroneous result, i.e., valid data appear conflict with either DQ6. order prevent spurious rejection, erroneous result occurs, software routine should include loop read accessed location additional times. both reads valid, then device completed Write cycle, otherwise rejection valid.
Flash Toggle (DQ6)
During internal Program Erase operation, consecutive attempts read will produce alternating i.e., toggling between When internal Program Erase operation completed, will stop toggling. device then ready next operation. Toggle (DQ6) valid after rising edge fourth (BEF1# BEF2#) pulse Program operation. Sector-, Block- Chip-Erase, Toggle (DQ6) valid after rising edge sixth (BEF1# BEF2#) pulse. Figure Toggle timing diagram Figure flowchart. There recovery time (TBR) required before valid data read data bus. commands entered immediately after longer toggles.
Ready/Busy# (RY/BY#)
SST34HF3223B/3243B includes Ready/Busy# (RY/BY#) output signal that applies flash Bank only. During initiated operation, e.g., Erase, Program, Read operation, RY/BY# actively pulled low, indicating controlled operation progress. status RY/BY# valid after rising edge fourth CE#) pulse Program operation. Sector-, Block-, Bank-Erase, RY/BY# valid after rising edge sixth (CE#) pulse. RY/BY# open drain output that allows several devices tied parallel external pull-up resistor. Ready/Busy# high impedance whenever high RST# low.
Data Protection
SST34HF3223B/3243B provide both hardware software features protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: BEF# (BEF1# BEF2#) pulse less than will initiate Write cycle. Write Inhibit Mode: Forcing low, BEF# (BEF1# BEF2#) high, high will inhibit Write operation. This prevents inadvertent writes during power-up power-down.
Flash Data# Polling (DQ7)
When SST34HF3223B/3243B internal Program operation, attempt read will produce complement true data. Once Program operation completed, will produce true data. Note that even though have valid data immediately following completion internal Write operation, remaining data outputs still invalid: valid data entire data will appear subsequent successive Read cycles. During internal Erase operation, attempt read will produce `0'. Once internal Erase opera©2002 Silicon Storage Technology, Inc.
Hardware Block Protection
SST34HF3223B/3243B provide hardware block protection which protects outermost KWord Bank block protected when held low. Figure Block-Protection location. user disable block protection driving high thus allowing erase program data into protected sectors. must held high prior issuing write command remain stable until after entire Write operation completed.
S71197-00-000 1/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF3223B SST34HF3243B
Hardware Reset (RST#)
RST# provides hardware method resetting device read array data. When RST# held least TRP, in-progress operation will terminate return Read mode (see Figure 19). When internal Program/Erase operation progress, minimum period TRHR required after RST# driven high before valid Read take place (see Figure 18). Erase operation that been interrupted needs reinitiated after device resumes normal operation mode ensure data integrity.
TABLE PRODUCT IDENTIFICATION
Address Manufacturer's Device SST34HF3223B SST34HF3243B 0001H 0001H 2761M 2761M
T1.1
Data 00BFH
0000H
Product Identification Mode Exit
order return standard Read mode, Software Product Identification mode must exited. Exit accomplished issuing Software Exit command sequence, which returns device Read mode. This command also used reset device Read mode after inadvertent transient condition that apparently causes device behave abnormally, e.g., read correctly. Please note that Software Exit command ignored during internal Program Erase operation. Table software command codes, Figure timing waveform Figure flowchart.
Software Data Protection (SDP)
SST34HF3223B/3243B provide JEDEC standard Software Data Protection scheme data alteration operations, i.e., Program Erase. Program operation requires inclusion three-byte sequence. three-byte load sequence used initiate Program operation, providing optimal protection from inadvertent Write operations, e.g., during system power-up power-down. Erase operation requires inclusion six-byte sequence. SST34HF3223B/3243B shipped with Software Data Protection permanently enabled. Table specific software command codes. During command sequence, invalid commands will abort device Read mode within TRC. contents DQ15-DQ8 VIH, other value, during command sequence.
SRAM Operation
With BES1# low, BES2 BEF# (BEF1# BEF2#) high, SST34HF3223B operates 256K 128K CMOS SRAM, SST34HF3243B operates 512K 256K CMOS SRAM, with fully static operation requiring external clocks timing strobes. CIOs configures SRAM SRAM operation modes. SST34HF3223B SRAM mapped into first KWord address space device, SST34HF3243B SRAM mapped into first KWord address space. When BES1#, BEF# (BEF1# BEF2#) high BES2 low, memory banks deselected device enters standby. Read Write cycle times equal. control signals UBS# LBS# provide access upper data byte lower data byte. Table SRAM Read Write data byte control modes operation.
Product Identification
Product Identification mode identifies devices SST34HF3223B SST34HF3243B manufacturer SST. This mode accessed software operations only. hardware device Read operation, which typically used programmers cannot used this device because shared lines between flash SRAM multi-chip package. Therefore, application high voltage damage this device. Users software Product Identification operation identify part (i.e., using device code) when using multiple manufacturers same socket. details, Tables software operation, Figure software entry Read timing diagram Figure entry command sequence flowchart.
SRAM Read
SRAM Read operation SST34HF3223B/3243B controlled BES1#, both have with BES2 high system obtain data from outputs. BES1# BES2 used SRAM bank selection. output control used gate data from output pins. data high impedance state when high. Refer Read cycle timing diagram, Figure further details.
©2002 Silicon Storage Technology, Inc.
S71197-00-000 1/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF3223B SST34HF3243B
SRAM Write
SRAM Write operation SST34HF3223B/3243B controlled BES1#, both have low, BES2 high system write SRAM. During Word-Write operation, addresses data referenced rising edge BES1# falling edge BES2 whichever occur first. write time measured from last falling edge BES1# rising edge BES2 first rising edge BES1# falling edge BES2. Refer Write cycle timing diagram, Figures further details.
FUNCTIONAL BLOCK DIAGRAM
Address Buffers
SuperFlash Memory (Bank
BEF1# BEF2# LBS# UBS# BES1# BES2 CIOs RST# RY/BY#
SuperFlash Memory (Bank
Control Logic Buffers
DQ15
Address Buffers Most significant address
Mbit Mbit SRAM
B1.0
©2002 Silicon Storage Technology, Inc.
S71197-00-000 1/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF3223B SST34HF3243B
1FFFFFH 1F8000H 1F7FFFH 1F0000H 1EFFFFH 1E8000H 1E7FFFH 1E0000H 1DFFFFH 1D8000H 1D7FFFH 1D0000H 1CFFFFH 1C8000H 1C7FFFH 1C0000H 1BFFFFH 1B8000H 1B7FFFH 1B0000H
Block Block Block
Bank
Block Block Block Block Block Block Block
Bank
Bank
11FFFFH 118000H 117FFFH 110000H 10FFFFH 108000H 107FFFH 100000H FFFFFH F8000H F7FFFH F0000H EFFFFH E8000H E7FFFH E0000H DFFFFH D8000H D7FFFH D0000H CFFFFH C8000H C7FFFH C0000H BFFFFH B8000H B7FFFH B0000H AFFFFH A8000H
Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block
Bank
Bank
Bank
1FFFFH 18000H 17FFFH 10000H 00FFFFH 008000H 007FFFH
Block Block Block
KWord Sector Protection (Four KWord Sectors)
001000H 000000H
Block
F01.1
FIGURE MEGABIT
©2002 Silicon Storage Technology, Inc.
CONCURRENT SUPERFLASH QUAD-BANK MEMORY ORGANIZATION
S71197-00-000 1/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF3223B SST34HF3243B
VIEW (balls facing down)
BEF1# BEF2#
DQ15 DQ14
DQ13 DQ12 VDDS CIOs VDDF DQ11
BES2
RST# RY/BY# LBS# UBS#
DQ10 BES1#
SST34HF3223B/3243B
F02.2
FIGURE ASSIGNMENTS 56-BALL LFBGA (10MM
12MM)
VIEW (balls facing down)
DQ15 DQ14
DQ13 DQ12 VDDS CIOs VDDF DQ11
BES2 RST# RY/BY# LBS# UBS#
DQ10
BEF# BES1#
SST34HF322x/324x
F03.0
FIGURE ASSIGNMENTS 56-BALL LFBGA (10MM
12MM) APPLY
FUTURE
SST34HF322X/324X
Note: Please refer application note, Design-In SST34HF3223A/3243A/3223B/3243B Devices, achieve dropin replacement when SST34HF322x/324x/328x becomes available.
©2002 Silicon Storage Technology, Inc.
S71197-00-000 1/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF3223B SST34HF3243B
Preliminary Information TABLE DESCRIPTION
Symbol AMS1 Name Address Inputs Address Input (SRAM) Functions provide flash address, A19-A0. provide SRAM address, A16-A0 A17-A0 provide SRAM address input byte mode (x8). When CIOs VIL, SRAM byte mode provides most significant address input. When CIOs VIH, SRAM Word mode becomes "Don't Care" pin. output data during Read cycles receive input data during Write cycles. Data internally latched during flash Erase/Program cycle. outputs tri-state when high BES1# high/BES2 low, BEF# (BEF1# BEF2#) high. activate flash memory bank when BEF1# activate flash memory bank when BEF2# activate SRAM memory bank when BES1# activate SRAM memory bank when BES2 high gate data output buffers control Write operations
DQ15DQ0 BEF1# BEF2# BES1# BES2 UBS# LBS# CIOs RST# RY/BY#
Data Inputs/Outputs
Flash Memory Bank Enable Flash Memory Bank Enable SRAM Memory Bank Enable SRAM Memory Bank Enable Output Enable Write Enable
Upper Byte Control (SRAM) enable DQ15-DQ8 Lower Byte Control (SRAM) enable DQ7-DQ0 Configuration (SRAM) Write Protect Reset Ready/Busy# CIOs Word mode (x16), CIOs Byte mode (x8) protect unprotect sectors from Erase Program operation (for Bank only) Reset return device Read mode output status Program Erase operation (for Bank only). RY/BY# open drain output, 10K-100K pull-up resistor required allow RY/BY# transition high indicating device ready read. Power Supply flash only (2.7-3.3V) Power Supply SRAM only (2.7-3.3V) Unconnected pins
T2.3
Ground Power Supply (flash) Power Supply (SRAM) Connection
VDDF VDDS
Most Significant Address
©2002 Silicon Storage Technology, Inc.
S71197-00-000 1/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF3223B SST34HF3243B
Preliminary Information TABLE OPERATIONAL MODES SELECTION
Mode Flash Read Flash Write Flash Erase SRAM Read BEF#1 BES1# BES22 SRAM Write Full Standby Output Disable Product Identification Software Mode Manufacturer's Device
T3.0
CIOs3
LBS#
UBS#
DQ7-0 DOUT DOUT HIGH-Z DOUT DOUT HIGH-Z HIGH-Z HIGH-Z HIGH-Z
DQ15-8 DOUT DOUT DOUT HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z
BEF# BEF1# operations that apply flash Bank BEF# BEF2# operations that apply flash Bank apply BEF# VIL, BES1# BES2 same time SRAM configuration input CIOs; (Word mode), (Byte mode) VIH, other value. With A19-A1 Manufacturer's 00BFH, read with SST34HF3223B Device 2761H, read with SST34HF3243B Device 2761H, read with
©2002 Silicon Storage Technology, Inc.
S71197-00-000 1/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF3223B SST34HF3243B
Preliminary Information TABLE SOFTWARE COMMAND SEQUENCE
Command Sequence Word-Program Sector-Erase Block-Erase Chip-Erase Software Entry5 Software Exit5,6
Write Cycle Addr1 5555H 5555H 5555H 5555H 5555H 5555H Data2
Write Cycle Addr1 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH Data2
Write Cycle Addr1 5555H 5555H 5555H 5555H 5555H 5555H Data2
Write Cycle Addr1 5555H 5555H 5555H Data2 Data
Write Cycle Addr1 2AAAH 2AAAH 2AAAH Data2
Write Cycle Addr1 SAX4 BAX4 5555H Data2
T4.2
Address format A14-A0 (Hex), Address A19-A15 VIH, other value, Command sequence. DQ15-DQ8 VIH, other value, Command sequence. Program Word address. Sector-Erase; uses A19-A11 address lines. Block-Erase; uses A19-A15 address lines. device does remain Software Product Identification Mode powered down. Manufacturer's 00BFH, read with With A20-A1 SST34HF3223B/3243B Device 2761H, read with
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" cause permanent damage device. This stress rating only functional operation device these conditions conditions greater than those defined operational sections this data sheet implied. Exposure absolute maximum stress rating conditions affect device reliability.) Operating Temperature -20°C +85°C Storage Temperature -65°C +125°C Voltage Ground Potential -0.5V 0.3V Transient Voltage (<20 Ground Potential -1.0V 1.0V Package Power Dissipation Capability 25°C) 1.0W Output Short Circuit Current OPERATING RANGE
Range Commercial Extended Ambient Temp +70°C -20°C +85°C 2.7-3.3V 2.7-3.3V
CONDITIONS
TEST
Input Rise/Fall Time Output Load Figures
©2002 Silicon Storage Technology, Inc.
S71197-00-000 1/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF3223B SST34HF3243B
Preliminary Information TABLE OPERATING CHARACTERISTICS (VDD1 2.7-3.3V)
Limits Symbol Parameter Active Current Read Flash SRAM Concurrent Operation Write2 Flash SRAM VILC VIHC VOLF VOHF VOLS VOHS Standby Current Input Leakage Current Output Leakage Current Input Voltage Input Voltage (CMOS) Input High Voltage Input High Voltage (CMOS) Flash Output Voltage Flash Output High Voltage SRAM Output Voltage SRAM Output High Voltage VDD-0.3 3.0V 3.3V Units Test Conditions Address input VIL/VIH, f=1/TRC Min, VDD=VDD Max, open IOL=100 VDD=VDD IOH=-100 VDD=VDD IOL=1 VDD=VDD IOH=-500 VDD=VDD
T5.4
OE#=VIL, WE#=VIH BEF#=VIL, BES1#=VIH BES2 BEF#=VIH, BES1#=VIL, BES2 BEF#=VIH, BES#=VIL WE#=VIL BEF#=VIL, BES1#=VIH BES2 VIL, OE#=VIH BEF#=VIH, BES1#=VIL, BES2 Max, BEF#=BES1#=VIHC BES2 VILC VIN=GND VDD, VDD=VDD VOUT=GND VDD, VDD=VDD VDD=VDD VDD=VDD
VDD-0.2
VDDF VDDS active while Erase Program progress. Note: BEF# BEF1# operations that apply flash Bank BEF2# operations that apply flash Bank
©2002 Silicon Storage Technology, Inc.
S71197-00-000 1/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF3223B SST34HF3243B
Preliminary Information TABLE RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol TPU-READ TPU-WRITE Parameter Power-up Read Operation Power-up Write Operation Minimum Units
T6.0
TABLE CAPACITANCE
Parameter CI/O1
25°C, Mhz, other pins open)
Description Capacitance Input Capacitance
Test Condition VI/O
Maximum
T7.0
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE FLASH RELIABILITY CHARACTERISTICS
Symbol NEND1 TDR1 ILTH1 Parameter Endurance Data Retention Latch Minimum Specification 10,000 Units Cycles Years Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard
T8.0
This parameter measured only initial qualification after design process change that could affect this parameter.
©2002 Silicon Storage Technology, Inc.
S71197-00-000 1/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF3223B SST34HF3243B
CHARACTERISTICS
TABLE SRAM READ CYCLE TIMING PARAMETERS
SST34HF3223B/3243B-70 Symbol TRCS TAAS TBES TOES TBYES TBLZS
SST34HF3223B/3243B-90 Units
T9.0
Parameter Read Cycle Time Address Access Time Bank Enable Access Time Output Enable Access Time UBS#, LBS# Access Time Bank Enable Active Output Output Enable Active Output UBS#, LBS# Active Output Bank Enable High-Z Output Output Disable High-Z Output UBS#, LBS# High-Z Output Output Hold from Address Change
TOLZS1 TBYLZS1 TBHZS1 TOHZS TOHS
TBYHZS1
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE SRAM WRITE CYCLE TIMING PARAMETERS
SST34HF3223B/3243B-70 Symbol TWCS TBWS TAWS TASTS TWPS TWRS TBYWS TODWS TOEWS TDSS TDHS Parameter Write Cycle Time Bank Enable End-of-Write Address Valid End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time UBS#, LBS# End-of-Write Output Disable from Output Enable from High Data Set-up Time Data Hold from Write Time SST34HF3223B/3243B-90 Units
T10.0
©2002 Silicon Storage Technology, Inc.
S71197-00-000 1/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF3223B SST34HF3243B
Preliminary Information TABLE FLASH READ CYCLE TIMING PARAMETERS 2.7-3.3V
SST34HF3223B/3243B-70 Symbol TCLZ1 TOLZ1 TCHZ TOH1 TRP1 TRHR1 TRY1,2
SST34HF3223B/3243B-90 Units
T11.6
Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time Active Output Active Output High High-Z Output High High-Z Output Output Hold from Address Change RST# Pulse Width RST# High before Read RST# Read Mode
TOHZ1
This parameter measured only initial qualification after design process change that could affect this parameter. This parameter applies Sector-Erase, Block-Erase, Program operations. This parameter does apply Chip-Erase.
TABLE FLASH PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol TOES TOEH TWPH1 TCPH1 TDH1 TIDA1 TSCE TBY1,3 TBR1 Parameter Word-Program Time Address Setup Time Address Hold Time Setup Time Hold Time High Setup Time High Hold Time Pulse Width Pulse Width Pulse Width High Pulse Width High Data Setup Time Data Hold Time Software Access Exit Time Sector-Erase Block-Erase Chip-Erase2 RY/BY# Delay Time Recovery Time Units
T12.6
This parameter measured only initial qualification after design process change that could affect this parameter. Chip-Erase operation needs done each individual bank (BEF1# BEF2#). This parameter applies Sector-Erase, Block-Erase, Program operations. This parameter does apply Chip-Erase.
©2002 Silicon Storage Technology, Inc.
S71197-00-000 1/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF3223B SST34HF3243B
TRCS ADDRESSES AMSS-0 TAAS BES1# TBES TOHS
BES2
TBES TBLZS TBHZS TOES TOLZS TBYES TOHZS
UBS#, LBS# TBYLZS DQ15-0 DATA VALID
F04.0
TBYHZS
AMSS Most Significant SRAM Address
FIGURE SRAM READ CYCLE TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71197-00-000 1/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF3223B SST34HF3243B
TWCS ADDRESSES AMSS-0 TASTS TWPS TWRS
TAWS TBWS BES1#
BES2
TBWS
TBYWS UBS#, LBS# TODWS TOEWS TDSS TDHS NOTE
DQ15-8, DQ7-0
NOTE
VALID DATA
F05.0
Notes: High during Write cycle, outputs will remain high impedance. BES1# goes BES2 goes High coincident with after goes Low, output will remain high impedance. BES1# goes High BES2 goes coincident with before goes High, output will remain high impedance. Because signals output state this time, input signals reverse polarity must applied.
FIGURE SRAM WRITE CYCLE TIMING DIAGRAM (WE# CONTROLLED)1
©2002 Silicon Storage Technology, Inc.
S71197-00-000 1/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF3223B SST34HF3243B
TWCS ADDRESSES AMSS-0 TWPS TWRS
TBWS BES1#
BES2
TBWS TAWS TASTS TBYWS
UBS#, LBS# TDSS DQ15-8, DQ7-0 TDHS
NOTE
VALID DATA
NOTE
F06.0
Notes: High during Write cycle, outputs will remain high impedance. Because signals output state this time, input signals reverse polarity must applied.
FIGURE SRAM WRITE CYCLE TIMING DIAGRAM (UBS#, LBS# CONTROLLED)1
©2002 Silicon Storage Technology, Inc.
S71197-00-000 1/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF3223B SST34HF3243B
ADDRESS A19-0 BEF# TCLZ HIGH-Z DQ15-0 DATA VALID TOLZ
TOHZ
TCHZ HIGH-Z DATA VALID
F07.0
FIGURE FLASH READ CYCLE TIMING DIAGRAM
ADDRESS A19-0 5555 TWPH 2AAA 5555 ADDR
BEF# RY/BY#
DQ15-0
XXAA XX55 XXA0 DATA WORD (ADDR/DATA) Note: VIH, other value. VALID
F32.1
FIGURE FLASH CONTROLLED WORD-PROGRAM CYCLE TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71197-00-000 1/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF3223B SST34HF3243B
ADDRESS A19-0 5555 BEF# TCPH 2AAA 5555 ADDR
RY/BY# DQ15-0
XXAA
XX55
XXA0
DATA WORD (ADDR/DATA)
VALID
F33.1
Note: VIH, other value.
FIGURE FLASH BEF# CONTROLLED WORD-PROGRAM CYCLE TIMING DIAGRAM
ADDRESS A19-0 BEF# TOEH DATA# DATA# VALID DATA
F34.0
TOES
FIGURE FLASH DATA# POLLING TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71197-00-000 1/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF3223B SST34HF3243B
ADDRESS A19-0 BEF# TOEH
READ CYCLES WITH SAME OUTPUTS VALID DATA
F35.1
FIGURE FLASH TOGGLE TIMING DIAGRAM
SIX-BYTE CODE CHIP-ERASE ADDRESS A19-0 5555 2AAA 5555 5555 2AAA 5555
TSCE
BEF#
RY/BY# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX10 VALID
F36.2
Note: This device also supports BEF# controlled Chip-Erase operation. BEF# signals interchageable long minimum timings met. (See Table VIH, other value.
FIGURE FLASH CONTROLLED CHIP-ERASE TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71197-00-000 1/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF3223B SST34HF3243B
SIX-BYTE CODE BLOCK-ERASE ADDRESS A19-0 5555 2AAA 5555 5555 2AAA
BEF#
RY/BY#
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX50
VALID
F37.2
Note: This device also supports BEF# controlled Block-Erase operation. BEF# signals interchageable long minimum timings met. (See Table Block Address VIH, other value.
FIGURE FLASH CONTROLLED BLOCK-ERASE TIMING DIAGRAM
SIX-BYTE CODE SECTOR-ERASE ADDRESS A19-0 5555 2AAA 5555 5555 2AAA
BEF#
RY/BY# DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX30
VALID
F38.2
Note: This device also supports BEF# controlled Sector-Erase operation. BEF# signals interchageable long minimum timings met. (See Table Sector Address VIH, other value.
FIGURE FLASH CONTROLLED SECTOR-ERASE TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc. S71197-00-000 1/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF3223B SST34HF3243B
THREE-BYTE SEQUENCE SOFTWARE ENTRY ADDRESS A14-0 5555 2AAA 5555 0000 0001
BEF#
TWPH DQ15-0 XXAA XX55 XX90 00BF
Device
F39.1
TIDA
Device 2761H SST34HF3223B 2761H SST34HF3243B Note: VIH, other value.
FIGURE FLASH SOFTWARE ENTRY
READ
THREE-BYTE SEQUENCE QUERY ENTRY ADDRESS A14-0 5555 2AAA 5555
BEF#
TWPH DQ15-0 XXAA XX55 XX98
F30.1
TIDA
Note: VIH, other value.
FIGURE ENTRY
READ
©2002 Silicon Storage Technology, Inc.
S71197-00-000 1/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF3223B SST34HF3243B
THREE-BYTE SEQUENCE SOFTWARE EXIT RESET
ADDRESS A14-0
5555
2AAA
5555
DQ15-0
XXAA
XX55
XXF0 TIDA
BEF#
TWHP
F15.2
Note: VIH, other value.
FIGURE FLASH SOFTWARE EXIT/CFI EXIT
RY/BY# RST#
BEF#/OE#
F40.1
TRHR
FIGURE RST# TIMING DIAGRAM (WHEN
INTERNAL OPERATION PROGRESS)
©2002 Silicon Storage Technology, Inc.
S71197-00-000 1/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF3223B SST34HF3243B
RY/BY#
RST# BEF#
F41.1
FIGURE RST# TIMING DIAGRAM (DURING SECTOR-
BLOCK-ERASE
OPERATION)
VIHT
INPUT
REFERENCE POINTS
OUTPUT
VILT
F19.0
test inputs driven VIHT (0.9 VDD) logic VILT (0.1 VDD) logic "0". Measurement reference points inputs outputs (0.5 VDD) (0.5 VDD). Input rise fall times (10% 90%)
Note: VINPUT Test VOUTPUT Test VIHT VINPUT HIGH Test VILT VINPUT Test
FIGURE INPUT/OUTPUT REFERENCE WAVEFORMS
TESTER
F20.0
FIGURE TEST LOAD EXAMPLE
©2002 Silicon Storage Technology, Inc.
S71197-00-000 1/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF3223B SST34HF3243B
Start
Load data: XXAAH Address: 5555H
Load data: XX55H Address: 2AAAH
Load data: XXA0H Address: 5555H
Load Word Address/Word Data
Wait Program (TBP, Data# Polling bit, Toggle operation) Program Completed
F21.0
Note: VIH, other value.
FIGURE WORD-PROGRAM ALGORITHM
©2002 Silicon Storage Technology, Inc.
S71197-00-000 1/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF3223B SST34HF3243B
Internal Timer Program/Erase Initiated
Toggle Program/Erase Initiated
Data# Polling Program/Erase Initiated
Wait TBP, TSCE,
Read word
Read
Program/Erase Completed
Read same word
true data?
Does match? Program/Erase Completed
Program/Erase Completed
F22.0
FIGURE WAIT OPTIONS
©2002 Silicon Storage Technology, Inc.
S71197-00-000 1/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF3223B SST34HF3243B
Query Entry Command Sequence
Software Product Entry Command Sequence
Software Exit/CFI Exit Command Sequence
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX98H Address: 5555H
Load data: XX90H Address: 5555H
Load data: XXF0H Address: 5555H
Wait TIDA
Wait TIDA
Wait TIDA
Read data
Read Software
Return normal operation
F23.1
Note: VIH, other value.
FIGURE SOFTWARE PRODUCT ID/CFI COMMAND FLOWCHARTS
©2002 Silicon Storage Technology, Inc.
S71197-00-000 1/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF3223B SST34HF3243B
Chip-Erase Command Sequence Load data: XXAAH Address: 5555H
Sector-Erase Command Sequence Load data: XXAAH Address: 5555H
Block-Erase Command Sequence Load data: XXAAH Address: 5555H
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX80H Address: 5555H
Load data: XX80H Address: 5555H
Load data: XX80H Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX10H Address: 5555H
Load data: XX30H Address:
Load data: XX50H Address:
Wait Options1
Wait Options1
Wait Options1
Chip erased FFFFH
Sector erased FFFFH
Block erased FFFFH
F24.0
Note: VIH, other value.
Refer Figure
FIGURE ERASE COMMAND SEQUENCE
©2002 Silicon Storage Technology, Inc.
S71197-00-000 1/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF3223B SST34HF3243B
PRODUCT ORDERING INFORMATION
Device Speed Suffix1 Suffix2 Package Modifier pins Package Type LFBGA (10mm 12mm 1.4mm) Temperature Range Commercial +70°C Extended -20°C +85°C Minimum Endurance =10,000 cycles Read Access Speed Version Bank Split Mbit (12+4) Mbit (12+4). Total banks. SRAM Density SRAM Mbit Mbit Flash Density Mbit Voltage 2.7-3.3V Device Family SRAM ComboMemory
SST34HF32x3B
Valid combinations SST34HF3223B SST34HF3223B-70-4C-LP SST34HF3223B-90-4C-LP SST34HF3223B-70-4E-LP SST34HF3223B-90-4E-LP Valid combinations SST34HF3243B SST34HF3243B-70-4C-LP SST34HF3243B-90-4C-LP SST34HF3243B-70-4E-LP SST34HF3243B-90-4E-LP
Note: Valid combinations those products mass production will mass production. Consult your sales representative confirm availability valid combinations determine availability combinations.
©2002 Silicon Storage Technology, Inc.
S71197-00-000 1/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF3223B SST34HF3243B
PACKAGING DIAGRAMS
BOTTOM VIEW
12.00 0.20
VIEW
5.60 0.80
0.80 10.00 0.20 5.60
0.45 0.05 (56X)
CORNER
1.30 0.10
CORNER
SIDE VIEW
0.15 SEATING PLANE 0.35 0.05
Note:
Although many dimensions similar those JEDEC Publication MO-210, this specific package registered. linear dimensions millimeters (min/max). Coplanarity: (±.05) actual shape corners slightly different than portrayed drawing.
56-BALL LOW-PROFILE, FINE-PITCH BALL GRID ARRAY (LFBGA) 10MM PACKAGE CODE:
12MM POSSIBLE
BALL POSITIONS)
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.sst.com
©2002 Silicon Storage Technology, Inc. S71197-00-000 1/02
Other recent searches
V602ME04 - V602ME04 V602ME04 Datasheet
SPC563M64 - SPC563M64 SPC563M64 Datasheet
MJ10005 - MJ10005 MJ10005 Datasheet
FS30KMJ-06 - FS30KMJ-06 FS30KMJ-06 Datasheet
FJX2907A - FJX2907A FJX2907A Datasheet
AMTNE08008 - AMTNE08008 AMTNE08008 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
