Preliminary Data Sheet December 2001 Packaging options: 44-lead d

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Preliminary Data Sheet December 2001 Packaging options: 44-lead d

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QCOTSUT8Q1024K8 SRAM
Preliminary Data Sheet December 2001
Packaging options: 44-lead dual cavity ceramic flatpack Standard Microcircuit Drawing 5962-01532 compliant part
input/output pins placed high impedance state when device deselected HIGH), outputs disabled HIGH), during write operation LOW).
A(18:0) 512K
DQ(7:0)
Immune >100 MeV-cm2 LETTH (0.25) MeV-cm2 Saturated Cross Section bit, 1.0E-9 <1E-10 errors/bit-day, Adams geosynchronous heavy
Writing each memory accomplished taking chip enable (En) inputs write enable (Wn) inputs LOW. Data pins then written into location specified address pins through Reading from device accomplished taking ofthe chip enable (En) output enable while forcing write enable (Wn) HIGH. Under these conditions, contents memory location specified address pins will appear pins. Only SRAM read written time.
512K
Figure UT8Q1024K8 SRAM Block Diagram
FEATURES 25ns maximum (3.3 volt supply) address access time Dual cavity package contains 512K industrystandard asynchronous SRAMs; control architecture allows operation 8-bit data width compatible inputs output levels, three-state bidirectional data Typical radiation performance Total dose: 50krad(Si)
INTRODUCTION QCOTS UT8Q1024K8 Quantified Commercial Off-theShelf product high-performance byte (8Mbit) CMOS static built with individual 524,288 SRAMs with common output enable. Memory access control provided active chip enable (En), active output enable (G). This device power-down feature that reduces power consumption more than when deselected.
DEVICE OPERATION
Table Device Operation Truth Table
Figure 25ns SRAM Pinout (44)
A(18:0) DQ(7:0)
Address Data Input/Output Device Enable WriteEnable
Output Enable Power
Ground
Notes: avoid contention, DQ(7:0) bus, only driven simultaneously while low.
NAMES
Notes: defined "don't care" condition. Device active; outputs disabled.
READ CYCLE combination greater than (min) with less than (max) defines read cycle. Read access time measured from latter device enable, output enable, valid address valid data output. SRAM Read Cycle Address Access initiated change address inputs while chip enabled with asserted deasserted. Valid data appears data outputs DQ(7:0) after specified AVQV satisfied. Outputs remain active throughout entire cycle. long device enable output enable active, address inputs change rate equal minimum read cycle time (tAVAV). SRAM Read Cycle Chip Enable-controlled Access initiated going active while remains asserted, remains deasserted, addresses remain stable entire cycle. After specified ETQV satisfied, eight-bit word addressed A(18:0) accessed appears data outputs DQ(7:0). SRAM Read Cycle Output Enable-controlled Access initiated going active while asserted, deasserted, addresses stable. Read access time tGLQV unless tAVQV tETQV have been satisfied.
Mode Mode 3-state Standby Write Read2 Read Data 3-state Data
Each UT8Q1024K8 three control inputs called Enable (En), Write Enable (Wn), Output Enable (G); address inputs, A(18:0); eight bidirectional data lines, DQ(7:0). device enable (En) controls device selection, active, standby modes. Asserting enables device, causes rise active value, decodes address inputs each memory controls read write operations. During read cycle, must asserted enable outputs.
WRITE CYCLE combination less than VIL(max) less than VIL(max) defines write cycle. state "don't care" write cycle. outputs placed high-impedance state when eitherG greater than IH(min), when less than (max). Write Cycle Write Enable-controlled Access defined write terminated going high, with still active. write pulse width defined tWLWH when write initiated byWn, ETWH when write initiated Unless outputs have been previously placed highimpedance state byG, user must wait WLQZ before applying data eight bidirectional pins DQ(7:0) avoid contention. Write Cycle Chip Enable-controlled Access defined write terminated former going inactive. write pulse width defined tWLEF when write initiated ETEF when write initiated going active. initiated write, unless outputs have been previously placed high-impedance state user must wait tWLQZ before applying data eight bidirectional pins DQ(7:0) avoid contention.
TYPICAL RADIATION HARDNESS UT8Q1024K8 SRAM incorporates features which allow operation limited radiation environment. Table Typical Radiation Hardness Design Specifications Total Dose Heavy Error Rate <1E-10 krad(Si) nominal Errors/Bit-Day
Notes: SRAM will latchup during radiation exposure under recommended operating conditions. worst case particle environment, Geosynchronous orbit, mils Aluminum.
ABSOLUTE MAXIMUM RATINGS (Referenced SYMBOL TSTG PARAMETER supply voltage Voltage Storage temperature Maximum power dissipation Maximum junction temperature2 Thermal resistance, junction-to-case3 input current LIMITS -0.5 4.6V -0.5 4.6V +150°C 1.0W (per byte) +150°C 10°C/W
RECOMMENDED OPERATING CONDITIONS SYMBOL
PARAMETER Positive supply voltage Case temperature range input voltage
Notes: Stresses outside listed absolute maximum ratings cause permanent damage device. This stress rating only, functional operation device these other conditions beyond limits indicated operational sections this specification recommended. Exposure absolute maximum rating conditions extended periods affect device reliability performance. Maximum junction temperature increased +175 during burn-in steady-static life. Test MIL-STD-883, Method 1012.
LIMITS
3.6V
+125°C
ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)* (-40°C +125°C) 3.3V 0.3) SYMBOL VOH1 VOH2 PARAMETER High-level input voltage Low-level input voltage Low-level output voltage Low-level output voltage High-level output voltage High-level output voltage Input capacitance Bidirectional capacitance Input leakage current Three-state output leakage current (CMOS) (CMOS) 8mA, =3.0V 200µA,VDD =3.0V -4mA,VDD =3.0V -200µA,VDD =3.0V 1MHz 1MHz (max) (max) (max) (OP) Short-circuit output current Supply current operating 1MHz DD-0.10 CONDITION 0.08 UNIT
-40°C 25°C +125°C
Inputs: 0.8V, 2.0V IOUT (max)
DD1(OP)
Supply current operating @40MHz
IDD2 (SB)
Nominal standby supply current @0MHz
Notes: Post-radiation performance guaranteed 25°C MIL-STD-883 Method Measured only initial qualification after process design changes that could affect input/output capacitance. Supplied design limit guaranteed tested. more than output shorted time maximum duration second.
2.0V IOUT Inputs: IOUT 0.5,
Inputs: 0.8V,
(max)
(max) 0.5V
CHARACTERISTICS READ CYCLE (Pre/Post-Radiation)* (-40°C +125°C) 3.3V 0.3) SYMBOL tAVAV tAVQV tAXQX tGLQX tGLQV tGHQZ tETQX2,3 tETQV3 tEFQZ1,2,4 Read cycle time Read access time Output hold time G-controlled Output Enable time G-controlled Output Enable time (Read Cycle G-controlled output three-state time En-controlled Output Enable time En-controlled access time En-controlled output three-state time PARAMETER UNIT
High Active Levels
Notes: Post-radiation performance guaranteed 25°C MIL-STD-883 Method 1019. Functional test. Three-state defined 300mV change from steady-state output voltage. (enable true) notation refers falling edge immunity does affect read parameters. (enable false) notation refers rising edge immunity does affect read parameters.
Active High Levels
300mV 300mV
VLOAD VLOAD 300mV
Figure 3-Volt SRAM Loading
VLOAD 300mV
tAVAV A(18:0)
DQ(7:0)
Previous Valid Data
Valid Data tAVQV
Assumptions: andG (max) (min)
tAXQX Figure SRAM Read Cycle Address Access
A(18:0) ETQV DQ(7:0) tETQX tEFQZ
Figure SRAM Read Cycle Chip Enable-Controlled Access
A(18:0)
AVQV
tGLQV
Assumptions: (max) (min)
tGLQX
DATA VALID
DQ(7:0)
Assumptions: (max) andW (min)
Figure SRAM Read Cycle Output Enable-Controlled Access
DATA VALID
tGHQZ
CHARACTERISTICS WRITE CYCLE (Pre/Post-Radiation)* (-40°C +125°C) 3.3V 0.3) SYMBOL tAVAV tETWH tAVET tAVWL tWLWH tWHAX tEFAX tWLQZ tWHQX tETEF tDVWH tWHDX tWLEF tDVEF tEFDX tAVWH tWHWL1 Write cycle time Device Enable write Address setup time write controlled) Address setup time write controlled) Write pulse width Address hold time write controlled) Address hold time Device Enable controlled) controlled three-state time controlled Output Enable time Device Enable pulse width controlled) Data setup time Data hold time PARAMETER UNIT
Device Enable controlled write pulse width Data setup time Data hold time Address valid write Write disable time
Notes Post-radiation performance guaranteed MIL-STD-883 Method 1019. Functional test performed with outputs disabled high). Three-state defined 300mV change from steady-state output voltage.
A(18:0) AVAV2 tAVWH ETWH tAVWL Q(7:0) tWLQZ D(7:0)
Assumptions: (max). (min) then Qn(8:0) will three-state entire cycle. high AVAV cycle. APPLIED DATA
WHWL tWHAX
WLWH
tWHQX
Figure SRAM Write Cycle Write Enable Controlled Access
tDVWH
tWHDX
tAVAV A(18:0) tAVET ETEF EFAX
tAVET WLEF
APPLIED DATA
ETEF tEFAX
D(7:0)
WLQZ Q(7:0)
Figure SRAM Write Cycle Chip Enable Controlled Access
CMOS DD-0.05V 0.5V
Assumptions Notes: (max). (min) then Q(7:0) will three-state entire cycle. Either scenario above occur. high AVAV cycle.
Input Pulses
DVEF
tEFDX
ohms
LOAD 1.55
50pF
Notes: 50pF including scope probe test socket capacitance. Measurement data output occurs high high transition mid-point (i.e., CMOS input DD/2).
Figure Test Loads Input Waveforms
DATA RETENTION MODE
2.0V
Figure Data Retention Waveform
MINIMUM
DATA RETENTION CHARACTERISTICS (Pre/Post-Irradiation) Second Data Retention Test) SYMBOL PARAMETER tEFR tR1,3 data retention Data retention current (per byte) Chip select data retention time Operation recovery time
MAXIMUM -2.0
UNIT
Data retention current 25oC. guaranteed tested.
DATA RETENTION CHARACTERISTICS (Pre/Post-Irradiation) SYMBOL tEFR2, tR2,
PARAMETER
Second Data Retention Test, TC=-40oC +125oC) data retention
MINIMUM tAVAV MAXIMUM
Notes: .2V, other inputs
tAVAV
UNIT
Chip select data retention time
Notes: Performed (min) (max). other inputs guaranteed tested.
Operation recovery time
PACKAGING
exposed metalized areas must plated MIL-PRF-38535. electrically connected Index mark configuration optional.
Figure 44-lead dual cavity ceramic flatpack package
ORDERING INFORMATION 1024K8 SRAM:
UT8Q1024K8
Lead Finish: solder dipped (contact factory availability) Gold Factory option (gold solder)
Screening: Military Temperature Range flow Prototype flow Extended Industrial Temperature Range Flow (-40o +125o
Package Type: 44-lead dual cavity CQFP
Aeroflex UTMC Core Part Number
Notes: Lead finish (A,C, must specified. specified when ordering, then part marking will match lead finish will either (solder) old). Prototype flow UTMC Manufacturing Flows Document. Tested only. Lead finish GOLD ONLY. Radiation neither tested guaranteed. Military Temperature Range flow UTMC Manufacturing Flows Document. Devices tested room temp, +125 Radiation neither tested guaranteed. Extended Industrial Temperature Range flow UTMC Manufacturing Flows Document. Devices tested -40°C +125°C. Radiation neither tested guaranteed. Gold Lead Finish Only.
Device Type: 25ns access, 3.3V operation
1024K8 SRAM:
5962 01532
Lead Finish: solder dipped (Contact factory availability) Gold Factory Option (gold solder) Case Outline: 44-lead dual cavity CQFP Class Designator: Class Class
Device Type 25ns access time, 3.3V operation, Mil-Temp 25ns access time, 3.3V operation, Extended Industrial Temp (-40oC +125 Drawing Number: 01532 Total Dose (10krad(Si)) (30krad(Si)) (contact factory) (50krad(Si)) (contact factory) Federal Stock Class Designator: Options
Notes: Lead finish must specified. specified when ordering, part marking will match lead finish will either (solder) (gold). Total dose radiation must specified when ordering. available without radiation hardening.

Preliminary Data Sheet December 2001 Packaging options: 44-lead d

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