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Clock Systems October 2001-1 GENERAL DESCRIPTION XRT8001 Clo


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XRT8001
Clock Systems
October 2001-1
GENERAL DESCRIPTION XRT8001 Clock dual-phase-locked loop chip that generates very jitter output clock signals that used synchronization clocks wide area networking systems. XRT8001 preprogrammed multipliers dividers that selected serial port. generates integer multiples 8kHz, 56kHz, 64kHz while locked onto incoming reference 1.54MHz (T1), 2.048MHz (E1), 8kHz, 56kHz, 64kHz XRT8001 Clock configured operate modes: Forward/Master Mode Reverse/Master Mode "Fractional T1/E1" Reverse/Master Mode Forward/Master" Mode "High Speed Reverse" Mode "Slave" Mode FEATURES
Generates Output Clock Frequencies Ranging
From 8kHz 16.384MHz Serial Port Control Optimal Performance Sync Output: 8kHz 64kHz Jitter Cascadable (Master Slave Modes) External Components Needed Compatible with XRT8000 Power (3.3V 5V): 100mW 40°C +85°C Temperature Range 18-Lead PDIP SOIC Packages
APPLICATIONS
Dual Phased Locked Loops with
Pre-Programmed Multipliers Dividers
Pre-Programmed with Popular Frequency
Conversions Communications Systems
3.3V
T1/E1 Access Equipment (DSU/CSU) Frame Relay Access Devices (FRAD) Basic Rate Primary Rate ISDN Equipment ISDN Routers Terminals Remote Access Servers T1/E1 Concentrators T1/E1 Multiplexers T1/E1 Clock Rate Converters Internal Timing Generators System Synchronizers
Reference Clock
8kHz 16.384
XRT8001
CLK1 CLK2
Clock Output Clock Output Lock Detect
Sync
8kHz 64kHz Master/Slave
SYNC
LOCKDET
SCLK
Serial
Figure System Diagram ORDERING INFORMATION
Part Number XRT8001IP XRT8001ID Package 18-Lead PDIP 18-Lead JEDEC SOIC Operating Temperature Range -40°C +85°C -40°C +85°C
Rev. 1.01
EXAR Corporation, 48720 Kato Road, Fremont, 94538 (510) 668-7000 (510) 668-7017 www.exar.com
XRT8001
Analog Digital Digital Digital
Analog Phase Locked Loop
Post Divider
Driver
CLK2
Feedback Divider
PLL2
LDETDIS1 LDETDIS2 Lock Detector
LOCKDET
SYNC
Input Divider
Analog Phase Locked Loop
Post Divider
Driver
CLK1
Feedback Divider 100K
PLL1
100K
SCLK
AGND DGND DGND DGND Serial Interface Mode Frequency Select Control
Figure XRT8001 Block Diagram
Rev. 1.01
XRT8001
SYNC CLK1 SCLK
XRT8001
CLK2 LOCKDET
Figure XRT8001
DESCRIPTION
Name Type Description Serial Data Output from Microprocessor Serial Interface This will serially output contents specified Command Register, during "Read" Operations. data, this pin, will updated falling edge SCLK input signal. This will tristated upon completion data transfer. Sync Output XRT8001 will typically output 8kHz clock signal this output pin. However, when XRT8001 operating "High Speed Reverse" Mode, then this device will simply output 64kHz clock signal. Reference Clock Input Reference Timing signal (from which CLK1 CLK2 output signals derived) input this pin. Digital Ground Digital Ground Clock Output XRT8001 will drive desired "synthesized" signal this output pin. This output signal will have 50+5% duty cycle. Note: This output tri-stated unless "CLK1EN" bit-field (within Command Register CR4) been "1". Digital Power Supply
SYNC
CLK1
Rev. 1.01
XRT8001
DESCRIPTION (CONT'D)
Name Type Description Master/Slave Mode Select Input Setting this input "HIGH" configures XRT8001 operate "MASTER" Mode. Conversely, setting this input "LOW" configures XRT8001 operate "SLAVE" Mode. Analog Ground Analog Power Supply Lock Detect Output This output indicates whether "selected" internal PLL(s) "in-lock" "out-of-lock". default, this output "high" when both PLLs in-lock" will toggle "low" either PLLs "out-of-lock". However, XRT8001 also permits user configure this output reflect state PLLs within chip. (See Table CLK2 Digital Power Supply Clock Output XRT8001 will drive desired "synthesized" signal this output pin. This output signal will have 50+5% duty cycle. Note: This output tri-stated unless "CLK1EN" bit-field (within Command Register CR4) been "1". Digital Ground Digital Power Supply Microprocessor Serial Interface Serial Data Input Whenever, user wishes read write data into Command Registers, over Microprocessor Serial Interface, user expected apply "Read/Write" bit, Address Values Command Registers) Data Value written (during "Write" Operations) this pin. This input will sampled rising edge SCLK (pin 18). Microprocessor Serial Interface Chip Select Input: Local Microprocessor must assert this (e.g., "0") order enable communication with XRT8001 Microprocessor Serial Interface. Note: This internally pulled "high". SCLK Microprocessor Serial Interface-Clock Signal This signal will used sample data, pin, rising edge this signal. Additionally, during "Read" operations, Microprocessor Serial Interface will update output falling edge this signal.
LOCKDET
Rev. 1.01
XRT8001
ABSOLUTE MAXIMUM RATINGS Supply Range Voltage -0.3V Vcc+0.3V Operating Temperature. 40°C +85°C Storage Temperature 40°C +85°C Package Dissipation 500mW
ELECTRICAL CHARACTERISTICS (Except Microprocessor Serial Interface)1
Symbol Parameter Input Level Input High Level Output Level (CLK1, CLK2) Output High Level (CLK1, CLK2) Output Level (LOCKDET, SYNC) Output High Level (LOCKDET, SYNC) Input Current (CSB, MSB) Input High Current (CSB, MSB) Input Current (except CSB, MSB) Input High Current (except CSB, MSB) Operating Current Internal Pull-up Resistance (CSB, MSB) -150 Min. Typ. Max. Units
3.3V, Load, CLk1, CLK2 2.048MHz Load, CLk1, CLK2 2.048MHz
Condition
-6.0mA 6.0mA -3.0mA 3.0mA
Note: tolerant input considerations when operating from 3.3V:
When XRT8001 powered 3.3V, tolerate 5V-level signals inputs. However, user should aware XRT8001 contains "Factory-Test" Mode. This mode enabled whenever (Master-Slave select) input pulled about above VDD. Therefore, user powering XRT8001 3.3V applying 5.25V signal input pin, then possible that XRT8001 could configured operate this "Factory-Test" Mode. Since "Factory-Test" Mode registers reset "0", upon chip power, this should problem user. However, user performs write operations "non-defined" address locations within XRT8001, then user observe strange operation from XRT8001. user must make sure that when Microcontroller performs WRITE operations XRT8001, only performing these WRITE operations Address Locations defined XRT8001 Data Sheet.
Rev. 1.01
XRT8001
ELECTRICAL CHARACTERISTICS (See Figure
Symbol t112 Parameter Input Frequency Minimum Input Signal "High" "Low" Duration Output Frequency Duty Cycle Jitter Added 8kHz 40kHz Jitter Added 10Hz 40kHz Broadband Jitter Jitter Added 20Hz 100kHz Jitter Added 18kHz 100kHz Capture Time Clock Output Rise Time Clock Output Fall Time SYNC Output Signal Duty Cycle SYNC Ouput Signal Cycle SYNC Output Signal Cycle Delay Time between rising edge SYNC Rising edge CLK1 CLK2 Rising Edge SCLK Setup Time High Rising Edge SCLK Hold Time Rising Edge SCLK Setup Time Rising Edge SCLK Hold Time SCLK "Low" Time SCLK "High" Time SCLK Period Rising Edge SCLK Hold Time "Inactive" Time Falling Edge SCLK Valid Time Falling Edge SCLK Invalid Time Falling Edge SCLK, rising edge High Rise/Fall time Output Duty Cycle
Min. 0.008 0.008 47.5
Typ.
Max. Units 32.7 32.7 3.3V
Conditions
0.01 0.01 0.03 0.03 0.03 0.035
16,384 52.5 0.02 0.02
0.05 0.05 0.07 0.01 0.07 0.03 0.007 0.03 10ns 10ns
VCC/2 switch point, 30pF Load 3.3V, Output 1.544MHz (0.025 UI)3 Output 1.544MHz (0.025 UI)3 3.3V, Output 1.544MHz (0.025 UI)3 Output 1.544MHz (0.025 UI)3 3.3V, Output 1.544MHz (0.05 UI)3 Output 1.544MHz (0.05 UI)3 3.3V, Output 2.048MHz (1.5 UI)3 Output 2.048MHz (1.5 UI)3 3.3V, Output 2.048MHz (0.2 UI)3 Output 2.048MHz (0.2 UI)3 3.3V 30pF load measured 20/80% 30pF load measured 20/80% VCC/2 switch point
t-20
t+20
Table values
PWMIN Notes:
(t12 t13)
Specifications from AT&T Publication 62411 ITU-T Recommendations G-823 (for 1.544MHz (2.048MHz). guaranteed characterization, tested.
Rev. 1.01
XRT8001
CLK1 CLK2
SYNC
Figure Timing Diagram Clocks
SCLK
SCLK
Hi-Z
Hi-Z
Figure Timing Diagram Microprocessor Serial Interface
Rev. 1.01
XRT8001
Operating Microprocessor Serial Interface XRT8001 Serial Interface simple four-wire interface that compatible with many microcontrollers available market. This interface consists following signals: SCLK Chip Select (Active Low) Serial Clock Serial Data Input Serial Data Output Bits Through Four Address Values (Labeled next four rising edges SCLK signal will clock 4-bit address value this particular Read Write) operation. address selects Command Register, within XRT8001, that user will either reading data from, writing data user must supply address bits input ascending order with (least significant bit) first. Bits next bits, must "0", shown Figure value "A6" "don't care". Once these first eight bits have been written into Microprocessor Serial Interface, subsequent action depends upon whether current operation "Read" "Write" operation. Read Operation Once last address (A3) been clocked into input, "Read" operation will proceed through idle period, lasting three SCLK periods. falling edge SCLK Cycle (see Figure serial data output signal (SDO) becomes active. this point user begin reading data contents addressed Command Register Address [A3, A0]) output pin. Microprocessor Serial Interface will output this 5-bit data word through ascending order (with first), falling edges SCLK pin. consequence, data output pin) will sufficiently stable reading Microprocessor), very next rising edge SCLK pin.
Using Microprocessor Serial Interface following instructions, using Microprocessor Serial Interface, best understood referring diagram Figure order Microprocessor Serial Interface user must first provide clock signal SCLK input pin. Afterwards, user will initiate "Read" "Write" operation asserting "activelow" Chip Select input (CSB). important assert (e.g., toggle "low") least 50ns prior very first rising edge clock signal. Once input been asserted, type operation target register address must specified user. user provides this information Microprocessor Serial Interface writing eight serial bits data into input. Note: each these bits will "clocked" into input rising edge SCLK. These eight bits identified described below. "R/W" (Read/Write) This will clocked into input first rising edge SCLK (after been asserted). This indicates whether current operation "Read" "Write" operation. this specifies "Read" operation; whereas, this specifies "Write" operation.
Rev. 1.01
XRT8001
Write Operation Once last address (A3) been clocked into input, "Write" operation will proceed through idle period, lasting three SCLK periods. Prior rising edge SCLK Cycle (see Figure user must begin apply 8-bit data word, that he/she wishes write Microprocessor Serial Interface, onto input pin. Microprocessor Serial Interface will latch value input pin, rising edge SCLK. user must apply this word through serially, ascending order with first.
SCLK
High
Notes: always "0". "Read" Operations "Write" Operations Denotes "don't care" value
Figure Microprocessor Serial Interface Data Structure
Simplified Interface Option user simplify design circuitry connecting Microprocessor Serial Interface tying both pins together, reading data from and/or writing data this "combined" signal. This simplification possible because only these signals active given time. inactive signal will tri-stated.
Rev. 1.01
XRT8001
Forward/Master Mode Forward/Master Mode, XRT8001 will accept either 1.544MHz" 2.048MHz" clock signal input (where: 16). From this "reference signal" XRT8001 will generate either 56kHz" 64kHz" clock signal (where: 32). Figure presents simple illustration XRT8001 Clock operating "Forward Master/Mode."
1.544MHz 2.048MHz Where
CLK1
56kHz 64kHz Where
XRT8001 Clock
XRT8001 Clock
CLK2
56kHz 64kHz Where
Figure Illustration XRT8001 Clock Operating Forward/Master Mode
Rev. 1.01
XRT8001
Reverse/Master Mode Reverse/Master Mode, XRT8001 will accept either 56kHz 64kHz clock signal input pin, will generate either 1.544MHz 2.048MHz clock signal Clock Output signals. Figure presents simple illustration XRT8001 Clock operating "Reverse/Master Mode."
56kHz 64kHz
CLK1
1.544MHz 2.048MHz
XRT8001 XRT8001 Clock Clock
CLK2
1.544MHz 2.048MHz
Figure Illustration XRT8001 Clock Operating Reverse/Master Mode
Rev. 1.01
XRT8001
Fractional T1/E1 Reverse/Master Mode Fractional T1/E1 Reverse/Master Mode, XRT8001 will accept either 56kHz" 64kHz" clock signal input (where: 32). From this "reference signal" XRT8001 will generate either 1.544MHz 2.048MHz clock signal. Figure presents simple illustration XRT8001 Clock operating "Fractional T1/E1 Reverse/Master" Mode.
56kHz 64kHz Where:
CLK1
1.544MHz 2.048MHz
XRT8001 XRT8001 Clock Clock
CLK2
1.544MHz 2.048MHz
Figure Illustration XRT8001 Clock Operating "Fractional T1/E1 Reverse/Master" Mode
Rev. 1.01
XRT8001
Forward/Master" Mode Forward/Master" Mode, XRT8001 will accept 2.048MHz" clock signal "Reference Clock Input" (FIN), will output "1.544MHz" clock signal CLK1 and/or CLK2 output pins.
Note: value range between
Figure presents simple illustration XRT8001 Clock operating Forward/Master" Mode.
2.048MHz Where:
CLK1
1.544MHz
XRT8001 XRT8001 Clock
CLK2
1.544MHz
Figure Illustration XRT8001 Clock Operating Forward/Master" Mode
Rev. 1.01
XRT8001
"High Speed Reverse" Mode "High Speed Reverse" Mode, XRT8001 will accept 64kHz clock signal "Reference Clock Input" (FIN), will output 2.048MHz" clock signal (where equal CLK1 and/or CLK2 output pins.
Note: XRT8001 will accept sythesze these clock frequencies independent whether been configured operate "Master" "Slave" Modes.
Figure presents simple illustration XRT8001 Clock operating "High Speed Reverse" Mode.
64kHz
CLK1
2.048MHz
XRT8001 Clock
2.048MHz CLK2
Figure Illustration XRT8001 Clock Operating "High Speed Reverse" Mode
Rev. 1.01
XRT8001
"Forward/Slave" Mode "Forward/Slave" Mode, XRT8001 will accept 8kHz clock signal Reference Clock Input (FIN), will output 64kHz 56kHz" clock signal (where range from CLK1 CLK2 output pins. Figure presents simple illustration XRT8001 Clock operating "Forward/ Slave" Mode.
8kHz
CLK1
56kHz 64kHz Where
XRT8001 Clock
CLK2
56kHz 64kHz Where
Figure Illustration XRT8001 Clock Operating "Forward/Slave" Mode
Rev. 1.01
XRT8001
Description Command Registers Address "On-Chip" Command Registers
Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07
Command Register
Type
IOC4 SEL14 SEL24 SYNCEN Reserved Reserved Reserved
IOC3 SEL13 SEL23 CLK1EN Reserved Reserved Reserved
Register Bit-Format IOC2 SEL12 SEL22 CLK2EN Reserved Reserved Reserved
IOC1 SEL11 SEL21 LDETDIS2 Reserved Reserved Reserved
PL1EN PL2EN SEL10 SEL20 LDETDIS1 Reserved Reserved Reserved
Command Register Description
3.2.1 Command Register (Address 0x00)
(Configuration Mode Select Bits) These four-bit fields permit user select which mode XRT8001 will operate Specifically, these four bit-fields make following configuration selections: Whether XRT8001 will operating "Forward/Master", "Reverse/Master", "Fractional T1/E1 Reverse/Master", Forward/Master" "High Speed Reverse" odes. What kind input signals applied Reference Clock Input (FIN). What kind signals will output CLK1 CLK2 output pins. Table relates value these four bit-fields four Master Modes Table relates three Slave Modes XRT8001.
Rev. 1.01
XRT8001
D[4:1] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Mode Forward/Master Forward/Master Forward/Master Reverse/Master Forward/Master Forward/Master Forward/Master Reverse/Master Forward/Master Fract. T1/E1 Reverse/Master Fract. T1/E1 Reverse/Master Fract. T1/E1 Reverse/Master Fract. T1/E1 Reverse/Master High Speed Reverse Reserved Reserved
Input Frequency input) 1.544MHz 1.544MHz 1.544MHz 56kHz 2.048MHz 2.048MHz 2.048MHz 64kHz 2.048MHz 56kHz 56kHz 64kHz 64kHz Reserved Reserved
CLK1 Output Signal 56kHz 56kHz 64kHz 1.544MHz 56kHz 56kHz 64kHz 1.544MHz 1.544MHz 1.544MHz 1.544MHz 2.048MHz 2.048MHz 2.048MHz Reserved Reserved
CLK2 Output Signal 56kHz 64kHz 64kHz 2.048MHz 56kHz 64kHz 64kHz 2.048MHz 1.544MHz 2.048MHz 1.544MHz 1.544MHz 2.048MHz 2.048MHz Reserved Reserved
Table Relationship between value (within Command Register CR0) Operating Modes XRT8001 Clock Master Modes
D[4:1] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Mode Forward/Slave Forward/Slave Forward/Slave Reverse/Slave Forward/Slave Forward/Slave Forward/Slave Reverse/Slave Reverse/Slave Reverse/Slave Reverse/Slave Reverse/Slave Reverse/Slave High Speed Reverse Reserved Reserved
Input Frequency input) 8kHz 8kHz 8kHz 8kHz 8kHz 8kHz 8kHz 8kHz 8kHz 8kHz 8kHz 8kHz 8kHz 64kHz Reserved Reserved
CLK1 Output Signal 56kHz 56kHz 64kHz 1.544MHz 56kHz 56kHz 64kHz 1.544MHz 56KHz 1.544MHz 1.544MHz 2.048MHz 2.048MHz 2.048MHz Reserved Reserved
CLK2 Output Signal 56kHz 64kHz 64kHz 2.048MHz 56kHz 64kHz 64kHz 2.048MHz 64KHz 2.048MHz 1.554MHz 1.544MHz 2.048MHz 2.048MHz Reserved Reserved
Table Relationship between value (within Command Register CR0) Operating Modes XRT8001 Clock Slave Modes
Rev. 1.01
XRT8001
PL1EN (PLL Enable Select) This bit-field permits user enable disable within XRT8001 Clock. Setting this bitfield enables Frequency Synthesis. Conversely, setting this bit-field disables Frequency Synthesis. 3.2.2 Command Register (Address 0x01) These bit-fields used support configuration implementation both "Forward/Master" Forward/Master" Modes. both "Forward/ Master" Forward/Master" Modes, XRT8001 Clock will receiving either 1.544MHz" 2.048MHz" clock signal. through bit-fields, within this register, permit user specify value "N". consequence, XRT8001 configured accept maximum frequency 1.544MHz" 2.048MHz". PL2EN (PLL Enable Select) This bit-field permits user enable disable within XRT8001 Clock. Setting this bitfield enables Frequency Synthesis. Conversely, setting this bit-field disables Frequency Synthesis. 3.2.3 Command Register (Address 0x02) (SEL1[4:0]) These bit-fields used support configuration implementation both "Forward/Master", "Fractional T1/E1 Reverse/Master" "High Speed Reverse" Modes. Forward/Master Mode "Forward/Master" Mode, XRT8001 Clock will output either 56kHz" 64kHz" clock signal CLK1 output pin. These five bitfields within Command Register used define value CLK1 Output. consequence, XRT8001 configured generate maximum frequency 56kHz" 64kHz" CLK1 output pin. "Fractional T1/E1 Reverse/Master" Mode "Fractional T1/E1 Reverse/Master" Mode, XRT8001 Clock will receiving either 56kHz" 64kHz" clock signal "FIN" input pin. XRT8001 Clock will, response, generate either 1.544MHz 2.048MHz clock signal CLK1 and/or CLK2 output pins. These five bitfields used define value "P". consequence, XRT8001 configured accept maximum frequency 56kHz" 64kHz".
Rev. 1.01
XRT8001
"High Speed Reverse" Mode "High Speed Reverse" Mode, XRT8001 Clock will receiving 64kHz clock signal "FIN" input pin. XRT8001 Clock will, response, generate 2.048MHz" clock CLK1 CLK2 output pins. These five bit-fields within Command Register used define value CLK1 output.
Note: only acceptable values
3.2.5 Command Register (Address 0x04) SYNCEN (SYNC Output Driver Enable Select) This "read/write" bit-field permits user enable disable Driver associated with SYNC output pin. Setting this bit-field enables this Driver. Setting this bit-field disables this Driver. CLK1EN (CLK1 Output Driver Enable Select) This "read/write" bit-field permits user enable disable Driver associated with CLK1 output pin. Setting this bit-field enables this Driver. Setting this bit-field disables this Driver. CLK2EN (CLK2 Output Driver Enable Select) This "read/write" bit-field permits user enable disable Driver associated with CLK2 output pin. Setting this bit-field enables this Driver. Setting this bit-field disables this Driver. LDETDIS[2:1] Lock Detector Output Control combination these bit-fields permit user specify signal that will output LOCKDET output pin. user's options shown Table
3.2.4 Command Register (Address 0x03) (SEL2[4:0]) These bit-fields used support configuration implementation "Forward/Master" "High Speed Reverse" Modes operation. "Forward/Master" Mode "Forward/Master" Mode, XRT8001 Clock will output either 56kHz" 64kHz" clock signal CLK2 output pin. These five bitfields within Command Register used define value CLK2 Output. consequence, XRT8001 configured generate maximum frequency 56kHz" 64kHz" CLK2 output pin. "High Speed Reverse" Mode "High Speed Reverse" Mode, XRT8001 Clock will receiving 64kHz clock signal "FIN" input pin. XRT8001 Clock will, response, generate 2.048MHz" clock CLK1 CLK2 output pins. These five bit-fields within Command Register used define value CLK2 output.
Note: only acceptable values
Rev. 1.01
XRT8001
LDETDIS[2:1] Signal output LOCKDET Signal LOCK Condition PLL1 PLL2 With this selection, LOCKDET output will "high" either following conditions true. both PLL1 PLL2 "LOCK" condition, (applies both PLL1 PLL2 enabled) only enabled "LOCK" condition (applies only PLLs enabled). LOCK Condition PLL2 Only With this selection, only "LOCK" state PLL2 will reflected LOCKDET output pin. LOCKDET "high" PLL2 "LOCK". LOCKDET "low" PLL2 "LOCK". LOCK Condition PLL1 Only With this selection, only "LOCK" state PLL1 will reflected LOCKDET output pin. LOCKDET "high" PLL1 "LOCK". LOCKDET "low" PLL1 "LOCK". LOCKDET will unconditionally pulled "LOW"
Table Relationship Between Values LDETDIS[2:1] Bit-Fields Meaning LOCKDET Output Signal
Instructions Configuring XRT8001 Clock mentioned earlier, XRT8001 Clock configured operate following modes:
"Forward/Master" Mode "Reverse/Master" Mode "Fractional T1/E1 Reverse/Master" Mode Forward/Master" Mode "High Speed Reverse" Mode "Forward/Slave" Mode
"Forward/Master" Mode. When XRT8001 Clock been configured operate "Forward/Master" Mode, then will accept 1.544MHz" 2.048MHz" clock signal "Reference Clock" input (pin where range anywhere between response this clock signal, XRT8001 Clock will output either 56kHz" 64kHz" clock signal, Clock Output pins (CLK1 and/or CLK2). simple illustration XRT8001 Clock, operating "Forward/Master" Mode shown figure
detailed description operation configuration steps each these configurations follows.
Rev. 1.01
XRT8001
1.544MHz 2.048MHz Where
CLK1
56kHz 64kHz Where
XRT8001 Clock
CLK2
56kHz 64kHz Where
Figure Illustration XRT8001 Clock Device Operating "Forward/Master" Mode
Configuring XRT8001 Clock into "Forward/Master" Mode
user configure XRT8001 Clock operate "Forward/Master" Mode, executing following steps:
Step Configure XRT8001 operate "MASTER" Mode, pulling (pin VDD. Step Review Table determine which combination "Input Frequency" "Output Frequencies" (via PLL1 PLL2) correlate with desired configuration.
Input Frequency 1.544MHz 1.544MHz 1.544MHz 2.048MHz 2.048MHz 2.048MHz
PLL1 Output Frequency 56kHz 56kHz 64kHz 56kHz 56kHz 64kHz
PLL2 Output Frequency 56kHz 64kHz 64kHz 56kHz 64kHz 64kHz
Value Write D4-D1 0000 0001 0010 0100 0101 0110
Table Listing "Input Frequency "Output Frequency" Cases "Forward/Master" Mode Operation
Rev. 1.01
XRT8001
Step Upon reviewing Table write listed value (under "Value Write CR0" Register Column) into through bit-fields within Command Register CR0, illustrated below. Command Register (Address 0x00)
IOC4 IOC3 IOC2 IOC1 Value Write PL1EN
order specify value "K", needs write value binary format) into Command Register CR2, illustrated below. Command Register, (Address 0x02)
SEL14 SEL13 SEL12 SEL11 SEL10 Value Binary Format).
Note: user wishes output clock signal CLK1 output signal, then he/she should also write into "PL1EN" bit-field within Command Register CR0.
example, wishes configure XRT8001 output clock signal either "56kHz" "64kHz" (e.g., where CLK1 output pin, then should write value "0", into Command Register CR2. Step Specify value (e.g., 56kHz" 64kHz" clock signal which output CLK2 output signal). order specify value "K", needs write value (binary format) into Command Register CR3, illustrated below. Command Register, (Address 0x03)
SEL24 SEL23 SEL22 SEL21 SEL20 Value Binary Format).
This step configures XRT8001 operate "Forward/Master" Mode. Step Next, need specify value (e.g., 1.544MHz" 2.048MHz" clock signal which applied "FIN" input pin.) order specify value "N", needs write value binary format) into through bits within Command Register CR1, illustrated below. Command Register, (Address 0x01)
Value Binary Format) PL2EN
example, user wishes configure XRT8001 accept 1.544MHz clock signal, "FIN" input (e.g., then user should write value "0", into Command Register CR1.
Note: user wishes output clock signal CLK2 output signal, then he/she should also write into "PL2EN" bit-field within Command Register CR1.
example, wishes configure XRT8001 output clock signal either "1.792MHz" "2.048MHz" (e.g., where CLK2 output pin, then he/she should write value "31" binary format) into Command Register CR3. Step Enable following output signals appropriate: "SYNC", "CLK1", "CLK2" "LOCKDET". This accomplished writing into corresponding bit-fields, within Command Register CR4, illustrated below. Command Register CR4, (Address 0x04)
SYNCEN
Step Specify value (e.g., 56kHz" 64kHz" clock signal which output CLK1 output signal).
CLK1EN
CLK2EN
LDETDIS2
LDETDIS1
Note: information "LDETDIS1" "LDETDIS2" bit-fields, please Table
Rev. 1.01
XRT8001
"Reverse/Master" Mode When XRT8001 Clock been configured operate "Reverse/Master" Mode, then will accept either "56kHz" "64kHz" clock signal "Reference Clock" input (pin response this clock signal, XRT8001 Clock will output either "1.544MHz" "2.048MHz" clock signal, Clock Output pins (CLK1 and/or CLK2). simple illustration XRT8001 Clock, operating "Reverse/Master" Mode presented Figure
56kHz 64kHz
CLK1
1.544MHz 2.048MHz
XRT8001 XRT8001 Clock Clock
CLK2
1.544MHz 2.048MHz
Figure Illustration XRT8001 Clock Operating "Reverse/Master" Mode
Configuring XRT8001 Clock Device into "Reverse/Master" Mode user configure XRT8001 Clock operate "Reverse/Master" Mode, executing following steps: Step Configure XRT8001 operate "MASTER" Mode pulling "MSB" (pin VDD. Step Review Table determine which combination "Input Frequency" "Output Frequencies" (via PLL1 PLL2) correlate with desired configuration.
Rev. 1.01
XRT8001
Input Frequency 56kHz 64kHz PLL1 Output Frequency 1.544MHz 1.544MHz PLL2 Output Frequency 2.048MHz 2.048MHz Value Write 0011 0111
Table Listing "Input Frequency" "Output Frequency" Cases "Reverse/Master" Mode Operation
Step Upon reviewing Table write listed value (under "Value Write CR0" register) into through bit-fields within Command Register CR0, illustrated below: Command Register (Address 0x00)
IOC4 IOC3 IOC2 IOC1 Value Write PL1EN
Step Enable following output signals appropriate: SYNC", CLK1, CLK2 LOCKDET. This accomplished writing into corresponding bit-fields, within Command Register CR4, illustrated below: Command Register CR4, (Address 0x04)
SYNCEN
CLK1EN
CLK2EN
LDETDIS2
LDETDIS1
Note: user wishes output clock signal CLK1 output signal, then he/she should also write into "PL1EN" bit-field within Command Register CR0.
Note: information "LDETDIS1" "LDETDIS2" bit-fields, please Table
"Fractional T1/E1 Reverse/Master" Mode This step configures XRT8001 operate "Reverse/Master" Mode. Step Write into "PL2EN" bit-field within Command Register wish output clock signal "CLK2" output pin), illustrated below: Command Register, (Address 0x01)
Don't Care PL2EN
When XRT8001 Clock been configured operate "Fractional T1/E1 Reverse/Master" Mode, then will accept either 56kHz" 64kHz" clock signal "FIN" input (pin response, XRT8001 will output either 1.544MHz 2.048MHz clock signal CLK1 and/or CLK2 outputs. simple illustration XRT8001 Clock, operating "Fractional T1/E1 Reverse/Master" Mode presented Figure
Notes: value through bit-fields within Command Register, "Don't Care". contents Command Registers "Don't Care".
Rev. 1.01
XRT8001
56kHz 64kHz Where:
CLK1
1.544MHz 2.048MHz
XRT8001 XRT8001 Clock Clock
CLK2
1.544MHz 2.048MHz
Figure Illustration XRT8001 Clock Operating "Fractional T1/E1 Reverse/Master" Mode
Configuring XRT8001 Clock into "Fractional T1/E1 Reverse/Master" Mode user configure XRT8001 Clock operate "Fractional T1/E1 Reverse/Master" Mode executing following steps.
Step Configure XRT8001 operate "MASTER" Mode, pulling "MSB" input (pin VDD. Step Review Table determine which combination "Input Frequency" "Output Frequencies" (via PLL1 PLL2) correlate with desired configuration.
Input Frequency 56kHz 56kHz 64kHz 64kHz
PLL1 Output Frequency 1.544MHz 1.544MHz 2.048MHz 2.048MHz
PLL2 Output Frequency 2.048MHz 1.544MHz 1.544MHz 2.048MHz
Value Write 1001 1010 1011 1100
Table Listing "Input Frequency" "Output Frequency" Cases "Fractional T1/E1 Reverse/ Master" Mode Operation
Rev. 1.01
XRT8001
Step Upon reviewing Table write listed value (under "Value Write CR0" register) into through bit-fields within Command Register CR0, illustrated below: Command Register (Address 0x00)
IOC4 IOC3 IOC2 IOC1 Value Write PL1EN
Step Write binary expression "11111" into Command Register CR3. This step necessary order insure proper operation XRT8001. This step also illustrated below: Command Register, (Address 0x03)
SEL24 SEL23 SEL22 SEL21 SEL20
Notes: user wishes output clock signal CLK1 output signal, then he/she should also write into "PL1EN" bit-field within Command Register CR0. contents bit-fields through (within Command Register CR1) "Don't Care" user wishes output clock signal CLK2 output signal, then he/she should also write into "PL2EN" bit-field within Command Register CR1.
Step Enable following output signals appropriate: "SYNC", "CLK1", "CLK2" "LOCKDET". This accomplished writing into corresponding bit-fields, within Command Register CR4, illustrated below:
Command Register CR4, (Address 0x04)
SYNCEN
This step configures XRT8001 operate "Fractional T1/E1 Reverse/Master" Mode. Step Specify value (e.g., 56kHz" 64kHz" clock signal which input Reference Clock input). order specify value "P", needs write value (binary format) into Command Register CR2, illustrated below: Command Register, (Address 0x02)
SEL14 SEL13 SEL12 SEL11 SEL10 Value Binary Format).
CLK1EN
CLK2EN
LDETDIS2
LDETDIS1
-Forward/Master" Mode When XRT8001 Clock been configured operate Forward/Master" Mode, then will accept 2.048MHz" clock signal "Reference Clock" input (pin where range anywhere between response this clock signal, XRT8001 Clock will output 1.544MHz clock signal Clock Output pins (CLK1 and/or CLK2). simple illustration XRT8001 Clock, operating Forward/Master" Mode presented Figure
other words, intends input either "56kHz" "64kHz" clock signal "FIN" input (e.g., where then he/she should write into Command Register CR2.
Rev. 1.01
XRT8001
2.048MHz Where:
CLK1
1.544MHz
XRT8001 XRT8001 Clock
CLK2
1.544MHz
Figure Illustration XRT8001 Clock Operating Forward/Master" Mode Configuring XRT8001 Clock into Forward/Master" Mode user configure XRT8001 Clock operate Forward/Master" Mode executing following steps: Step Configure XRT8001 operate "MASTER" Mode, pulling "MSB" input (pin VDD. Step Write binary value "1000" into Command Register CR0, illustrated below: This step configures XRT8001 Clock operate Forward/Master" Mode.
Note: user wishes output clock signal CLK1 output signal, then he/she should also write into "PL1EN" bit-field within Command Register, CR0.
Step Next, need specify value *(e.g., 2.048MHz" clock signal which will applied "FIN" input pin). user accomplishes this writing binary expression into Command Register, CR1, illustrated below.
Command Register (Address 0x00)
IOC4 IOC3 IOC2 IOC1 PL1EN
Command Register, (Address 0x01)
Value Binary Format) PL2EN
Rev. 1.01
XRT8001
example, user wishes input clock signal 2.048MHz, "FIN" input (e.g., where then he/she should write into Command Register CR1.
Note: user wishes output clock signal CLK2 output signal, then he/she should also write into "PL2EN" bit-field within Command Register CR1.
Step Enable following output signals appropriate: "SYNC", "CLK1", "CLK2" "LOCKDET". This accomplished writing into corresponding bit-fields, within Command Register CR4, illustrated below.
Command Register CR4, (Address 0x04)
SYNCEN CLK1EN CLK2EN LDETDIS2 LDETDIS1
Step Write binary expression "11111" into Command Register CR2, illustrated below. This step necessary order insure proper operation XRT8001.
"High Speed Reverse" Mode Command Register, (Address 0x02) SEL14 SEL13 SEL12 SEL11 SEL10 Step Write binary expression "11111" into Command Register CR3, illustrated below. This step necessary order insure proper operation XRT8001. This step also illustrated below. Command Register, (Address 0x03) SEL24 SEL23 SEL22 SEL21 SEL20 When XRT8001 Clock been configured operate "High Speed Reverse" Modes, operation independent whether been configured "Master" "Slave" Mode. When XRT8001 Clock been configured operate "High Speed Reverse" Modes, then will accept "64kHz" clock signal "Reference Clock" input (pin response, this clock signal, XRT8001 Clock will output 2.048MHz" clock signal Clock Output pins (CLK1 and/or CLK2); where only have values simple illustration XRT8001 Clock, operating "High Speed Reverse" Mode presented Figure
Rev. 1.01
XRT8001
64kHz
CLK1
2.048MHz
XRT8001 Clock
2.048MHz CLK2
Figure Illustration XRT8001 Clock Operating "High Speed Reverse" Mode
Configuring XRT8001 Clock into "High Speed Reverse" Mode. user configure XRT8001 Clock operate "High Speed Reverse" Mode, executing following steps. Step Configure XRT8001 operate "SLAVE" Mode, pulling "MSB" input (pin GND. Step Write value "1101" into D4-D1 within command register Command Register (Address 0x00) IOC4 IOC3 IOC2 IOC1 PL1EN
Note: user wishes output clock signal CLK1 output signal, then he/she should also write into "PL1EN" bit-field within Command Register CR0.
Step Write binary expression "0000" into bitfields through within Command Register, CR1, illustrated below. Command Register, (Address 0x01) PL2EN
Note: user wishes output clock signal CLK2 output signal, then he/she should also write into "PL2EN" bit-field within Command Register CR1.
Step Specify value (e.g., 2.048MHz" clock signal) which output "CLK1" output pin. This accomplished reviewing Table determining binary value which corresponds with desired value "M". Afterwards, user should write this value into Command Register CR2.
This step configures XRT8001 operate "High Speed Reverse" Mode.
Rev. 1.01
XRT8001
Value Value Written into Command Register 0000X 0001X 001XX X1XX 1XXX
Command Register, (Address 0x03)
SEL24 SEL23 SEL22 SEL21 Value from Table SEL20
Table Relationship Between Value Value Written into Command Register Order Configure "CLK1" Output Frequency)
Note: expression indicates "Don't Care" value that particular bit-field.
Step Enable following output signals appropriate: "SYNC", "CLK1", "CLK2" "LOCKDET". This accomplished writing into corresponding bit-fields, within Command Register CR4, illustrated below:
Command Register CR4, (Address 0x04)
Command Register, (Address 0x02)
SEL14 SEL13 SEL12 SEL11 Value from Table SEL10
SYNCEN
CLK1EN
CLK2EN
LDETDIS2
LDETDIS1
"Forward/Slave" Mode Step Specify value (e.g., 2.048MHz" clock signal) which output "CLK2" output pin. This accomplished reviewing Table determining 5-bit binary value which corresponds with desired value "M". Afterwards, user should write this value into Command Register, CR3.
Value Value Written into Command Register 0000X 0001X 001XX X1XXX 1XXXX
When XRT8001 Clock been configured operate "Forward/Slave" Mode, then will accept 8kHz clock signal "Reference Clock" input (pin response this clock signal, XRT8001 Clock will output either 56kHz" 64kHz" clock signal "Clock Output pins" (CLK1 CLK2); where range value from simple illustration XRT8001 Clock operating "Forward/Slave" Mode" presented Figure
Table Relationship Between Value Value Written into Command Register Order Configure "CLK2" Output Frequency)
Note: expression indicates "Don't Care" value that particular bit-field.
Rev. 1.01
XRT8001
8kHz
CLK1
56kHz 64kHz
XRT8001 Clock
CLK2
56kHz 64kHz
Figure Illustration XRT8001 Clock operating "Forward/Slave" Mode
Configuring XRT8001 Clock into "Forward/Slave" Mode. user configure XRT8001 Clock operate "Forward/Slave Mode" executing following steps: Step Configure XRT8001 operate "SLAVE" Mode pulling input (pin GND. Step Refer Table write value that corresponds desired "Forward/Slave" Mode into Bits D[4:1] within Command Register CR0. Step Define values CLK1 output writing appropriate value into register. This achieved writing value into this register.
Notes: example, user writes "00000" into this register, then XRT8001 device will output 64kHz signal CLK1 output pin. user intends output data CLK1, then he/she must ensure that PL1EN bit-field within Command Register "1".
Step Define value CLK2 output writing appropriate value into register. This achieved writing value into this register.
Note: user intends output data CLK2, then must ensure that PL2EN bit-field within Command Register "1".
Step CLK1EN CLK2EN bit-fields, within Command Register order enable output drivers CLK1 CLK2, illustrated below. Command Register
SYNCEN CLK1EN CLK2EN
Rev. 1.01
XRT8001
1.544 2.048
CLK1
CLK2
1.544 2.048
Figure XRT8001 Reverse/Slave Mode 6.10 Phase relationship between "FIN" input "CLK1 CLK2" outputs Phase relationship depends upon whether XRT8001 operating "Slave" "Master" Mode. 6.11 Slave Mode: XRT8001 operating "Slave" Mode, then there specific phase relationship between "FIN" "CLK1, CLK2" outputs. reasons follows. Slave Mode Operation, XRT8001 accepts 8kHz clock signal (which will also synthesize output SYNC output signal). Each PLLs (within XRT8001) will configured generate either 56kHz" 64kHz" clock signal. Hence, "Slave Mode", "SYNC" output, simply buffered version "FIN" input. Therefore, generate 56kHz" clock signal.
"SYNC" signal approximately delayed from "FIN" input signal. Each PLLs "lock" onto "SYNC" signal, frequency synthesis. This timing relationship (between CLK1, CLK2 signals) depends upon "CLK1" "CLK2" signal frequencies listed following tables.
NOTES: Table presents timing relationship between "FIN" "CLK1, CLK2" PLLs configured generate 64kHz" clock signal. Table presents timing relationship between "FIN" "CLK1, CLK2" PLLs configured generate 56kHz" clock signal.
CLK1 CLK2
Figure Timing Relationship between "CLK1/CLK2" outputs
Rev. 1.01
XRT8001
Values written into 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Value "SEL1[4:0] CLK1/CLK2 64kHz) 64kHz 128kHz 192kHz 256kHz 320kHz 384kHz 448kHz 512kHz 576kHz 640kHz 704kHz 768kHz 832kHz 896kHz 960kHz 1.024MHz 1.088Mhz 1.152MHz 1.214MHz 1.280MHz 1.344MHz 1.408MHz 1.472MHz 1.536MHz 1.600MHz 1.664MHz 1.728MHz 1.792MHz 1.856MHz 1.920MHz 1.984MHz 2.048MHz (ns) Output Frequency
Table Timing Relationship (T), from rising edge "CLK1/CLK2" rising edge "FIN" with XRT8001 Slave Mode, 8kHz
Rev. 1.01
XRT8001
Values written into 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Value "SEL1[4:0] CLK1/CLK2 56kHz) 56kHz 112kHz 168kHz 224kHz 280kHz 336kHz 392kHz 448kHz 504kHz 560kHz 616kHz 672kHz 728kHz 784kHz 840kHz 896kHz 952kHz 1.008MHz 1.064MHz 1.120MHz 1.176MHz 1.232MHz 1.288MHz 1.344MHz 1.400MHz 1.456MHz 1.512MHz 1.568MHz 1.624MHz 1.680MHz 1.756MHz 1.812MHz (ns) Output Frequency
Table Timing Relationship (T), from rising edge "CLK1/CLK2" rising edge "FIN" with XRT8001 Slave Mode, 8kHz
6.12 Master Mode: XRT8001 operating "Master" Mode, then timing relationship between "Reference signal" (e.g., signal applied "FIN" "CLK1" "CLK2" output readily available. This because "FIN" signal internally divided down,
Programmable Divider, which generates "SYNC" signal. internal Phase Locked Loops (within XRT8001) "locked" onto "SYNC" signal. Hence, there definitely phase relationship between "SYNC" "CLK1, CLK2" outputs.
Rev. 1.01
XRT8001
Phase Relationship Between SYNC CLK1 CLK2 Table presents information delay between rising edge SYNC CLK1 CLK2 output signals. important Note that this delay behaves function settings within register.
SEL14~SEL10 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111
Values (nS) Kx56 MODE
Kx64 MODE
Table Delay Time Between SYNC CLK1 CLK2
Note: This table only applies when XRT8001 configured operate "Forward/Master" "Forward/Slave" Modes.
Rev. 1.01
XRT8001
Synthesizing 2.048MHz" clock signal, such that take value "1", "2", "4", with clock signal 2.048MHz Figure presents possible approach that used. this example, user takes 2.048MHz clock signal, runs through external "Divideby-32" counter (which realized with 74AHCT193). This "Divide-by-32" counter generates 64kHz clock signal, which applied "FIN" input XRT8001.
user configures XRT8001 Clock operate "High Speed Reverse" Mode, then will accepts 64kHz clock signal (via input) generates 2.048MHz" clock signal both CLK1 CLK2 outputs.
NOTES: this configuration, configured value "1", "2", "8". steps required configure XRT8001 into "High Speed Reverse" Mode presented below.
LOAD
2.048MHz_CLOCK
74AHCT193
LOAD 64kHz Clock Signal SCLK LOCKDET Serial_Clock Serial_Data_Out Serial_Data_In XRT8000_Select WAN_CLOCK_PLL_LOCK_STATUS CLK1 2.048MHz_CLOCK
CLK2
2.048MHz_CLOCK
Clear_Counter
74AHCT193
XRT8001
Figure Circuit that inputs 2.048MHz clock generates 2.048MHz clock
Configuring XRT8001 Clock operate "High Speed Reverse" Mode. following "six-step" procedure configure XRT8001 Clock into "High Speed Reverse" Mode. STEP Configure XRT8001 operate "SLAVE" Mode, pulling "MSB" input (pin (low). STEP Write binary expression "1101" into bitfields through within Command Register, CR0, indicated below. Command Register, (Address 0x01) PL2EN
Rev. 1.01
XRT8001
This step configures XRT8001 operate "High Speed Reverse" Mode.
NOTE: user wishes output clock signal "CLK1" output pin, then he/she should also write into "PL1EN" bit-field within Command Register, CR0.
STEP Specify value (e.g., 2.048MHz" clock signal) which output "CLK2" output pin.
This accomplished reviewing Table determine binary value corresponding with desired value "M". Afterwards, user should write this value into Command Register, CR3.
STEP Write binary expression "0000" into bit-fields through within Command Register, CR1, illustrated below. Command Register, (Address 0x01) PL2EN
NOTE: user wishes output clock signal CLK2 output pin, then he/she should also write into "PL2EN" bit-field within Command Register
Value
Value written into Command Register, 0000x 0001x 001xx x1xx 1xxx
STEP Specify value (e.g., 2.048MHz" clock signal) which output "CLK1" output pin. This accomplished reviewing Table determine binary value which corresponds with desired value "M". Afterwards, user should write this value into Command Register, CR2.
Table Relationship between value "M", Value written into Command Register, configure "CLK2" output frequency STEP Enable desired output signals: "SYNC", "CLK1", "CLK2" "LOCKDET". This accomplished writing into corresponding bit-fields, within Command Register CR4, illustrated below.
Value
Value written into Command Register, 0000x 0001x 001xx x1xx 1xxx
Command Register, (Address 0x04)
SYNCEN CLK1EN CLK2EN LDETDIS2 LDETDIS1
Table Relationship between value "M", Value written into Command Register, configure "CLK1" output frequency
Rev. 1.01
XRT8001
Generating 2.048MHz from 1.55MHz
Optional
N.C. 1.544
SYNC 8/64
SCLK
XRT8001
CKL1
2.048
LOCKDET
N.C.
Clock Data
Serial Port Control
Reset
Optional
Busy VER_REQ VER_PASS/FAIL
Figure Typical Application Example: Generating 2.048MHz from 1.544MHz
Serial Port Programming Four Steps
Step Procedure "MSB_OUT" output "high" Write value "00101" into Command Register (located 0x00) Result Configures XRT8001 operate "Master" mode Configures XRT8001 accept 1.544MHz clock signal "FIN" input pin., output 64kHz" clock signal "CLK1" output pin. (For this application 32). This step also enables "PLL within XRT8001 Sets 1.544MHz") Sets 64kHz") "32" Enables output driver CLK1
Write value "00000" into Command Register (located 0x01) Write value "11111" into Command Register (located 0x02) Write value "01000" into Command Register (located 0x04)
Rev. 1.01
XRT8001
Generating 1.544MHz clock signal "CLK1/CLK2" outputs from either 1.544MHz, 2.048MHz clock signal When approaching this problem, aware that XRT8001 Clock configured accept 2.048MHz clock signal "FIN" input generate 1.544MHz clock signal. However, XRT8001 Clock cannot configured accept 1.544MHz clock signal, generate 1.544MHz clock signal. Also, note XRT8001 Clock configured accept 2.048MHz clock signal (via "FIN" input) generate 1.544MHz clock signal configured operate Forward/Master" Mode. XRT8001 similarly configured accept 8kHz clock signal (via same "FIN" input pin) generate 1.544MHz clock signal configured operate "Reverse/Slave" Mode. Based upon these points, necessary circuitry order synthesize 1.544MHz clock signal, from either 1.544MHz 2.048MHz clock signal) achieved approach shown below block diagram.
2.048MHz 8kHz Clock Signal
1.544MHz 2.048MHz Clock Signal
8kHz Divide Divide
CLK1
1.544MHz
CLK2
1.544MHz
XRT8001 Clock
E1/T1* SELECT
Figure Synthesizing 1.544MHz clock signal from 1.544MHz 2.048MHz clock Figure 1.544MHz 2.048MHz input clock signal routed locations. inputs "2:1 MUX". this case, user must "E1/T1* SELECT" signal "LOW", order select rates" (1.544MHz). doing this, 8kHz output from "Divide-by-193" block selected will applied "FIN" input XRT8001; XRT8001 will configured operate "Slave" Mode. this point, user will need execute appropriate steps order configure XRT8001 into "Reverse-Slave" Mode. incoming clock signal (from T1/E1 LIU) 2.048MHz clock signal, then this signal will also divided 193. passes through "Divide-by193" block, generates clock signal strange (and undesirable frequency). This clock signal will applied inputs "2:1 MUX" (NOTE: 2.048MHz clock will also applied other input "2:1 MUX).
"CU" input "Divide-by-193" Block.
Figure also includes digital "E1/T1* SELECT" signal. This signal connected both "SEL" input "2:1 MUX" "MSB" input XRT8001 Clock. basic idea behind this schematic follows: incoming clock signal (from T1/E1 example) 1.544MHz clock signal, then this signal will divided 193. passes through "Divideby-193" block 8kHz clock signal generated. This 8kHz clock signal will applied inputs "2:1 MUX". (NOTE: 1.544MHz clock signal applied other input "2:1 MUX").
Rev. 1.01
XRT8001
this case, user must "E1/T1* SELECT" signal "HIGH", order select rates" (2.048MHz). doing this, 2.048MHz clock signal (from LIU) selected will applied "FIN" input XRT8001, XRT8001 will configured operate "Master" Mode. this point, user will need execute appropriate steps order configure XRT8001 into Forward/Master" Mode. Hardware Software Implementation Details Figure presents simple block diagram design that accept either 1.544MHz 2.048MHz clock signal, synthesize 1.544MHz clock signal. need provide some details. Hence, Figure presents circuit schematic which realizes function, depicted Figure
Divide-by-193 1.544MHz 2.048MHz 1.544MHz 2.048MHz E1/T1* SELECT 74AHCT157 8kHz 2.048MHz
74AHCT04 LOAD
SCLK
CLK1
1.544MHz
74AHCT193 8001_SCLK 8001_SDO 8001_SDI 8001_CS XRT8001
LOAD
CLK2
1.544MHz
LOCKDET
LOCK_DET
74AHCT193
Load-in-64
E1/T1* SELECT
Figure Hardware Design Implementation Figure Next, describe configure circuitry Figure accept 2.048MHz clock signal, configure synthesize 1.544MHz clock signal executing five steps. also describe accept 1.544MHz clock signal configure synthesize 1.544MHz clock. Configuring Circuitry Figure accept 2.048MHz clock order synthesize 1.544MHz output clock. STEP Drive "E1/T1* SELECT" input "HIGH". This step configures "2:1 MUX" select apply 2.048MHz clock "FIN" input XRT8001 Clock, well configuring XRT8001 Clock into "Master Mode".
NOTE: next steps devoted configuring XRT8001 Clock into Forward/Master" Mode.
STEP Write binary value "1000" into Command Register (within XRT8001 Clock) indicated below. Command Register, (Address 0x00) IOC4 IOC3 IOC2 IOC1 PL1EN
Rev. 1.01
XRT8001
NOTE: order synthesize output clock signal "CLK1" output pin, user must write into (PL1EN) bit-field within Command Register, CR0, indicated above.
Once user executed these five steps, then circuitry Figure configured accept 2.048MHz clock signal (from T1/E1 LIU) synthesize 1.544MHz clock signal. Configuring Circuitry Figure accept 1.544MHz clock signal synthesize 1.544MHz clock signal. user configure circuitry (within Figure accept 1.544MHz clock signal, synthesize 1.544MHz clock signal, executing following four steps. STEP Drive "E1/T1* SELECT" input "LOW". This step configures "2:1 MUX" select apply 8kHz clock signal "FIN" input XRT8001 Clock, configures XRT8001 Clock into "Slave" Mode.
NOTE: next steps will devoted configuring XRT8001 Clock into "Reverse/Slave" Mode.
This step configures XRT8001 operate Forward/Master" Mode. this mode, XRT8001 Clock will configured accept 2.048MHz" clock signal "FIN" input will synthesize 1.544MHz clock signal both "CLK1" "CLK2" output pins. STEP Next specify value (e.g., 2.048MHz" clock signal, which will applied "FIN" input). this application, value "1". Hence, user must configure XRT8001 Clock this value "Q", writing binary value into Command Register, CR1. this application, user should write "0000" into Command Register, indicated below. Command Register, (Address 0x01) PL2EN
NOTE: order synthesize output clock signal "CLK2" output pin, user must write into (PL2EN) bit-field within Command Register, CR1, indicated above.
STEP Write binary value "1000" into Command Register CR0, within XRT8001 Clock, indicated below. Command Register, (Address 0x00)
IOC4 IOC3 IOC2 IOC1 PL1EN
STEP Write binary value "11111" into both Command Registers CR3. This necessary order ensure proper operation XRT8001 Clock. STEP Enable desired output signals: SYNC, CLK1, CLK2, LOCKDET. This accomplished writing into corresponding bit-field, within Command Register, CR4, illustrated below. Command Register, (Address 0x04)
SYNCEN CLK1EN CLK2EN LDETDIS2 LDETDIS1
NOTE: order synthesize output clock signal "CLK1" output pin, user must write into (PL1EN) bit-field within Command Register, CR0, indicated above.
This step configures XRT8001 operate "Reverse/Slave" Mode. this mode, XRT8001 Clock will configured accept 8kHz clock signal "FIN" input will synthesize 1.544MHz clock signal both "CLK1" "CLK2" output pins. STEP Write binary expression "0000" into bitfields through within Command Register CR1, illustrated below.
Rev. 1.01
XRT8001
Command Register, (Address 0x01) PL2EN
NOTE: order synthesize output clock signal "CLK2" output, user must write into (PL2EN) bit-field within Command Register, CR1, illustrated above.
values within Command Registers "don't care". STEP Enable desired output signals: SYNC, CLK1, CLK2, LOCKDET. This accomplished writing into corresponding bit-field, within Command Register, CR4, illustrated below.
Command Register, (Address 0x04) SYNCEN CLK1EN CLK2EN LDETDIS2 LDETDIS1
Once user executed these four steps, then circuitry Figure configured accept 1.544MHz clock signal (from T1/E1 LIU) synthesize 1.544MHz clock signal.
Rev. 1.01
XRT8001
10.0 Jitter Transfer Characteristics XRT8001 definition "Jitter Transfer Characteristics" XRT8001) amount "output" jitter that XRT8001 produces "CLK1" "CLK2" outputs), when provided with certain amount jitter input pin. "Jitter Transfer Characteristics" XRT8001 presented Figure (for 3.3V applications) Figure 26(for 5.0V applications).
Jitter Gain
Normalized Wideband Output Jitter
1100 Frequency
1300
1500
1700
1900
Figure Jitter Transfer Characteristics XRT8001 Clock 3.3V Applications
Jitter Gain
Normalized Wideband Output Jitter
1100
1300
1500
1700
1900
Frequency
Figure Jitter Transfer Characteristics XRT8001 Clock Applications
Rev. 1.01
XRT8001
10.1 Reading Figures Figures linear opposed logarithmic) plots. Jitter Gain computed following equation. Jitter Gain Jitter Frequency 11.0 layout guidelines XRT8001
multi-layer circuit board with separate plane
layers "+5V" 3.3V) "Ground"
Bypass Analog ground with 6.9mF
"ceramic" capacitor.
Where: Jitter_Amplitude_FIN Jitter Amplitude applied "FIN" input Jitter Frequency Jitter_Amplitude_CLK Jitter Amplitude measured "CLK1" "CLK2" output, when "Jitter_Amplitude_FIN" applied input XRT8001. Hence, Jitter Gain expressed terms simply ratio numbers. Wherever Jitter Gain exceeds "1.0" value, then, those "Jitter Frequencies" XRT8001 amplifies Jitter (e.g., amplitude jitter, propagates from "FIN" input "CLK1" CLK2" output, increases). Conversely, wherever Jitter Gain falls below "1.0" value, then those "Jitter Frequencies" XRT8001 attenuates jitter (e.g., amplitude jitter, propagates from "FIN" input "CLK1" "CLK2" output, decreases). Figures indicate that Jitter Frequencies, ranging between 100Hz 1100Hz, XRT8001 amplifies Jitter. Further, these figures also indicate that Jitter Frequencies greater than 1100Hz, that XRT8001 attenuates Jitter. 10.2 Test Conditions Measurements associated with Figures Power Supply voltage either 3.3V
large "vias" located close package
ensure that Digital (e.g., pins Digital Ground (e.g., pins have inductance path (+3.3V) Ground Planes, respectively.
Bypass Digital pins (pin ground with
0.1mF ceramic capacitors that located close possible package. 12.0 Comparing XRT8001 with earlier pincompatible XRT8000 XRT8001 pin-to-pin compatible with XRT8000. However, there some functional differences between these products. These differences summarized below. XRT8001 configured generate frequencies 2.048MHz, 4.096MHz, 8.192MHz 16.384MHz. Maximum Frequency that XRT8000 generate either 2.048MHz 1.544MHz XRT8001 configured accept rate clock signal synthesize rate clock signal. XRT8001 also synthesize rate clock signal, when provided with rate clock signal XRT8000 configured accept rate clock signal (e.g., 1.544MHz) easily configured synthesize rate clock signal (e.g., 2.048MHz). However, XRT8000 cannot configured accept rate clock signal synthesize rate clock signal.
Input Clock Frequency 2.048MHz Output Clock Frequency 2.048MHz Input Jitter Amplitude 0.25Upp. Ambient Temperature 25°C.
Rev. 1.01
XRT8001
Both XRT8001 XRT8000 configured accept "Fractional T1/E1" rate clock signals (e.g., 64kHz) synthesize either 1.544MHz 2.048MHz clock signal. However, XRT8001 also synthesize "Fractional T1/E1" rate clock signals, when provided with either 1.544MHz 2.048MHz clock signal XRT8001 permits user determine exact role LOCKDET output pin. on-chip Command Register (within XRT8001) permits user configure LOCKDET output have functions listed below. XRT8000, LOCKDET output pulled HIGH only when both XRT8000 PLLs "in-lock".
LOCKDET Function LOCK Condition both PLL1 PLL2
Description LOCKDET pin's role LOCKDET output toggles "HIGH" only both only enabled) PLLs "In-LOCK". LOCKDET output will toggle "LOW" PLLs LOCK.
NOTE: this case, LOCKDET output XRT8001 behaves identical that XRT8000.
LOCK Condition PLL1 Only LOCK Condition PLL2 Only Forced "LOW"
LOCKDET output toggles "HIGH" only PLL1 "InLOCK" condition. LOCKDET output toggles "HIGH" only PLL2 "InLOCK" condition. LOCKDET output pulled "LOW" regardless "Lock" condition PLLs.
NOTE: XRT8000 additional divide block which included XRT8001.
Table Selectable Functions LOCKDET Output XRT8001
Rev. 1.01
XRT8001
Rev. 1.01
XRT8001
Rev. 1.01
XRT8001
NOTICE EXAR Corporation reserves right make changes products contained this publication order improve design, performance reliability. EXAR Corporation assumes responsibility circuits described herein, conveys license under patent other right, makes representation that circuits free patent infringement. Charts schedules contained here only illustration purposes vary depending upon user's specific application. While information this publication been carefully checked; responsibility, however, assumed accuracies. EXAR Corporation does recommend products life support applications where failure malfunction product reasonably expected cause failure life support system significantly affect safety effectiveness. Products authorized such applications unless EXAR Corporation receives, writing, assurances satisfaction that: risk injury damage been minimized; user assumes such risks; potential liability EXAR Corporation adequately protected under circumstances. Copyright 2001 EXAR Corporation DatasheetOctober 2001 Reproduction, part whole, without prior written consent EXAR Corporation prohibited. Rev. 1.01

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