Enhanced Memory Systems SS2625 72-Mbit synchronous pipelined burst SRA

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Enhanced Memory Systems SS2625 72-Mbit synchronous pipelined burst SRA

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72Mbit Pipelined BSRAM NoBL Architecture 2Mx36 Description
Enhanced Memory Systems SS2625 72-Mbit synchronous pipelined burst SRAM designed specifically support back-to-back read/write operations without insertion wait states. device organized 2Mx36 offered 3.3V 2.5V versions. They designed transfer data every clock cycle. This feature dramatically improves throughput, especially systems that require frequent write/read transitions. synchronous inputs pass through input registers controlled rising edge clock. data outputs pass through output registers controlled rising edge clock. clock input qualified Clock Enable signal, which, when deasserted, suspends operation extends previous clock cycle. Maximum access delay from rising edge clock (166 device). Write operations controlled four Byte Write Select signals Read/Write signal. writes conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enable signals asynchronous Output Enable signal provide easy depth expansion output three-state control. avoid contention, output drivers synchronously three-stated during data portion write sequence.
High Density 72-Mbit operations with zero wait states Data transferred every clock Fully Registered Pipelined Operation User Selectable Linear Interleaved Burst Order Byte Write Capability Single 2.5V 3.3V Power Supply Fast Clock Output Times (for device) (for device) (for device) Clock Enable Suspend Operations Synchronous Self Timed Writes Asynchronous Output Enable JEDEC Standard 100-pin TQFP 119-pin PBGA Standby Power JTAG 1149.1 Compliant Boundary Scan
Block Diagram
Data-In
Reg.
Addr CKE# CE1# CE3# R/W# BW#(a:d)
CONTROL WRITE LOGIC
Memory Array
OUTPUT REGISTERS LOGIC
2Mx36
DQ(a:d)
This product sampling pre-production phase development. Characteristic data other specifications subject change without notice. Revision
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72Mbit Pipelined BSRAM NoBL Architecture 2Mx36 Assignments (Top View)
BWd#
BWb#
BWa#
BWc#
CKE#
R/W#
CE1#
CE3#
VDDQ VSSQ VSSQ VDDQ VDDQ VSSQ VSSQ VDDQ
VDDQ VSSQ VSSQ VDDQ VDDQ VSSQ VSSQ VDDQ
SS2625 100-pin TQFP
LBO#
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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72Mbit Pipelined BSRAM NoBL Architecture 2Mx36
Assignments (Top View)
SS2625 2Mx36 119-ball PBGA
VDDQ VDDQ VDDQ VDDQ VDDQ
BWc# BWd# LBO#
CE1# R/W# CKE#
BWb# BWa#
CE3#
VDDQ VDDQ VDDQ VDDQ VDDQ
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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72Mbit Pipelined BSRAM NoBL Architecture 2Mx36 Descriptions
Symbol
CKE# CE1#, CE2, CE3#
Type
Input Input Input
Function
Clock: input signals (except output signals referenced rising edge CLK. Clock Enable: This active input enables internal clock signal. CKE# driven high, chip ignores clock (all signals except suspends pending operations. Chip Enable Inputs: These inputs determine whether begins read, write, deselect cycle. When qualified low, three inputs must true select chip begin read write cycle. When qualified low, least chip enable input must false begin deselect cycle. Load Input: This active input loads external address, begins read write cycle. Once read write cycle initiated, must negated advance internal burst counter. cannot asserted consecutive clocks. Read/Write Input: When asserted chip enabled, this input determines whether chip begins read (R/W# high) write (R/W# low) cycle. Byte Write Inputs: These active inputs allow write data written low) masked high) during write cycles. During read deselect cycles, inputs ignored. controls DQa, controls DQb, controls DQc, controls DQd. Address Inputs: Used select starting burst address location. address inputs sampled when chip enabled. Inputs determine starting address burst cycles. Data Inputs: These pins deliver output data during burst read cycles. Output data valid from rising edge clock. These data pins also allow input write data written chip. Input data must satisfy setup hold timing specifications. Output Enable Input: This active input enables output data buffers drive output data during read cycles. When negated, three states data bus. data output pins automatically three stated during write deselect cycles. Linear Burst Order Input: This signal must remain steady state. Linear burst. High Interleaved burst. Input: These unused pins left open circuit, should reserved future address pins. Test Clock: Input clock boundary scan. boundary scan used, must tied VSS. Test Mode Select: This input controls controller sampled rising edge TCK. Test Data This serial data input boundary scan testing. Test Data Out: This serial data output boundary scan testing. Core Power Supply: Connect 3.3V 2.5V. Power Supply: Connect 3.3V (only 3.3V devices) 2.5V. Ground: VSSQ connected inside chip. Connect: These pins connect chip.
Input
R/W# [a:d]#
Input Input
Input
[a:d]
Input/ Output Input
LBO#
Input
VDDQ VSS, VSSQ
Input Input Input Input Output Supply Supply Supply
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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72Mbit Pipelined BSRAM NoBL Architecture 2Mx36
Device Operation
SS2625 synchronous pipelined burst SRAM designed specifically eliminate wait states during write/read transitions. synchronous inputs pass through input registers controlled rising edge clock. clock signal qualified with Clock Enable input signal (CKE#). CKE# high, clock signal recognized internal states maintained. synchronous operations qualified with CKE#. data outputs pass through output registers controlled rising edge clock. Maximum access delay from clock rise (tCO) (166 device). Accesses initiated driving three chip enables (CE1#, CE2, CE3#) true rising edge clock. CKE# driven low, address presented device latched. access either read write, depending status R/W#. BW[a:d]# used perform byte write operations. Writes simplified with on-chip synchronous self-timed write circuitry. Three synchronous chip enables asynchronous Output Enable signal (G#) simplify depth expansion. Reads writes pipelined with two-clock cycle latency. must driven initiate transaction. reads writes burst operations. burst non-interruptible sequence four clock cycles. burst sequence determined state LBO# input signal. Driving LBO# provides linear burst order, driving high provides interleaved burst order.
Burst Read Accesses
burst read access initiated when following conditions satisfied clock rise: CKE# driven low; CE1#, CE2, CE3# driven true; R/W# driven high; driven low. address presented inputs A0-Ax latched into Address register presented memory core control logic. control logic recognizes read allows access specified address location. requested data allowed propagate data within (166 device) provided driven low. SS2625 on-chip burst counter that incremented rising edge clock when driven high. device sequences through four address locations each burst read access. Once burst sequence completed read access initiated described above. Reads pipelined such that data flows device every clock edge. burst counter uses burst sequence wraps around when incremented more than four times. burst order tables burst sequence. burst sequence determined state LBO# input signal. This signal strap must remain static during device operation.
Burst Write Accesses
burst write access initiated when following conditions satisfied clock rise: CKE# driven low; CE1#, CE2, CE3# driven true; R/W# driven low; driven low. address presented inputs A0-Ax loaded into Address register byte write signals latched into control logic block. next rising clock edge data lines automatically three-stated regardless state input signal. This allows external logic present data DQ[a:d]. next rising clock edge data presented DQ[a:d] inputs subset byte write operations, Write Cycle Description table details) latched into device stored into specified address location. Data written during write operation controlled BW[a:d]# signals. SS2625 provides byte write capability (see Write Cycle Description table details). Driving R/W# input with appropriate BW[a:d]# input selectively writes desired bytes. Bytes selected during byte write operation remain unaltered. synchronous self-timed write mechanism provided simplify write operations. Byte write capability included greatly simplify readEnhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com Copyright 2001 Enhanced Memory Systems. rights reserved. information contained herein subject change without notice.
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72Mbit Pipelined BSRAM NoBL Architecture 2Mx36
-modify-write sequences, which reduced simple byte write operations. Because SS2625 common device, data should driven into device while outputs active. should driven high before presenting data DQ[a:d] inputs. This three-states output drivers. safety precaution, DQ[a:d] automatically three-stated during data portion write, regardless state SS2625 on-chip burst counter that increments rising edge clock when driven high. device then sequences through four address locations. sequencing continues, this counter wraps around original location. appropriate BW[a:d]# inputs must driven each cycle write correct bytes data. burst sequence determined state LBO# input. Burst Order tables sequence. LBO# input signal strap must remain static during device operation.
Deselecting Device
Deselecting SS2625 accomplished deasserting chip enables while driving low. deselect process requires four clock cycles complete. When deselected device enters lower power state while still monitoring input signals detect access. deselect must occur least once every (for example: once every 1600 clock cycles 100MHz). DQ[a:d] pins automatically three-stated clocks after deselection.
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Preliminary Data Sheet Truth Table Operation Deselect Begin Read Continue Read Begin Write Continue Write Suspend Address Used External Next External Next Current
72Mbit Pipelined BSRAM NoBL Architecture 2Mx36
CKE#
R/W#
Notes
Notes: deselect cycle complete four clocks. True False. true when CE1# CE3# high. false when CE1# high CE3# high. Valid. During write cycles, BWX# inputs must valid (high low) throughout burst cycle. suspend occurs during read, remains active (low-Z). During write deselect cycles, remains high-Z state. write operations performed during suspend.
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72Mbit Pipelined BSRAM NoBL Architecture 2Mx36
Electrical Characteristics
Absolute Maximum Ratings Description Power Supply Voltage (3.3V device) Power Supply Voltage (2.5V device) Voltage with Respect Ground Operating Temperature (ambient) Storage Temperature Power Dissipation Symbol VDD3 VDD2 VIN, VOUT Tstg Value -0.5V +4.6V -0.5V +3.6V -0.5V VDDQ +0.5V -55°C +125°C -65°C +150°C (TQFP), (PBGA)
Output Current (I/O pins) IOUT 20mA Stresses greater than those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only, functional operation device these, other conditions above those listed operational section specification, implied. Exposure conditions absolute maximum ratings extended periods affect device reliability. Characteristics 70°C) Symbol VDD3 VDDQ3 VDD2 VDDQ2 VIHDQ VIH1 VIL1 VIH2 VIL2 VOH3 VOL3 VOH2 VOL2 II(L) IO(L) Parameter Power Supply Voltage Supply Voltage Power Supply Voltage Supply Voltage Input High Voltage pins) Input High Voltage (Input-only pins) Input Voltage Input High Voltage (Input-only pins) Input Voltage Output High Voltage (IOUT -4mA) Output Voltage (IOUT +8mA) Output High Voltage (IOUT -4mA) Output Voltage (IOUT +4mA) Input Leakage Current Output Leakage Current 3.135 2.375 2.375 2.375 -0.3 -0.3 Typical 3.465 3.465 2.625 2.625 VDDQ VDDQ VDDQ Units Notes
Notes: Applies SM2625Q SM2625B 3.3V devices. Applies SM2625Q1 SM2625B1 2.5V devices. VDDQ 3.3V VDDQ 2.5V
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Preliminary Data Sheet Capacitance 70°C) Symbol CI/O Parameter Input Capacitance Input/Output Capacitance Typical
72Mbit Pipelined BSRAM NoBL Architecture 2Mx36
Units
Notes
Test Load
INPUTS
OUTPUT
3.3V, timing tests 3.0V. VDDQ 2.5V timing tests 2.5V. both cases, input transit time must Input timings referenced (VH-VL) Output timings referenced (for VDDQ 3.3V, 1.5V VDDQ 2.5V, 1.25V). Equivalent Load
VDDQ OUTPUT VDDQ 2.5V VDDQ 3.3V
Including Scope
Package Thermal Characteristics Symbol Parameter Thermal Resistance (Junction Ambient) Thermal Resistance (Junction Case) TQFP PBGA Units °C/W °C/W Notes
Notes: Tested still with device soldered 4.25 1.125 inch, 4-layer printed circuit board. Tested initially after design process changes that affect these parameters. Value accounts thermal conduction through device leads solder balls.
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72Mbit Pipelined BSRAM NoBL Architecture 2Mx36
Operating Currents 70°C)
Value Symbol Parameter Operating Current Test Conditions Read Write Every Cycles Max., IOUT 1/tCK Max., Device Deselected, VIL, 1/tCK Max., Device Deselected, 0.3V VDDQ 0.3V, Max., Device Deselected, 0.3V VDDQ 0.3V, 1/tCK -7.5 Units
ISB1
Automatic Power Down Current-TTL Inputs Automatic Power Down Current-CMOS Inputs Automatic Power Down Current-CMOS Inputs
ISB2
ISB3
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72Mbit Pipelined BSRAM NoBL Architecture 2Mx36
Characteristics 70°C)
Clock Symbol tCKH tCKL Parameter Clock Cycle Time Clock High Time Clock Time -7.5 Units Notes
Notes: This parameter sampled 100% tested.
Clock Input Timing
tCKH tCKL
Input Setup Input Hold
Input
Input Setup Symbol tCKES tRWS tLDS tCES Parameter Address Setup Time Data Input Setup Time Clock Enable Setup Time R/W#, [a:d] Setup Time Setup Time Chip Enable Setup Time -7.5 Units Notes
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72Mbit Pipelined BSRAM NoBL Architecture 2Mx36
Input Hold Symbol tCKEH tRWH tLDH tCEH Parameter Address Hold Time Data Input Hold Time Clock Enable Hold Time R/W#, [a:d] Hold Time Hold Time Chip Enable Hold Time -7.5
Units
Notes
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Preliminary Data Sheet Output Timing
72Mbit Pipelined BSRAM NoBL Architecture 2Mx36
Read DS/Wr
Command
tCLZ tCHZ
Output Symbol tCHZ tCLZ tGHZ tGLZ Parameter Data Valid After Rise Output Valid Data Output Hold Clock High-Z Clock Low-Z High Output High-Z Output Low-Z -7.5 Units 1,2,3,4 1,2,3,4 1,2,4 1,2,4 Notes
Notes: test conditions assume signal transition time less, timing reference levels, input pulse levels, output loading shown Test Loads circuit diagram. tCHZ, tCLZ, tGHZ, tGLZ specified with test conditions shown Test Loads circuit diagram. Transition measured 200mV from steady-state voltage. given voltage temperature, tGHZ tCHZ less than tCLZ eliminate contention between SRAMs when sharing same data bus. These specifications imply contention condition, reflect parameters guaranteed over worst-case user conditions. device designed achieve High-Z prior Low-Z under same system conditions. This parameter sampled 100% tested.
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72Mbit Pipelined BSRAM NoBL Architecture 2Mx36
Timing Diagrams
Deselect-Read
Four Clocks Minimum
R/W#
Addr
Deselect-Write
Four Clocks Minimum
R/W#
Addr
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Preliminary Data Sheet Read-Write-Read
72Mbit Pipelined BSRAM NoBL Architecture 2Mx36
Four Clocks Minimum
Four Clocks Minimum
R/W#
Addr
tGHZ
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72Mbit Pipelined BSRAM NoBL Architecture 2Mx36
IEEE 1149.1 Serial Boundary Scan (JTAG)
SS2625 includes serial boundary scan Test Access Port (TAP) PGBA package only. included TQFP package. This port functions accordance with IEEE Standard 1149.1-1990, does have functions required full 1149.1 compliance. These functions excluded because they place added delay critical speed path SRAM. Note that controller functions manner that does conflict with operation other devices that 1149.1 fully compliant TAPs. operates using JEDEC standard 2.5V logic levels.
Disabling JTAG Feature
SS2625 operate without JTAG feature. disable controller, prevent clocking device. internally pulled unconnected. They alternately connected through pull-up resistor. should left unconnected. power-up device reset state, which does interfere with device operation.
Test Access Port (TAP) Test Clock (TCK)
test clock used only with controller. inputs captured rising edge TCK. outputs driven from falling edge TCK.
Test Mode Select (TMS)
input used give commands controller sampled rising edge TCK. allowable leave this unconnected used. This pulled internally.
Test Data (TDI)
used serially input information registers. connected input registers. Which register placed between determined instruction loaded into Instruction register. Controller State Diagram more information. internally pulled unconnected unused application. connected most significant (MSB) register.
Test Data-Out (TDO)
output used serially output information from registers. output active depending current state state machine. Controller State Diagram more information. output changes falling edge TCK. connected least significant (LSB) register.
Performing Reset
reset performed forcing high five rising edges TCK. This reset does affect operation SRAM performed while SRAM operating. power-up, reset internally ensure that comes high-z state.
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72Mbit Pipelined BSRAM NoBL Architecture 2Mx36
Registers
Registers connected between pins allow scanning data into SRAM test circuitry. Only register selected time through Instruction register. Data serially loaded through rising edge TCK, output through falling edge TCK.
Instruction Register
Three-bit instructions serially loaded into Instruction register. This register loaded when placed between pins shown Controller Block Diagram. power-up, Instruction register loaded with IDCODE instruction. also loaded with IDCODE instruction controller placed reset state described previous section "Performing Reset". When controller Capture-IR state, least significant bits loaded with binary "01" pattern allow fault isolation board level serial test data path.
Bypass Register
save time when serially shifting data through registers, sometimes advantageous skip certain chips. Bypass register single-bit register that placed between pin, allowing data shift through SRAM with minimal delay. Bypass register when Bypass instruction executed.
Boundary Scan Register
This 70-bit register connected input output pins SRAM. Several no-connect (NC) pins included Boundary Scan register reserve pins higher density devices. Boundary Scan register loaded with current states inputs outputs ring when controller enters Capture-DR state, then placed between pins when controller enters Shift-DR state. EXTEST, SAMPLE/PRELOAD, SAMPLE-Z instructions used capture contents ring. Boundary Scan Order table shows order which bits connected. Each corresponds bumps SRAM package. register connected TDI, connected TDO.
Identification (ID) Register
register loaded with vendor specific, 32-bit code during Capture-DR state when IDCODE command loaded Instruction register. IDCODE hardwired into SRAM shifted when controller Shift-DR state. register vendor code other information described Identification Register Definitions table.
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72Mbit Pipelined BSRAM NoBL Architecture 2Mx36 Instruction
Eight different instructions possible with 3-bit Instruction register. combinations listed Instruction Code table. Three these instructions listed RESERVED should used. other five instructions described below. controller used this SRAM fully compliant with 1149.1 conventions because some mandatory instructions fully implemented. controller cannot used load address, data, control signals into SRAM, cannot preload Input Output buffers. SRAM does implement 1149.1 instructions EXTEST, INTEST, PRELOAD portion SAMPLE/PRELOAD. Instead capture current states inputs outputs ring when these instructions executed. Instructions loaded into controller during Shift-IR state when Instruction register placed between TDO. During this state, instructions shifted through Instruction register through pins. execute instruction once shifted controller moved into Update-IR state.
EXTEST
EXTEST mandatory 1149.1 instruction that executed when Instruction register loaded with EXTEST, specified, implemented controller. Therefore, this device fully compliant with 1149.1 standard. However, controller does recognize all-0 instruction. When EXTEST instruction loaded into Instruction register, SRAM responds SAMPLE/PRELOAD instruction loaded. only difference that unlike SAMPLE/PRELOAD instruction, EXTEST places SRAM outputs high-Z state.
IDCODE
IDCODE instruction causes vendor specific, 32-bit code load into register. also places register between pins, allows shifting IDCODE device when controller enters Shift-DR state. IDCODE instruction loaded into Instruction register power when controller given TEST-LOGIC RESET state.
SAMPLE-Z
SAMPLE-Z instruction places Boundary Scan register between pins when controller enters Shift-DR state. also places SRAM outputs into high-Z state.
SAMPLE/PRELOAD
SAMPLE/Preload mandatory 1149.1 instruction. PRELOAD portion this instruction implemented, controller fully compliant with 1149.1 standard. When SAMPLE/PRELOAD instruction loaded into Instruction register, controller Capture-DR state, snapshot data input output pins captured Boundary Scan register. important point that controller clock operates frequency MHz, while SRAM clock operates more that magnitude faster. Because this, possible input output change during Capture-DR state. tries capture signal while transitioning (metastable state), device harmed, results guaranteed possibly repeatable. guarantee that Boundary Scan register captures correct value, signal must stable long enough meet controller capture set-up hold times (tCS tCH). capture SRAM clock input correctly there must stop slow) clock during SAMPLE/PRELOAD instruction. this done design, still possible capture other signals simply ignore value captured Boundary Scan register.
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72Mbit Pipelined BSRAM NoBL Architecture 2Mx36
Once data captured, possible shift data putting into Shift-DR state. This places Boundary Scan register between pins. Note that since PRELOAD part this instruction implemented, putting into Update Update-DR state while performing SAMPLE/PRELOAD instruction same effect Pause-DR instruction.
BYPASS
When BYPASS instruction loaded Instruction register placed Shift-DR state, Bypass register placed between pins. advantage BYPASS instruction that shortens boundary scan path when multiple devices connected together board.
RESERVED
These instructions implemented reserved future use. these instructions.
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72Mbit Pipelined BSRAM NoBL Architecture 2Mx36
Controller State Diagram
TEST-LOGIC RESET
TEST-LOGIC/ IDLE
SELECT DR-SCAN
SELECT IR-SCAN
CAPTURE-DR
CAPTURE-IR
SHIFT-DR
SHIFT-IR
EXIT1-DR
EXIT1-IR
PAUSE-DR
PAUSE-IR
EXIT2-DR
EXIT2-IR
UPDATE-DR
UPDATE-IR
NOTE: next each state represents signal value rising edge TCK.
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Preliminary Data Sheet Controller Block Diagram
72Mbit Pipelined BSRAM NoBL Architecture 2Mx36
Bypass Register
Instruction Register Selection Circuitry
Selection Circuitry
Identification Register
Boundary Scan Register
Controller
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72Mbit Pipelined BSRAM NoBL Architecture 2Mx36
Electrical Characteristics Symbol VOH1 VOH2 VOL1 VOL2 Parameter Output High Voltage Output High Voltage Output Voltage Output Voltage Input High Voltage Input Voltage Input Output Leakage Current Test Conditions -2.0 -100 VDDQ -0.3 VDD+0.3
Units
Notes
Notes: voltage referenced ground. Overshoot: VIH(AC) VDD+0.7V (tTCYC Undershoot: VIL(AC) 0.5V (tTCYC Power 2.6V VDD<2.4V VDDQ<1.4 t<200ms.
Switching Characteristics Symbol tTCYC tTMSS tTDIS tTMSH tTDIH tTDOV tTDOX Clock Cycle Time Clock Frequency Clock High Clock Setup Clock Rise Setup Clock Rise Capture Setup Clock Rise Hold after Clock Rise Hold after Clock Rise Capture Hold after Clock Rise Clock Valid Clock Invalid Parameter Units Notes
Notes: Test conditions specified using loads test conditions. tR/tF refer setup hold time requirements latching data from Boundary Scan register.
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Preliminary Data Sheet Timing Test Conditions
72Mbit Pipelined BSRAM NoBL Architecture 2Mx36
1.25V Input Pulses 2.5V 1.25V
tTCYC
Test Clock
tTMSS tTMSH
Test Mode Select
tTDIS tTDIH
Test Data-In
tTDOV tTDOX
Test Data-Out
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72Mbit Pipelined BSRAM NoBL Architecture 2Mx36
Boundary Scan Order Scan Signal Name LBO# Location Scan Signal Name CKE# R/W# CE3# CE1# Location Scan Signal Name
Location
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Preliminary Data Sheet Identification Register Definitions Instruction Field Revision Number (31:29) Voltage (28,24) Reserved (27:25) Architecture (23:21) Memory Type (20:18) Width (17:15) Density (14:12) JEDEC Code (11:1) Register Presence Value 0011 0010 Defines revision number.
72Mbit Pipelined BSRAM NoBL Architecture 2Mx36
Description
Defines voltage SRAM (3.3V) (2.5V). Reserved. Defines SRAM architecture (NoBL). Defines type SRAM (pipelined burst Defines width SRAM. Defines density SRAM (64M/72M). Unique identification SRAM vendor Enhanced Memory Systems). Indicates presence register.
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72Mbit Pipelined BSRAM NoBL Architecture 2Mx36
Scan Register Sizes Register Name Instruction Bypass Boundary Scan Size
Instruction Codes Instruction EXTEST Code Description Captures input/output states. Places Boundary Scan register between TDO. Forces SRAM outputs high-Z state. This instruction 1149.1 compliant. Loads register with vendor code places register between TDO. This operation does affect SRAM operation. Captures input/output states. Places Boundary Scan register between TDO. Forces SRAM output drivers high-Z state Use: This instruction reserved future use. Captures input/output states. Places Boundary Scan register between TDO. Does affect SRAM operation. This instruction does implement 1149.1 preload function therefore 1149.1 compliant Use: This instruction reserved future use. Use: This instruction reserved future use. Places Bypass register between TDO. Does affect SRAM operation.
IDCODE SAMPLE RESERVED SAMPLE/PRELOAD
RESERVED RESERVED BYPASS
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
Copyright 2001 Enhanced Memory Systems. rights reserved. information contained herein subject change without notice.
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72Mbit Pipelined BSRAM NoBL Architecture 2Mx36
Mechanical Drawings
Package Dimensions (100-pin TQFP)
22.00 0.20 20.00 0.20
14.00 0.20 16.00 0.20
I.D. 1.60
1.40 0.05
0.05/0.15 (Min/Max) 0.22 0.35 0.65 Basic
1.60
0.25 Seating Plane 0.10 Lead Coplanarity 0.20 0.60 0.15/-0.10 dimensions millimeters Conforms JEDEC MS-026/Variation
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
Copyright 2001 Enhanced Memory Systems. rights reserved. information contained herein subject change without notice.
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72Mbit Pipelined BSRAM NoBL Architecture 2Mx36
Package Dimensions (119-bump PBGA)
View
Bottom View
20.32 1.27
22.0
14.0
1.27 7.62
Side View
2.40
±0.1
1.50 ±0.2
dimensions millimeters Conforms JEDEC MS-028, variation
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
Copyright 2001 Enhanced Memory Systems. rights reserved. information contained herein subject change without notice.
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72Mbit Pipelined BSRAM NoBL Architecture 2Mx36
Revision
Revision Date 10/11/01 Initial release. Summary Changes
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
Copyright 2001 Enhanced Memory Systems. rights reserved. information contained herein subject change without notice.
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72Mbit Pipelined BSRAM NoBL Architecture 2Mx36 Ordering Information
Part Number SS2625Q-6 SS2625Q-7.5 SS2625Q-10 SS2625B-6 SS2625B-7.5 SS2625B-10 SS2625Q1-6 SS2625Q1-7.5 SS2625Q1-10 SS2625B1-6 SS2625B1-7.5 SS2625B1-10
Power Supply 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V
Package 100-pin TQFP 100-pin TQFP 100-pin TQFP 119-ball PBGA 119-ball PBGA 119-ball PBGA 100-pin TQFP 100-pin TQFP 100-pin TQFP 119-ball PBGA 119-ball PBGA 119-ball PBGA
Type LVTTL, 2.5V LVTTL, 2.5V LVTTL, 2.5V LVTTL, 2.5V LVTTL, 2.5V LVTTL, 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V
Maximum Operating Frequency (MHz)
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
Copyright 2001 Enhanced Memory Systems. rights reserved. information contained herein subject change without notice.
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Enhanced Memory Systems SS2625 72-Mbit synchronous pipelined burst SRA

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