72Mbit Density Clock Rate, 600Mbps Data Rate Latency Cached DRAM Archi

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72Mbit Density Clock Rate, 600Mbps Data Rate Latency Cached DRAM Archi

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72Mbit ESRAM 2Mx36
72Mbit Density Clock Rate, 600Mbps Data Rate Latency Cached DRAM Architecture Selectable Read/Write Latency Burst Length Eight Coherent Late Writes Single 2.5V Power Supply Power 1.5V HSTL Interface Differential Echo Clock Outputs Programmable Output Impedance Drivers JEDEC Standard 209-ball PBGA Package Body Size Ball Pitch, Array 1.65 (max) Package Height
Description
Enhanced Memory Systems SS2615 ESRAM 72Mbit double data rate memory device that combines high speed signalling interface with innovative memory architecture optimize system price/performance high performance cache memory communications systems. device packaged JEDEC standard 209-ball plastic BGA. SS2615 achieves bandwidth GB/s while maintaining initial access 13.3ns. equivalent serial data rate 21.6 Gb/s. memory arrays organized sixteen independent banks, which allow pseudorandom address cycle time 13.3
FUNCTIONAL BLOCK DIAGRAM
WORD LINE DRIVERS
A(2:0) R/W#
ADDRESS CONTROL DECODERS, BURST COUNTER
2Mx36 Memory Array
TIMING GENERATOR
SENSE AMPLIFIERS
COLUMN DECODE READ/WRITE CACHES
OUTPUT REGISTERS BUFFERS
DATA LATCHES
TCK, TMS, TDI,
BOUNDARY SCAN
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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72Mbit ESRAM 2Mx36 Assignments (Top View)
SS2615 2Mx36 209-ball PBGA
VDDQ
VREF
VDDQ
VDDQ
VDDQ
R/W#
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NOTE: Location expansion address future 144Mb device.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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72Mbit ESRAM 2Mx36
Descriptions
Symbol
Type
Input Input
Function
Input Clock: input signals sampled rising edge falling edge CK#, where voltage levels cross. Chip Select: This active synchronous input registered when low, otherwise ignored. When registered chip select registered low, chip begins read write cycle. When registered chip select registered high, chip begins deselect cycle. Load Address: Active latches address, decodes R/W#. When registered high, device internally increments A(2:0) address that initially latched. Read/Write Input: This signal determines whether start read write cycle only when both registered low. Burst Address Inputs: These inputs registered when low, otherwise they ignored. They define starting address. burst wrap sequence defined Burst Wrap Sequence Table. Address Inputs: These address inputs registered when low, otherwise they ignored. bank address pins determine which sixteen internal banks accessed. Data I/O: Data inputs outputs. read cycles, device drives output data these pins after read latency satisfied. Read data edge aligned with output clocks CQ#. completion burst read cycle, device automatically places output buffers hi-Z. write cycles, input data applied these pins must set-up held relative rising falling edge clock Output Clock: These free running output clocks used capture read data memory controller using timing reference. Read data driven pins valid rising falling edges CQ#, where voltage levels cross. Output Impedance Control: resistor must connected between VSS. resistor value defines output driver impedance. must chosen such that times desired driver impedance. Mode Input: This static input defines read/write latency. high, read/write latency clocks. low, read/write latency clocks. Test Clock: Input clock boundary scan. boundary scan used, must tied either VSS. Test Mode Select: This input controls controller sampled rising edge TCK. Test Data This serial data input boundary scan testing. Test Data Out: This serial data output boundary scan testing. Reference power supply input buffers. Power (+2.5V) ground input buffers core logic. Isolated power supply interface (DQ). VDDQ must connected 1.5V power. Connect: These pins connect chip.
R/W# A(2:0)
Input Input Input
Input
Input/ Output
Output
Input
VREF VDD, VDDQ
Input Input Input Input Output Supply Supply Supply
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72Mbit ESRAM 2Mx36
Device Operation
Enhanced Memory Systems SS2615 ESRAM DRAM-based SRAM equivalent. device burstable read/write memory with double data rate (DDR) interface. Read write transactions always have burst length eight. Burst cycles cannot interrupted. Once burst length satisfied, device automatically hi-Z's data reads ignores data writes. selects initial read write data latency either clocks clocks. device internally organized sixteen banks. This allows most accesses serviced four clock boundaries since only timing constraint imposed alternate bank accesses that ensures read write bursts interrupted.
Burst Read Accesses
read cycle initiated rising edge clock when registered R/W# registered high. first beat read data driven data low) high) clocks following read address. Output data valid coincident with output clocks CQ#. improved data signal integrity, eighth beat read data extended extra data phase. exception this rule occurs when alternate bank read access allows back-to-back read bursts without interruption. Timing Diagrams section details.
Burst Write Accesses
write cycle initiated when CS#, LD#, R/W# registered rising edge clock Write data latency clocks dependent setting. Input data referenced device's input clocks CK#.
Burst Wrap Sequence Start Address Interleaved (decimal)
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Preliminary Data Sheet Programmable Latency Pin)
72Mbit ESRAM 2Mx36
Command
Read Latency
Write Latency
Command
Read Latency
Write Latency
high
Device Deselect (Refresh)
deselect cycle initiated when registered high registered low. address inputs ignored. Once Deselect command issued, device unavailable read write cycle until minimum bank cycle time satisfied (tRC). requirement 4,096 deselect cycles every necessary maintain data integrity memory arrays. This corresponds Deselect commands being evenly distributed every Since some system designs require flexibility timing Deselect commands, device allows reduced time interval between Deselect commands. Output buffer (DQ) impedance updates occur during deselect cycles.
Operation
Once burst cycle completes registered high rising edge clock device performs operation cycle.
Truth Table Operation Burst Read Burst Write Device Deselect Operation
R/W#
Address Start Address Start Address
Action Start bursting data clock. Start bursting data clock. Refresh cycle begins completes clocks. burst complete, device remains idle.
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72Mbit ESRAM 2Mx36
Electrical Characteristics
Absolute Maximum Ratings
Description Power Supply Voltage Power Supply Voltage Voltage with Respect Ground Junction Temperature Storage Temperature Output Current (I/O pins) Symbol VDDQ VIN, VOUT TSTG IOUT Value -0.5V +3.5V -0.5V +2.5V, where VDDQ VDD+0.5V -0.5V +2.65V 110°C -55°C +125°C ±50mA
Stresses greater than those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only, functional operation device these, other conditions above those listed operational section specification, implied. Exposure conditions absolute maximum ratings extended periods affect device reliability.
Characteristics +70°C)
Symbol VDDQ VREF IILK IOLK Supply Voltage Supply Voltage Input High Voltage (excluding CK,CK#) Input Voltage (excluding CK#) Clock Input Voltage Clock Input Differential Voltage Clock Input Common Mode Voltage Range Input Reference Voltage Input Leakage Current Output Leakage Current Output High Current VDDQ/2, Output Current VDDQ/2, Parameter VREF+0.1 -0.3 -0.3 0.68 0.68 12.5 12.5 Typical 2.65 VREF-0.1 0.85 0.85 18.0 18.0 Units Notes
Notes: minimum -0.7V 1ns. test limits intended guarantee value driver output impedance ohms 10%. Minimum limit defined [(VDDQ 10%)]. Maximum limit defined [(VDDQ 10%)]. max. equal max. clock signal minus min. other clock signal.
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Power Supply Currents +70°C, 2.4V 2.65V)
-3.3 Symbol Parameter Average Operating Current (Read/Write command every clocks, accessing alternate internal banks) Standby Current Read/Write commands, Deselect command issued every -4.0 Units Notes
Package Thermal Characteristics Symbol Parameter Thermal Resistance (Junction Ambient) Thermal Resistance (Junction Case) Value Units °C/W °C/W Notes
Notes: Tested still with device soldered 4.25 1.125 inch, 4-layer printed circuit board. Tested initially after design process changes that affect these parameters. Value accounts thermal conduction through solder balls.
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Test Conditions +70°C)
tSETUP tHOLD Input Output tCQD Output Load Curcuit VREF CLOAD 20pF
initial pause 500µs required after power-up. test output timings referenced (VDDQ inputs VDDQ, VREF 0.75V, input timings referenced VREF transition time measured between 80%. test measurements assume 0.5ns. addition meeting transition rate specification, clock must transit between between monotonic manner. Access time first data word following hi-Z condition guaranteed only from (VDDQ condition, also from VDDQ condition well.
Capacitance 25°C, 100MHz, 2.4V 2.65V, VDDQ 1.5V 0.1V) Symbol Parameter Input Clock Capacitance (CK, CK#) Input Capacitance (Address, Control) Output Capacitance (DQ) VREF Input Capacitance Typical Units Notes
Notes: Value includes package capacitance.
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Operating Conditions +70°C)
Clock -3.3 Symbol tCKH tCKL tCKDC tCQD Clock Frequency Clock Cycle Time Clock High Time Clock Time Clock Duty Cycle Clock Clock Delay Time Parameter 3.33 -4.0 Units Notes
Notes: Access time measured (VDDQ Test Load. Assumes clock rise fall times equal 0.5ns.
Clock Input Timing
tCKH tCKL
Input Setup Input Hold
Input
tCQD
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Common Parameters -3.3 Symbol tRC1 tRC2 tREF Parameter Command Address Set-Up Time Command Address Hold Time Read/Write Bank Cycle Time low) Read/Write Bank Cycle Time high) Deselect Time Interval 0.33 26.6 33.3 32.0 40.0 -4.0 Units Notes
Notes: When low, read/write latencies four clocks. When high, read/write latencies clocks. memory controller must issue least 4,096 deselect commands every
Read Write Parameters -3.3 Symbol Parameter Clock Access Time (ref Output Hold Time (ref Output Rise/Fall Time Data Input Set-Up Time Data Input Hold Time -0.33 0.33 0.33 0.33 -0.4 -4.0 Units Notes
Notes: Access time measured (VDDQ Test Load. Assumes clock rise fall times equal 0.5ns. Based measurement. Guaranteed design characterization.
Read Parameter Timing
tCQD
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Timing Diagrams
Burst Reads (Latency
RCBank Cycle Time Bank Cycle Time
R/W# Addr
Read Latency
Alternate Bank, Same bank Data phase extended uninterrupted Burst Read cycles
automatically goes hi-Z after Burst Read note extended data phase
Burst Writes (Latency
Bank Cycle Time
R/W# Addr
Write Latency Write Latency Write Latency
Alternate Bank, Same bank
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72Mbit ESRAM 2Mx36 Burst Read/Write/Read (Latency
Bank Cycle Time
R/W# Addr
Read Latency Write Latency
Alternate Bank, Same bank
RCBank Cycle Time
R/W# Addr
Read Latency Write Latency Read Latency
Alternate Bank, Same bank
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Deselect (Refresh) Cycle between Random Reads
RCBank Cycle Time Bank Cycle Time
R/W# Addr
Read Latency Read Latency
Power-Up Initialization
min.
max.
min.
clocks min.
R/W# Addr VDDQ VREF
stable CQ/CQ# both toggle (follow CK/CK#), however output buffers default highest condition, proper switching parameters valid. driven low, driven high while CK/CK# both low.
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72Mbit ESRAM 2Mx36
IEEE 1149.1 Serial Boundary Scan (JTAG)
SS2615 includes serial boundary scan Test Access Port (TAP). This port functions accordance with IEEE Standard 1149.1-1990, does have functions required full 1149.1 compliance. These functions excluded because they place added delay critical speed path device's inputs outputs. Note that controller functions manner that does conflict with operation other devices that 1149.1 fully compliant TAPs.
Disabling JTAG Feature
SS2615 operate normally without using JTAG feature. power-up, controller placed reset state does interfere with device operation. ensure controller disabled, either VDD. This prevents controller from operating even toggles.
Test Access Port (TAP) Test Clock (TCK)
test clock used only with controller. inputs captured rising edge TCK. outputs driven from falling edge TCK.
Test Mode Select (TMS)
input used give commands controller sampled rising edge TCK. allowable leave this unconnected used. This pulled internally.
Test Data (TDI)
used serially input information registers. connected input registers. Which register placed between determined instruction loaded into Instruction register. Controller State Diagram more information. internally pulled unconnected unused. connected most significant (MSB) register.
Test Data-Out (TDO)
output used serially output information from registers. output active depending current state state machine. Controller State Diagram more information. output changes falling edge TCK. connected least significant (LSB) selected register. JTAG feature used, should left unconnected.
Performing Reset
reset performed forcing high five rising edges TCK. This reset does affect operation device performed while device operating. power-up, reset internally ensure that comes high-Z state.
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Registers
Registers connected between pins allow scanning data into SS2615 test circuitry. Only register selected time through Instruction register. Data serially loaded through rising edge driven through falling edge TCK.
Instruction Register
Three-bit instructions serially loaded into Instruction register. This register loaded when placed between pins shown Controller Block Diagram. power-up, Instruction register loaded with IDCODE instruction. also loaded with IDCODE instruction controller placed reset state described previous section "Performing Reset". When controller placed Capture-IR state, least significant bits loaded with binary "01" pattern allow fault isolation board level serial test data path.
Bypass Register
save time when serially shifting data through registers, sometimes advantageous skip certain chips. Bypass register single-bit register that placed between pin, allowing data shift through device with minimal delay. Bypass register when Bypass instruction executed.
Boundary Scan Register
This register connected input output pins SS2615. Boundary Scan register loaded with current states inputs outputs ring when controller enters Capture-DR state. register then serially placed between pins when controller enters Shift-DR state. EXTEST, SAMPLE/PRELOAD, SAMPLE-Z instructions used capture contents ring. Boundary Scan Order table shows order which bits connected. Each corresponds solder balls package. register connected TDI, connected TDO.
Identification (ID) Register
register loaded with vendor specific, 32-bit code during Capture-DR state when IDCODE command loaded Instruction register. IDCODE hardwired into device shifted when controller placed Shift-DR state. register vendor code other information described Identification Register Definitions table.
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72Mbit ESRAM 2Mx36 Instruction
Eight different instructions possible with 3-bit Instruction register. combinations listed Instruction Code table. Three these instructions listed RESERVED should used. other five instructions described below. controller used this device fully compliant with 1149.1 conventions because some mandatory instructions fully implemented. controller cannot used load address, data, control signals into ESRAM, cannot preload Input Output buffers. This device does implement following instructions specified 1149.1 standard: EXTEST, INTEST, PRELOAD portion SAMPLE/PRELOAD. Instead captures current states inputs outputs ring when these instructions executed. Instructions loaded into controller during Shift-IR state when Instruction register placed between TDO. During this state, instructions shifted through Instruction register through pins. execute instruction once shifted controller moved into Update-IR state.
EXTEST
When EXTEST instruction loaded into Instruction register, SS2615 places outputs (DQ, CQ#) into high-Z state. EXTEST instruction executed when Instruction register loaded with 0's. EXTEST instruction places Boundary Scan register between pins when controller enters Shift-DR state. When controller placed Capture-DR state, snapshot data input output pins captured Boundary Scan register. CK#, pins each captured singleended. EXTEST mandatory 1149.1 instruction. EXTEST implemented controller specified 1149.1 standard. Therefore, this device fully compliant with 1149.1 standard.
IDCODE
IDCODE instruction causes vendor specific, 32-bit code load into register. also places register between pins, allows shifting IDCODE device when controller enters Shift-DR state. IDCODE instruction loaded into Instruction register power when controller given TEST-LOGIC RESET state.
SAMPLE-Z
SAMPLE-Z instruction places Boundary Scan register between pins when controller enters Shift-DR state. also places outputs (DQ, CQ#) into high-Z state.
SAMPLE/PRELOAD
When SAMPLE/PRELOAD instruction loaded into Instruction register controller placed Capture-DR state, snapshot data input output pins captured Boundary Scan register. Note that controller clock operates frequency MHz, while main clocks CK/CK# operate more than order magnitude faster. Because this, possible input output change during Capture-DR state. tries capture signal while transitioning (metastable state), device harmed, results guaranteed possibly repeatable. guarantee that Boundary Scan register captures correct value, signal must stable long enough meet controller capture set-up hold times (tCS tCH). capture clock inputs correctly, there must
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stop slow) clock during SAMPLE/PRELOAD instruction. this done design, still possible capture other signals simply ignore value CK/CK# captured Boundary Scan register. Once data captured, possible shift data putting into Shift-DR state. This places Boundary Scan register between pins. SAMPLE/PRELOAD mandatory 1149.1 instruction. PRELOAD portion this instruction implemented, controller fully compliant with 1149.1 standard. Note that since PRELOAD part this instruction implemented, placing into Update-DR state while performing SAMPLE/PRELOAD instruction same effect Pause-DR instruction.
BYPASS
When BYPASS instruction loaded Instruction register placed Shift-DR state, Bypass register placed between pins. advantage BYPASS instruction that shortens boundary scan path when multiple devices connected together board.
RESERVED
These instructions implemented reserved future use. these instructions.
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Controller State Diagram
TEST-LOGIC RESET
TEST-LOGIC/ IDLE
SELECT DR-SCAN
SELECT IR-SCAN
CAPTURE-DR
CAPTURE-IR
SHIFT-DR
SHIFT-IR
EXIT1-DR
EXIT1-IR
PAUSE-DR
PAUSE-IR
EXIT2-DR
EXIT2-IR
UPDATE-DR
UPDATE-IR
NOTE: next each state represents signal value rising edge TCK.
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Preliminary Data Sheet Controller Block Diagram
72Mbit ESRAM 2Mx36
Bypass Register
Instruction Register Selection Circuitry
Selection Circuitry
Identification Register
Boundary Scan Register
Controller
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Electrical Characteristics Symbol Parameter Output High Voltage Output Voltage Input High Voltage Input Voltage Input Output Leakage Current Test Conditions -2.0 -0.3 VDD+0.3 Units Notes
Notes: voltage referenced ground. Overshoot: VIH(AC) VDD+0.5V (tTCYC Undershoot: VIL(AC) 0.5V (tTCYC Value accounts input pullups pins.
Switching Characteristics Symbol tTCYC tTMSS tTDIS tTMSH tTDIH tTDOV tTDOX Clock Cycle Time Clock Frequency Clock High Clock Setup Clock Rise Setup Clock Rise Capture Setup Clock Rise Hold after Clock Rise Hold after Clock Rise Capture Hold after Clock Rise Clock Valid Clock Invalid Parameter Units Notes
Notes: Test conditions specified using loads test conditions. tR/tF refer setup hold time requirements latching data from Boundary Scan register.
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Preliminary Data Sheet Timing Test Conditions
72Mbit ESRAM 2Mx36
1.2V Input Pulses 2.5V 1.2V
tTCYC
Test Clock
tTMSS tTMSH
Test Mode Select
tTDIS tTDIH
Test Data-In
tTDOV tTDOX
Test Data-Out
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72Mbit ESRAM 2Mx36
Boundary Scan Order Scan Signal Name R/W# Location Scan Signal Name Location Scan Signal Name Location
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Preliminary Data Sheet Identification Register Definitions Instruction Field Revision Number (31:29) Voltage (28,24) Reserved (27:25) Architecture (23:21) Memory Type (20:18) Width (17:15) Density (14:12) JEDEC Code (11:1) Register Presence Value 0011 0010 Defines revision number. Defines voltage (2.5V). Reserved. Defines ESRAM architecture Defines type ESRAM (burst Defines width (x36) Defines density (64M/72M) Description
72Mbit ESRAM 2Mx36
Unique identification SRAM vendor Enhanced Memory Systems) Indicates presence register
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Scan Register Sizes Register Name Instruction Bypass Boundary Scan Size
Instruction Codes Instruction EXTEST Code Description Captures input/output states. Places Boundary Scan register between TDO. Forces outputs high-Z state. This instruction 1149.1 compliant. Loads register with vendor code places register between TDO. This operation does affect device operation. Captures input/output states. Places Boundary Scan register between TDO. Forces output drivers high-Z state. Use: This instruction reserved future use. Captures input/output states. Places Boundary Scan register between TDO. Does affect device operation. This instruction does implement 1149.1 preload function therefore 1149.1 compliant. Use: This instruction reserved future use. Use: This instruction reserved future use. Places Bypass register between TDO. Does affect device operation.
IDCODE SAMPLE RESERVED SAMPLE/PRELOAD
RESERVED RESERVED BYPASS
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Mechanical Drawings
Package Dimensions (209-ball PBGA)
View
Bottom View
Index
22.0
18.0
14.0
10.0
Side View
1.65 Max. 1.35 Min.
dimensions millimeters Conforms JEDEC MS-028C, variation Drawings scale
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Revision
Revision 0.93C 0.94C Date 7/18/01 9/7/01 Summary Changes Commercial grade temperature spec. Added Boundary Scan Order table.
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Ordering Information
Part Number SS2615B-3.3 SS2615B-4.0 Latencies Width Type 1.5V HSTL 1.5V HSTL Package 209-ball PBGA 209-ball PBGA Power Supply 2.5V 2.5V Clock Frequency (MHz)
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72Mbit Density Clock Rate, 600Mbps Data Rate Latency Cached DRAM Archi

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