3.3V pipeline burst synchronous SRAM Asynchronous output enable c

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3.3V pipeline burst synchronous SRAM Asynchronous output enable c

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AS7C331MPFD18A
3.3V pipeline burst synchronous SRAM
Asynchronous output enable control Organization: 1,048,576 18bits Economical 100-pin TQFP package Fast clock speeds 200MHz LVTTL/LVCMOS Also offered 119-Ball Ball Grid Array Package) Fast clock data access: 3.0/3.5/4.0 Byte write enables Fast access time: 3.0/3.5/4.0 Multiple chip enables easy expansion Fully synchronous register-to-register operation core power supply Single register "Flow-through" mode 2.5V 3.3V operation with separate VDDQ Dual-cycle deselect Single-cycle deselect also available AS7C331MPFS18A NTDpipeline architecture available (AS7C331MNTD18A Pentium®* compatible architecture timing Pentium® registered trademark Intel Corporation. NTDis trademark
Alliance Semiconductor Corporation. trademarks mentioned this document property their respective owners.
Features
Logic Block Diagram:
ADSC ADSP A[19:0] Address register Burst logic
Arrangements:
1Mx18 Memory array N.C. N.C. N.C. VDDQ VSSQ N.C. N.C. VSSQ VDDQ VDDQ VSSQ N.C. VSSQ VDDQ N.C. N.C. N.C. ADSC ADSP
Byte write registers Byte write registers Byte write registers Byte write registers Enable register Power down Enable delay register
TQFP
Output registers
Input registers
DATA [17:0]
Selection guide
Minimum cycle time Maximum clock frequency Maximum pipelined clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC)
-200
-166
N.C. N.C. VDDQ VSSQ N.C. VSSQ VDDQ VDDQ VSSQ N.C. N.C. VSSQ VDDQ N.C. N.C. N.C.
-100
Units
10/5/01; v.0.9.1
Alliance Semiconductor
Copyright Alliance Semiconductor. rights reserved.
AS7C331MPFD18A
Configuration
View
VDDQ VDDQ VDDQ VDDQ VDDQ
DQPb
ADSP ADSC
DQPa
VDDQ VDDQ VDDQ VDDQ VDDQ
10/5/01; v.0.9.1
Alliance Semiconductor
Copyright Alliance Semiconductor Corporation. rights reserved. three-point logo, name Intelliwatt trademarks registered trademarks Alliance. other brand product names trademarks their respective companies. Alliance reserves right make changes this document products time without notice. Alliance assumes responsibility errors that appear this document. data contained herein represents Alliance's best data and/or estimates time issuance. Alliance reserves right change correct this data time, without notice. product described herein under development, significant changes these specifications possible. information this product data sheet intended general descriptive information potential customers users, intended operate provide, guarantee warrantee user customer. Alliance does assume responsibility liability arising application product described herein, disclaims express implied warranties related sale and/or Alliance products including liability warranties related fitness particular purpose, merchantability, infringement intellectual property rights, except express agreed Alliance's Terms Conditions Sale (which available from Alliance). sales Alliance products made exclusively according Alliance's Terms Conditions Sale. purchase products from Alliance does convey license under patent rights, copyrights, mask works rights, trademarks, other intellectual property rights Alliance third parties. Alliance does authorize products critical components life-supporting systems where malfunction failure reasonably expected result significant injury user, inclusion Alliance products such life-supporting systems implies that manufacturer assumes risk such agrees indemnify Alliance against claims arising from such use.

3.3V pipeline burst synchronous SRAM Asynchronous output enable c

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