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AS7C33512PFS32A AS7C33512PFS36A

Pentium® is a registered trademark of Intel Corporation. NTD is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property of their respective owners.

October 2001 Advanced Information
AS7C33512PFS32A AS7C33512PFS36A
· Organization: 524, 288 words x 32 / 36 bits · Fast clock speeds to 200MHz in LVTTL / LVCMOS · Fast clock to data access: 3.0 / 3.5 / 4.0 ns · Fast OE access time: 3.0 / 3.5 / 4.0 ns · Fully synchronous register-to-register operation · Single register "Flow-through" mode · Single-cycle deselect - Dual-cycle deselect also available ( AS7C33512PFD32A / AS7C33512PFD36A) · Pentium® compatible architecture and timing · Asynchronous output enable control · 100-pin TQFP package · 119-Ball BGA (7 x 17 Ball Grid Array Package) · Byte write enables · Multiple chip enables for easy expansion · 3.3 core power supply · 2.5V or 3.3V I / O operation with separate VDDQ · NTDTM pipeline architecture available (AS7C33512NTD32A / AS7C33512NTD36A)
Pentium® is a registered trademark of Intel Corporation. NTD is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property of their respective owners.
Logic Block Diagram:
LBO CLK ADV ADSC ADSP 19 CLK CE CLR D CE Address register CLK D Q0 Burst logic Q1 18 Q
Pin Arrangement:
A6 A7 CE0 CE1 BWd BWc BWb BWa CE2 VDD VSS CLK GWE BWE OE ADSC ADSP ADV A8 A9 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
GWE BWE BWd
DQd Q Byte write registers CLK D DQc Q Byte write registers CLK DQb Q Byte write registers CLK D DQa Q Byte write registers CLK D Enable CE register CLK Power down D Enable Q delay register CLK Q D
BWa CE0 CE1 CE2
OE Output registers CLK
Input registers CLK
FT DATA 35:0 DATA 31:0
Selection guide
Minimum cycle time Maximum clock frequency Maximum pipelined clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC)
LBO A5 A4 A3 A2 A1 A0 NC NC VSS VDD A18 A17 A10 A11 A12 A13 A14 A15 A16
DQPc / NC DQc DQc VDDQ VSSQ DQc DQc DQc DQc VSSQ VDDQ DQc DQc FT VDD NC VSS DQd DQd VDDQ VSSQ DQd DQd DQd DQd VSSQ VDDQ DQd DQd DQPd / NC
DQPb / NC DQb DQb VDDQ VSSQ DQb DQb DQb DQb VSSQ VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSSQ DQa DQa DQa DQa VSSQ VDDQ DQa DQa DQPa / NC
Units ns MHz ns mA mA mA
10 / 4 / 01 v.0.9.4
Alliance Semiconductor
AS7C33512PFS32A AS7C33512PFS36A
Pin Configuration
119 BGA Top View
1 VDDQ NC
DQC DQC VDDQ DQC DQC VDDQ DQd DQd VDDQ DQd DQd NC NC VDDQ
2 A A A DQPc DQc DQc DQc DQc VDD DQd DQd DQd DQd DQpd A NC TMS
ADSP ADSC
VDD NC
CE0 OE ADV GWE
VSS NC VSS
VDD CLK NC
VSS NC VSS
VSS VSS VSS
A1 A0 VDD A TCK
VSS VSS VSS VDD A TDO
6 A A A DQpb DQb DQb DQb DQb VDD DQa DQa DQa DQa DQPa A NC NC
7 VDDQ NC NC DQb DQb VDDQ DQb DQb VDDQ DQa DQa VDDQ DQa DQa NC ZZ VDDQ
Note: For P / N AS7C33512PFS32A, 4 of the I / O Pins must be left open (N.C.)
10 / 4 / 01 v.0.9.4
Alliance Semiconductor