3.3V 512K 32/36 pipeline burst synchronous SRAM Features Organiza

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3.3V 512K 32/36 pipeline burst synchronous SRAM Features Organiza

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AS7C33512PFS32A AS7C33512PFS36A
3.3V 512K 32/36 pipeline burst synchronous SRAM Features
Organization: 524,288 words 32/36 bits Fast clock speeds 200MHz LVTTL/LVCMOS Fast clock data access: 3.0/3.5/4.0 Fast access time: 3.0/3.5/4.0 Fully synchronous register-to-register operation Single register "Flow-through" mode Single-cycle deselect Dual-cycle deselect also available AS7C33512PFD32A/ AS7C33512PFD36A) Pentium®* compatible architecture timing Asynchronous output enable control 100-pin TQFP package 119-Ball Ball Grid Array Package) Byte write enables Multiple chip enables easy expansion core power supply 2.5V 3.3V operation with separate VDDQ NTDTM* pipeline architecture available (AS7C33512NTD32A/ AS7C33512NTD36A)
Pentium® registered trademark Intel Corporation. NTDis trademark Alliance Semiconductor Corporation. trademarks mentioned this document property their respective owners.
Logic Block Diagram:
ADSC ADSP Address register Burst logic
Arrangement:
ADSC ADSP
512K 32/36 Memory array
Byte write registers Byte write registers Byte write registers Byte write registers Enable register Power down Enable delay register
36/32
36/32
Output registers
Input registers
Note: Pins 1,30,51,80
DATA [35:0] DATA [31:0]
Selection guide
Minimum cycle time Maximum clock frequency Maximum pipelined clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC)
-200
-166
DQPc/NC VDDQ VSSQ VSSQ VDDQ VDDQ VSSQ VSSQ VDDQ DQPd/NC
TQFP 512K 32A/36A
DQPb/NC VDDQ VSSQ VSSQ VDDQ VDDQ VSSQ VSSQ VDDQ DQPa/NC
-100
Units
10/4/01; v.0.9.4
Alliance Semiconductor
Copyright Alliance Semiconductor. rights reserved.
AS7C33512PFS32A AS7C33512PFS36A
Configuration
View
VDDQ
VDDQ VDDQ VDDQ VDDQ
DQPc DQpd
ADSP ADSC
DQpb DQPa
VDDQ VDDQ VDDQ VDDQ VDDQ
Note: AS7C33512PFS32A, Pins must left open (N.C.)
10/4/01; v.0.9.4
Alliance Semiconductor
Copyright Alliance Semiconductor Corporation. rights reserved. three-point logo, name Intelliwatt trademarks registered trademarks Alliance. other brand product names trademarks their respective companies. Alliance reserves right make changes this document products time without notice. Alliance assumes responsibility errors that appear this document. data contained herein represents Alliance's best data and/or estimates time issuance. Alliance reserves right change correct this data time, without notice. product described herein under development, significant changes these specifications possible. information this product data sheet intended general descriptive information potential customers users, intended operate provide, guarantee warrantee user customer. Alliance does assume responsibility liability arising application product described herein, disclaims express implied warranties related sale and/or Alliance products including liability warranties related fitness particular purpose, merchantability, infringement intellectual property rights, except express agreed Alliance's Terms Conditions Sale (which available from Alliance). sales Alliance products made exclusively according Alliance's Terms Conditions Sale. purchase products from Alliance does convey license under patent rights, copyrights, mask works rights, trademarks, other intellectual property rights Alliance third parties. Alliance does authorize products critical components life-supporting systems where malfunction failure reasonably expected result significant injury user, inclusion Alliance products such life-supporting systems implies that manufacturer assumes risk such agrees indemnify Alliance against claims arising from such use.

3.3V 512K 32/36 pipeline burst synchronous SRAM Features Organiza

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