AS6UA5128 2.3V 3.6V Intelliwatt low-power CMOS SRAM Features

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AS6UA5128 2.3V 3.6V Intelliwatt low-power CMOS SRAM Features

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AS6UA5128
2.3V 3.6V Intelliwatt low-power CMOS SRAM Features
AS6UA5128 Intelliwattactive power circuitry Industrial commercial temperature ranges available Organization: 524,288 words bits 2.7V 3.6V 2.3V 2.7V power consumption: ACTIVE
3.6V 2.7V 2.3V
1.5V data retention Equal access cycle times Easy memory expansion with inputs Smallest footprint packages protection 2000 volts Latch-up current
36(48)-ball FBGA
power consumption: STANDBY
3.6V 2.7V
Logic block diagram
Input buffer I/O8 Sense
arrangement 36(48)-CSP/BGA Package (shading indicates ball)
I/O1
I/O1 I/O2
I/O5 I/O6 I/O7 I/O8
decoder
Array (4,194,304)
I/O3 I/O4
Column decoder
Control circuit
Selection guide
Range Product AS6UA5128 AS6UA5128 Typ2 Speed (ns) Power Dissipation Operating (ICC) (mA) Standby (ISB1) (µA)
9/21/01; v.1.2
Alliance Semiconductor
Copyright ©Alliance Semiconductor. rights reserved.
AS6UA5128
Functional description
AS6UA5128 low-power CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized 524,288 words bits. designed memory applications where slow data access, power, simple interfacing desired. Equal address access cycle times (tAA, tRC, tWC) 55/70ns ideal low-power applications. Active high chip selects (CS) permit easy memory expansion with multiple-bank memory systems. When high, device enters standby mode: AS6UA5128 guaranteed exceed power consumption 3.6V 2.7V 2.3V device also returns data when reduced 1.5V even lower power consumption. write cycle accomplished asserting write enable (WE) chip select (CS) low. Data input pins I/O1-I/O8 written rising edge (write cycle (write cycle avoid contention, external devices should drive pins only after outputs have been disabled with output enable (OE) write enable (WE). read cycle accomplished asserting output enable (OE), chip select (CS), with write enable (WE) High. chip drives pins with data word referenced input address. When either chip select output enable inactive, write enable active, output drivers stay high-impedance mode. chip inputs outputs CMOS-compatible, operation from single 2.3V 3.6V supply. device available JEDEC standard 36(48)-ball FBGA package.
Absolute maximum ratings
Parameter Voltage relative Voltage relative Power dissipation Storage temperature (plastic) Temperature with applied output current (low) Device Symbol VtIN VtI/O Tstg Tbias IOUT -0.5 -0.5 +150 +125 Unit
Note: Stresses greater than those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only functional operation device these other conditions outside those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
Truth table
Supply Current I/O1-I/O8 High High DOUT Mode Standby (ISB) Output disable (ICC) Read (ICC) Write (ICC)
Key: Don't care, Low, High.
9/21/01; v.1.2
Alliance Semiconductor
AS6UA5128
Recommended operating condition (over operating range)
Parameter Description -1.5mA Output HIGH Voltage -0.5mA 2.1mA Output Voltage 0.5mA Input HIGH Voltage 2.3V 2.7V Input Voltage 2.3V Input Load Current Output Load Current Operating Supply Current Average Operating Supply Current VCC; Outputs High
VIL, IOUT 0mA, 0.2V, 0.2V, 0.2V,
Test Conditions 2.7V 2.3V 2.7V 2.3V 2.7V
Unit
-0.5 -0.3 40/30 30/25
3.6V 2.7V 3.6V 2.7V 3.6V (55/70 2.7V (55/70 3.6V 3.6V
ICC1
ICC2
Average Operating VIL, VIH, fMax Supply Current Power Down Current; VIH, other inputs Inputs Power Down Current; CMOS Inputs
0.2V 0.2V, other inputs VCC, fMax
ISB1
Capacitance MHz, Room temperature, NOMINAL)
Parameter Input capacitance capacitance Symbol CI/O Signals Test conditions VOUT Unit
9/21/01; v.1.2
Alliance Semiconductor
AS6UA5128
Read cycle (over operating range)
Parameter Read cycle time Address access time Chip select (CS) access time Output enable (OE) access time Output hold from address change output high output high output high output high Power time Power down time Symbol tACS tCLZ tCHZ tOLZ tOHZ Unit Notes
switching waveforms
Rising input Falling input Undefined/don't care
Read waveform (address controlled)
Address DOUT Previous data valid Data valid
Read waveform (CS, controlled)
tRC1 tOLZ tACE DOUT tCLZ Supply current Data valid tOHZ tCHZ
9/21/01; v.1.2
Alliance Semiconductor
AS6UA5128
Write cycle (over operating range)
Parameter Write cycle time Chip select write Address setup write Address setup time Write pulse width Write recovery time Address hold from write Data valid write Data hold time Write enable output high Output active from write Symbol Unit Notes
Write waveform controlled)
Address DOUT Data valid
Write waveform controlled)
Address DOUT Data valid
9/21/01; v.1.2
Alliance Semiconductor
AS6UA5128
Data retention characteristics (over operating range)
Parameter data retention Data retention current Chip deselect data retention time Operation recovery time Symbol ICCDR tCDR Test conditions 1.5V 0.1V 0.1V 0.1V 1.5V Unit
Data retention waveform
Data retention mode tCDR 1.5V
test loads waveforms
OUTPUT INCLUDING SCOPE INCLUDING SCOPE OUTPUT Thevenin equivalent: OUTPUT INPUT PULSES
Parameters Notes
2.7V 1095 1600 1.6V
2.3V 3800 4000 1600 1.2V
Unit Ohms Ohms Ohms Volts
During power-up, pull-up resistor required meet specification. This parameter sampled, 100% tested. test conditions, Test Conditions. tCLZ tCHZ specified with Figure Transition measured ±500 from steady-state voltage. This parameter guaranteed, tested. HIGH read cycle. read cycle. Address valid prior coincident with transition LOW. read cycle timings referenced from last valid address first transitioning address. must HIGH during address transitions. Either asserting high terminates write cycle. write cycle timings referenced from last valid address first transitioning address. N/A. 1.5V data retention applies commercial industrial temperature range operations. 30pF, except high parameters, where 5pF.
9/21/01; v.1.2
Alliance Semiconductor
AS6UA5128
Typical characteristics
Normalized supply current supply voltage Normalized Normalized ISB2 Normalized 0.75 Normalized access time supply voltage -0.5 Ambient temperature (°C) Normalized Cycle Time 3.6V Normalized standby current ambient temperature
0.25
Supply voltage Normalized standby current supply voltage Normalized Supply voltage ISB2
Supply Voltage
Normalized
0.50
0.10 Supply voltage
9/21/01; v.1.2
Alliance Semiconductor
AS6UA5128
Package diagrams dimensions
36(48)-ball FBGA Bottom View Ball View Ball index
Elastomer SRAM
Side View
Detail View 0.3/Typ
Minimum 6.90 10.90 0.30 0.22
Typical 0.75 7.00 3.75 11.00 5.25 0.35 0.68 0.25
Maximum 7.10 11.10 0.40 1.20 0.27 0.08
Notes Bump counts: 36(48) column). Pitch: (x,y) 0.75 0.75 (typ). Units: millimeters. tolerance ±0.050 unless otherwise specified. Typ: typical. coplanarity: 0.08 (max).
9/21/01; v.1.2
Alliance Semiconductor
AS6UA5128
Ordering codes
Speed (ns) 55/70 55/70
Ordering Code
AS6UA5128-BC AS6UA5128-BI
Package Type
48-ball fine pitch 48-ball fine pitch
Operating Range Commercial
Industrial
Part numbering system
AS6UA SRAM Intelliwattprefix 5128 Device number Package: CSP/BGA Temperature range: Commercial: Industrial: -40°C
9/21/01; v.1.2
Alliance Semiconductor
Copyright Alliance Semiconductor Corporation. rights reserved. three-point logo, name Intelliwatt trademarks registered trademarks Alliance. other brand product names trademarks their respective companies. Alliance reserves right make changes this document products time without notice. Alliance assumes responsibility errors that appear this document. data contained herein represents Alliance's best data and/or estimates time issuance. Alliance reserves right change correct this data time, without notice. product described herein under development, significant changes these specifications possible. information this product data sheet intended general descriptive information potential customers users, intended operate provide, guarantee warrantee user customer. Alliance does assume responsibility liability arising application product described herein, disclaims express implied warranties related sale and/or Alliance products including liability warranties related fitness particular purpose, merchantability, infringement intellectual property rights, except express agreed Alliance's Terms Conditions Sale (which available from Alliance). sales Alliance products made exclusively according Alliance's Terms Conditions Sale. purchase products from Alliance does convey license under patent rights, copyrights, mask works rights, trademarks, other intellectual property rights Alliance third parties. Alliance does authorize products critical components lifesupporting systems where malfunction failure reasonably expected result significant injury user, inclusion Alliance products such life-supporting systems implies that manufacturer assumes risk such agrees indemnify Alliance against claims arising from such use.

AS6UA5128 2.3V 3.6V Intelliwatt low-power CMOS SRAM Features

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