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2.7V 3.3V 512K Intelliwattlow-power CMOS SRAM Features AS6VA5128
Top Searches for this datasheetAS6VA5128 2.7V 3.3V 512K Intelliwattlow-power CMOS SRAM Features AS6VA5128 Intelliwattactive power circuitry Industrial commercial temperature ranges available Organization: 524,288 words bits 2.7V 3.3V power consumption: ACTIVE 3.3V 1.5V data retention Equal access cycle times Easy memory expansion with inputs Smallest footprint packages protection 2000 volts Latch-up current 36(48)-ball FBGA power consumption: STANDBY 3.3V Logic block diagram Input buffer 48-CSP/BGA Package (shading indicates ball) I/O5 I/O6 I/O7 I/O8 I/O8 Sense I/O1 I/O2 decoder 512K Array (4,194,304) I/O1 Column decoder Control circuit I/O3 I/O4 Selection guide Range Product AS6VA5128 Typ2 Speed (ns) Power Dissipation Standby (ISB1) Operating (ICC) (mA) (µA) 9/24/01; v.1.2 Alliance Semiconductor Copyright Alliance Semiconductor. rights reserved. AS6VA5128 Functional description AS6VA5128 low-power CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized 524,288 words bits. designed memory applications where slow data access, power, simple interfacing desired. Equal address access cycle times (tAA, tRC, tWC) ideal low-power applications. Active high chip selects (CS) permit easy memory expansion with multiple-bank memory systems. When high, device enters standby mode: AS6VA5128 guaranteed exceed power consumption 3.3V 55ns. device also returns data when reduced 1.5V even lower power consumption. write cycle accomplished asserting write enable (WE) chip select (CS) low. Data input pins I/O1-I/O8 written rising edge (write cycle (write cycle avoid contention, external devices should drive pins only after outputs have been disabled with output enable (OE) write enable (WE). read cycle accomplished asserting output enable (OE), chip select (CS), with write enable (WE) High. chip drives pins with data word referenced input address. When either chip select output enable inactive, write enable active, output drivers stay high-impedance mode. chip inputs outputs CMOS-compatible, operation from single 2.7V 3.3V supply. device available JEDEC standard 36(48)-ball FBGA package. Absolute maximum ratings Parameter Voltage relative Voltage relative Power dissipation Storage temperature (plastic) Temperature with applied output current (low) Device Symbol VtIN VtI/O Tstg Tbias IOUT -0.5 -0.5 +150 +125 Unit Note: Stresses greater than those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only functional operation device these other conditions outside those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. Truth table Supply Current I/O1-I/O8 High High High DOUT Mode Standby (ISB) Standby (ISB) Output disable (ICC) Read (ICC) Write (ICC) Key: Don't care, Low, High. 9/24/01; v.1.2 Alliance Semiconductor AS6VA5128 Recommended operating condition (over operating range) Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input Load Current Output Load Current Operating Supply Current -1.5mA 2.1mA Test Conditions 2.7V 2.7V 2.7V 2.7V VCC; Outputs High VIL, IOUT 0mA, 3.3V -0.5 Unit ICC1 0.2V, 0.2V, Average Operating 0.2V, Supply Current Average Operating VIL, Supply Current VIH, fMax 3.3V ICC2 3.3V Power Down Current; VIH, other inputs Inputs 0.2V, Power Down Current; other inputs CMOS Inputs VCC, fMax 3.3V ISB1 3.3V Capacitance MHz, Room temperature, NOMINAL) Parameter Input capacitance capacitance Symbol CI/O Signals Test conditions VOUT Unit 9/24/01; v.1.2 Alliance Semiconductor AS6VA5128 Read cycle (over operating range) Parameter Read cycle time Address access time Chip select (CS) access time Output enable (OE) access time Output hold from address change output high output high output high output high Power time Power down time Symbol tACS tCLZ tCHZ tOLZ tOHZ Unit Notes switching waveforms Rising input Falling input Undefined/don't care Read waveform (address controlled) Address DOUT Previous data valid Data valid Read waveform (CS, controlled) tRC1 tOLZ tACE DOUT tCLZ Supply current Data valid tOHZ tCHZ 9/24/01; v.1.2 Alliance Semiconductor AS6VA5128 Write cycle (over operating range) Parameter Write cycle time Chip select write Address setup write Address setup time Write pulse width Write recovery time Address hold from write Data valid write Data hold time Write enable output high Output active from write Symbol Unit Notes Write waveform controlled) Address DOUT Data valid Write waveform controlled) Address DOUT Data valid 9/24/01; v.1.2 Alliance Semiconductor AS6VA5128 Data retention characteristics (over operating range) Parameter data retention Data retention current Chip deselect data retention time Operation recovery time Symbol ICCDR tCDR Test conditions 1.5V 0.1V 0.1V 0.1V 1.5V Unit Data retention waveform Data retention mode tCDR 1.5V test loads waveforms OUTPUT INCLUDING SCOPE INCLUDING SCOPE OUTPUT Thevenin equivalent: OUTPUT INPUT PULSES Parameters Notes 2.7V 1095 1600 1.6V Unit Ohms Ohms Ohms Volts During power-up, pull-up resistor required meet specification. This parameter sampled, 100% tested. test conditions, Test Conditions. tCLZ tCHZ specified with Figure Transition measured ±500 from steady-state voltage. This parameter guaranteed, tested. HIGH read cycle. read cycle. Address valid prior coincident with transition LOW. read cycle timings referenced from last valid address first transitioning address. must HIGH during address transitions. Either asserting high terminates write cycle. write cycle timings referenced from last valid address first transitioning address. N/A. 1.5V data retention applies commercial industrial temperature range operations. 30pF, except high parameters, where 5pF. 9/24/01; v.1.2 Alliance Semiconductor AS6VA5128 Typical characteristics Normalized supply current supply voltage Normalized Normalized ISB2 Normalized 0.75 Normalized access time supply voltage -0.5 Ambient temperature (°C) Normalized Cycle Time 3.6V Normalized standby current ambient temperature 0.25 Supply voltage Normalized standby current supply voltage Normalized Supply voltage ISB2 Supply Voltage Normalized 0.50 0.10 Supply voltage 9/24/01; v.1.2 Alliance Semiconductor AS6VA5128 Package diagrams dimensions 36(48)-ball FBGA Bottom View Ball View Ball index Elastomer SRAM Side View Detail View 0.3/Typ Minimum 6.90 10.90 0.30 0.22 Typical 0.75 7.00 3.75 11.00 5.25 0.35 0.68 0.25 Maximum 7.10 11.10 0.40 1.20 0.27 0.08 Notes Bump counts: 36(48) column). Pitch: (x,y) 0.75 0.75 (typ). Units: millimeters. tolerances ±0.050, unless otherwise specified. Typ: typical. coplanarity: 0.08 (max). 9/24/01; v.1.2 Alliance Semiconductor AS6VA5128 Ordering codes Speed (ns) Ordering Code AS6VA5128-BC AS6VA5128-BI Package Type 48-ball fine pitch 48-ball fine pitch Operating Range Commercial Industrial Part numbering system AS6VA SRAM Intelliwattprefix 5128 Device number Package: CSP/BGA Temperature range: Commercial: Industrial: -40°C 9/24/01; v.1.2 Alliance Semiconductor Copyright Alliance Semiconductor Corporation. rights reserved. three-point logo, name Intelliwatt trademarks registered trademarks Alliance. other brand product names trademarks their respective companies. Alliance reserves right make changes this document products time without notice. Alliance assumes responsibility errors that appear this document. data contained herein represents Alliance's best data and/or estimates time issuance. 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