GTLP6C816 GTLP-to-TTL Clock Driver Features Bidirection

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GTLP6C816 GTLP-to-TTL Clock Driver Features Bidirection

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TTLIN
GTLP6C816
GTLP-to-TTL Clock Driver
Features
Bidirectional interface between GTLP logic levels Designed with Edge Rate Control Circuit reduce output noise GTLP port Power up/down high impedance live insertion fanout clock driver port Lower Drive (12mA) Port reduce noise fanout clock driver GTLP port compatible driver control inputs Flow -through architecture optimizes layout Open drain GTLP support wired-or connection Operating Temperature: 40°C +85°C Package: 24-Pin wide plastic TSSOP (L24)
Product Description
Pericom Semiconductors GTLP series logic circuits produced using Companys advanced micron CMOS technology, achieving industry leading performance. GTLP6C816 clock driver that provides GTLP signal level translation (and vice versa). device provides high-speed interface between cards operating logic levels backplane operating GTLP logic levels. High-speed backplane operation direct result GTLPs reduced output swing (<1V), reduced input threshold levels, output edge-rate control which minimizes settling times. Pericoms GTLP internal edge-rate control. function similar with different output levels receiver threshold. GTLP output voltage typically less than 0.5V, output level HIGH 1.5V receiver threshold 1.0V.
PinConfiguration
GTLP Ports
Ports
GTLPIN
TTLIN GNDT VCCT GNDT VCCT GNDT
24-Pin
GNDT GNDG VREF GNDG GNDG GTLPIN GNDT
PS8426A
03/15/00
GTLP6C816 GTLP-to-TTL Clock Driver
Functional Description
GTLP6C816 clock driver that provides GTLP clock translation, GTLP-to-TTL clock translation. TTL-to-GTLP direction clock driver path with single Enable (OEB).
GTLP -to-TTL direction, clock receiver path buffer with single Enable control (OEA). Data polarity inverting both directions.
Descriptions
Name TTLIN, GTLPIN VCCT, GNDT GNDG VREF cription Clock Inputs (TTL GTLP respectively) Output Enable (Active LOW) GTLP Port (TTL Levels) Output Enable (Active LOW) Port (TTL Levels) Output Supplies (5V) Internal Circuitry (5V) GTLP Output Grounds Voltage Reference Input Buffered Clock Outputs GTLP Buffered Clock Outputs
Truth Table
Inputs TTLIN GTLPIN Outputs High High
PS8426A
03/15/00
GTLP6C816 GTLP-to-TTL Clock Driver
Absolute Maximum Ratings(1)
(Above which useful life impaired. user guidelines, tested.) Supply Voltage (VCC) 0.5V +7.0V Input Voltage 0.5V +7.0V Output Voltage (VO) Outputs 3-State 0.5V +7.0V Outputs Active(2) 0.5V +7.0V Output Sink Current into OA-Port 32mA Output Source Current into OA-Port 32mA Output Sink Current into OB-Port State 80mA Input Diode Current (IIK) 50mA Output Diode Current (IOK) 50mA +50mA Rating >2000V Storage Temperature (TSTG) 65°C +150°C
Recommended Operating Condition(3)
Supply Voltage 4.75V 5.25V Termination Voltage (VTT) GTLP 1.47V 1.53V VREF 0.98V 1.02V Input Voltage (VI) INA-Port Control Pins .0.0V 5.5V HIGH Level Output Current (IOH) OA-Port 12mA Level Output Current (IOL) OA-Port +12mA OB-Port +34mA Operating Temperature (TA) 40°C +85°C Notes: Absolute Maximum continuous ratings those values beyond which damage device occur. Exposure these conditions conditions beyond those indicated adversely affect device reliability. Functional opertion under absolute maximum rated conditions implied. Absolute Maximum Rating must observed Unused inputs must held HIGH LOW.
PS8426A
03/15/00
GTLP6C816 GTLP-to-TTL Clock Driver
Electrical Characteristics
Symbol GTLPIN Others GTLPIN Others GTLP GTLP
(Over recommended Operating Free-Air Temperature Range, VREF (Unless otherwise noted)
Conditions VREF +0.05 VREF 0.05 4.75V 4.75V 18mA 100mA 12mA 100mA OAn- Port 4.75V 12mA OBn- Port TTLIN/ Control Pins GTLPIN IOFF IOZH IOZL TTLIN OAn- Port OBn- Port OAn- Port Ports TTLIN Control Pins/ GTLPPIN/TTLIN OAn- Port OBn- Port 4.75V 5.25V 5.25V 5.25V 5.25V 5.25V 100µA 34mA 5.25V 5.25V 5.25V 1.5V Outputs HIGH Outputs Outputs Disabled 0.65 Typ.(4) Units
VREF(5) VTT(5)
OAn- Port
DICC
COUT
5.25V
Notes: typical values 5.0V 25°C GTLP, VREF specified tolerance since signal integrity noise margin significantly degraded these supplies noisy. addition, RTERM adjusted accommodate backplane impedances other than within boundaries exceeding Absolute ratings. Similarly, VREF adjusted compensate changes VTT.
PS8426A 03/15/00
GTLP6C816 GTLP-to-TTL Clock Driver
Operating Requirements
(Over recommended ranges supply voltage operating free-air temperature, VREF (Unless otherwise noted) 30pF OBn-Port 50pF OAn-Port.
Symbol tPLH tPHL tPLH tPHL tRISE tFALL tRISE tFALL tPZH, tPZL tPLZ, tPHZ tPLH tPHL tOSHL, tOSLH(7) From (Input) TTLIN (Output) Typ.(6) 0.15 0.25 Units
Transition Time. Outputs (20% 80%) Transition Time. Outputs (20% 80%) Transition Time. Outputs (10% 90%) Transition Time. Outputs (10% 90%) GTLPIN
Common Edge Skew
Notes: typical values 5.0V 25°C Skew specs given specific worst case Temp. Skew values between outputs could vary backplance owing loading impedance seen device.
PS8426A
03/15/00
GTLP6C816 GTLP-to-TTL Clock Driver
Test Circuits Timing Waveforms
Test Circuit Outputs
Test Circuit Outputs
From Output Under Test 50pF
(Note
Open
From Output Under Test
1.5V (GTLP) 1.2V (GTL) 30pF
(Notes
Test tPLH/tPHL tPLZ/tPZH tPHZ/tPZH
Open
Note includes probes capacitance
Notes: includes probes capacitance. B-Port outputs, 30pF used worst case.
Voltage Waveforms Propagation Delay 1.5V A-Port B-Port)
3.0V Input (1.5V B-Port GTLP)
Voltage Waveforms Enable Disable Times A-Port
3.0V 1.5V tPZL 1.5V tPZH 1.5V VOH-0.3V VOL+0.3V 1.5V
tPHL tPHL
Output
(1.5V B-Port GTLP)
24-Pin Wide Plastic TSSOP Package
.169 .177
.303 .311 .047 1.20
.004 .008 0.45 0.75 SEATING PLANE .018 .030
0.09 0.20
.252
.0256 0.65
.007 .012 0.19 0.30
.002 .006
0.05 0.15
X.XX DENOTES CONTROLLING X.XX DIMENSIONS MILLIMETERS
Pericom Semiconductor Corporation 2380 Bering Drive Jose, 95131 1-800-435-2336 (408) 435-1100 http://www.pericom.com
PS8426A 03/15/00

GTLP6C816 GTLP-to-TTL Clock Driver Features Bidirection

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