DMUX 8/10-bit 2GHz 1:4/8 TS81102G0 Package TBGA Tape Ball Gr
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Programmable DMUX ratio Data rate Gsps, (8b/10b)< (ECL output) Data Rate 2GSPS, (8b/10b)< (ECL output) 1:16 with TS8388B TS83102G0 DMUX. Parallel output mode. 8/10 bit. Differential input data. DataReady DataReady/2 input clock. Input clock sampling delay adjust. Single ended output data Adjustable common mode swing Logic threshold reference output (ECL, PECL, TTL). Asynchronous reset. Synchronous reset. DMUX multi-channel applications Stand-alone delay adjust cell ADCs sampling instant alignment. Differential data ready output. Built-in self test (BIST). Dual power supply Radiation tolerance oriented design (more than Krad (Si) expected).
DMUX 8/10-bit 2GHz 1:4/8
TS81102G0
Package TBGA Tape Ball Grid Array (cavity down)
SCREENING
Atmel-Grenoble standard screening level Temperature range 90°C -40°C 110°C
DESCRIPTION
TS81102G0 monolithic 10-bits high speed 2GHz) demultiplexor. DMUX designed with kinds ADCs more specifically, fits perfectly with Atmel Grenoble high speed 8-bit Gsps TS8388B, 10bit TS83102G0 8-bit Gsps TS83084G0. TS81102G0 using innovative architecture, including sampling delay adjust tunable output levels. This DMUX allows users process high speed out-put data stream down processor speed. uses very high speed bipolar technology cutt-off frequency).
January 2002
Product Specification
Product specification
TABLE CONTENTS
BLOCK DIAGRAM INTERNAL TIMING DIAGRAM FUNCTIONAL DESCRIPTION MAIN FUNCTIONS DESCRIPTION. 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 4.7. 4.8. 4.9. 4.10. 4.11. 4.12. 4.13. PROGRAMMABLE DMUX RATIO PARALLEL OUTPUT MODE INPUT CLOCK SAMPLING DELAY ADJUST (DEMUXDELADJCTRL) ASYNCHRONOUS RESET (ASYNCRESET): SYNCHRONOUS RESET (SYNCRESET) COUNTER PROGRAMMABLE STATE PIPELINE DELAY 8/10 BIT, WITH MODE UNUSED DIFFERENTIAL INPUT DATA OHMS DIFFERENTIAL OUTPUT DATA SINGLE ENDED OUTPUT DATA DIFFERENTIAL DATA READY OUTPUT BUILT-IN SELF TEST (BIST)
SPECIFICATIONS. 5.1. 5.2. 5.3. 5.4. 5.5. ABSOLUTE MAXIMUM RATINGS (SEE NOTE BELOW). RECOMMENDED CONDITIONS USE. ELECTRICAL OPERATING CHARACTERISTICS. SWITCHING PERFORMANCE CHARACTERISTICS EXPLANATION TEST LEVELS
PACKAGE DESCRIPTION 6.1. 6.2. 6.3. 6.4. 6.5. DESCRIPTION TBGA PACKAGE PINOUT OUTLINE DIMENSIONS TAPE BALL GRID ARRAY THERMAL MOISTURE CHARACTERISTICS DETAILLED CROSS SECTION
APPLYING TS81102G0 DEMUX TSEV81102G0TP DEVICE EVALUATION BOARD ORDERING INFORMATION 9.1. 9.2. 9.3.
PACKAGE DEVICE FORM. EVALUATION BOARD.
TS81102G0
TS81102G0
BLOCK DIAGRAM
Data Path
DEMUXDelAdjCt SwiAdj VplusDOut DIODE ClkInType
Clock Path
SyncReset AsyncReset RatioSel ADCDelAdjIn ADCDelAdjCtrl
delay
I[0.7/9]
BIST
NbBit
RatioSel
FS/8
delay
BIST 8/10 8/10 ClkPar even master latch even slave latch master latch slave latch Phase control RstGen Reset
Counter Counter stage Status shift register)
ClkIn FS/8 DataReady generation
Latch Even/Odd
Port Selection Clock
Data Output Clock
8/10 A[0.7/9] RefA C[0.7/9] RefC E[0.7/9] RefE G[0.7/9] RefG B[0.7/9] RefB D[0.7/9] RefD F[0.7/9] RefF H[0.7/9] RefH
Even Ports
Ports
DR/DR
Product Specification
ADCDelAdjOut
Product specification
INTERNAL TIMING DIAGRAM
This diagram corresponding established operation DMUX with Synchronous Reset.
Data DR/2 Fs/2 ClkPar Master Even Latch Master Latch Slave Even Latch Slave Latch Synchronous reset Fs/8 Internal reset pulse Port Select Port Select Port Select Port Select Port Select Port Select Port Select Port Select Latch Select Latch Select Latch Select Latch Select Latch Select Latch Select Latch Select Latch Select Port Latch
TS81102G0
TS81102G0
FUNCTIONAL DESCRIPTION
TS81102G0 demultiplexer based advanced high speed bipolar technology featuring cutoff frequency GHz. role reduce data rate that data could processed DEMUX output. TS81102G0 provides programmable ratios 1:8. maximum data rate GSPS ratio GSPS ratio. TS81102G0 able process bits data flow. input clock differential signal single-ended coupled signal. Moreover could DataReady DataReady/2 clock. input digital data must differential signals. output signals (Data Ready, digital data Reference voltage) adjustable with VplusD independent power supply. Typical output modes ECL, PECL TTL. Data Ready output differential signal. digital output data Reference voltages single-ended signals. TS81102G0 started Asynchronous Reset. Synchronous Reset enables re-synchronize output port selection minimize possible loss data that could occur within DMUX. delay adjust cell available ensure good phase between input clock input data DEMUX. Another delay adjust cell available control ADCs sampling instant alignment, case ADCs interleaving. bits generator implemented TS81102G0, Built-In Self Test (BIST). This test sequence very useful testing DMUX first use. fine tuning output swing also available. TS81102G0 used with following ATMEL-Grenoble ADCs: TS8388B(F/G), 8-bit Gsps TS83102G0, 10-bit 2Gsps TS83084G0, 8-bit 4Gsps Dual Port DMUX port).
Product Specification
Product specification
4.1.
MAIN FUNCTIONS DESCRIPTION
PROGRAMMABLE DMUX RATIO 4.4. ASYNCHRONOUS RESET (ASYNCRESET):
CLKIN AsyncReset Port Selected Port selected Port selected Port selected Port selected Port selected Port selected Port selected
Asynchronous Reset master reset port selection, which works levels. active high level. During asynchronous reset, clock must run. used start DMUX. When active, paralyzing outputs (output clock output data remain level they had, just before asynchronous reset). When comes back level, DMUX starts outputs active first processed data port
conversion ratio programmable
IInput Words 1,2,3,4,5,6,7,8.
IInput Words 1,2,3,4,5,6,7,8.
Output Words PortA PortB PortC PortD PortE used PortF used PortG used PortH used Output Words PortA PortB PortC PortD PortE PortF PortG PortH
4.5. 4.2. PARALLEL OUTPUT MODE
SYNCHRONOUS RESET (SYNCRESET)
Parallel Mode ClkIn Data PortA PortB PortC PortD PortE PortF PortG PortH
DR/2 SyncReset FS/8 Internal reset pulse Port Selected Port selected Port selected Port selected Port selected Port selected Port selected Port selected
4.3.
INPUT CLOCK SAMPLING DELAY ADJUST (DEMUXDELADJCTRL)
input clock phase adjusted with adjustable delay (from ps). This ensure good phase between clock input data DMUX.
DMUX synchronously reset programmable state depending conversion ratio. clock must stopped during reset. synchronization signal clock (SyncRest) which frequency like FS/8*n where integer (n=1,2,3,.) mode FS/4*n mode. division factor called next schematic. front edge this clock synchronized with Clkln inside DMUX, generates 200ps reset pulse. This reset pulse occurs during fixed level Clkln.
TS81102G0
TS81102G0
DMUX synchronized with Syncreset previous reset, then output data immediately correct, modification seen output DMUX, data lost (see Internal Timing Diagram).
ohms
DMUX synchronized with SyncReset, then output data data ready DMUX changed. output data correct after number input clock corresponding pipeline delay (see examples page 17).
ADCDelAdjOut
ohms
ADCDelAdjOutb
4.6.
COUNTER PROGRAMMABLE STATE
When counter reset, initial states depends conversion ratio counting bits, counting bits,
4.11.
SINGLE ENDED OUTPUT DATA
4.7.
PIPELINE DELAY
reduce number DMUX, power consumption, eight output ports single ended. reach high frequency output MHz), with reasonable power consumption, swing must limited maximum common mode adjustable from -1.3V with Vplus DOut pins. ensure better noise immunity, reference level (common mode) available (one output port). output buffers type (open emitter resistive adapted impedance). They designed average output current, used with ohms termination impedance.
maximum pipeline delay depends conversion ratio pipeline delay pipeline delay
4.8.
8/10 BIT, WITH MODE UNUSED
DMUX parallel device. last (bit used, corresponding functions mode reduce power consumption.
4.9.
DIFFERENTIAL INPUT DATA
Input data compatible (Voh 0.8V, 1.8V). minimum swing required differential. inputs have differential termination resistor. middle point these resistor connected ground through 10pF capacitor
VPlusDOut
ClkIn
ClkInb
PadOut
ohms
ohms
10pF
4.10.
OHMS DIFFERENTIAL OUTPUT DATA
Output clock generated through ohms loaded long tailed. ohms resistor connected ground through diode. levels ohms differential termination resistor) 1.4V, 1.0V.
give thereafter three examples application these buffers ECL/PECL/TTL. Please note that possible have other output format current max) voltage (Vplus Dout 8.3V) limits overridden. maximum frequency output mode depends load drive.
Product Specification
Product specification
Ohms PECL Ohms Ohms MSPS
VplusDout Swing Reference Load Average Output Current Output Data rate max.
MSPS
MSPS
This corresponds "Adjustable Logic Single" pin-out description. "Adjustable Single" buffers reference voltage same buffers. information available out-put these buffers more like analog than logic.
4.12.
DIFFERENTIAL DATA READY OUTPUT
front Edge DataReady Output occurs when data available corresponding port. frequency this clock depends conversion ratio (1:8 1:4), with duty cycle definition same single ended output data, buffers differential. This corresponds "Adjustable Logic Differential" pin-out description.
4.13.
BUILT-IN SELF TEST (BIST)
pseudo-random generator implemented DMUX. generates signals output DMUX, with period input clock. probability occurrence codes uniformly spread over 1024 possible codes 1/1024. Note that codes occur least once. starts with Bist command, phase with FS/8 clock, Port logic output obtained ports depends conversion ratio. driving clock BIST Clkln. ClklnType must (DataReady clock) have different code each output. complete BIST sequence available request.
TS81102G0
TS81102G0
5.1.
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (SEE NOTE BELOW)
Parameter Positive supply voltage Positive output buffer supply voltage Negative supply voltage Analog input voltages
Symbol VPLUSD ADCDelAdjCtrl, ADCDelAdjCtrlb DMUXDelAdjCtrl, DMUXDelAdjCtrlb SwiAdj Clkln Clklnb I[0.9] orI[0.9]b SyncReset SyncResetb ADCDelAdjln ADCDelAdjlnb Clkln Clklnb I[0.9] I[0.9]b SyncReset Syncresetb ADCDelAdjln ADCDelAdjlnb A[0.9] H[0.9] RefA RefH Clkln Type RatioSel NbBit AsyncReset BIST DIODE
Comments
Value
Unit
Voltage range each Differential voltage range
input voltage
Voltage range each
-2.2V +0.6V
Maximum difference between input voltages
Minimum differential swing Maximum differential swing Maximum current
+0.1V
Data output current
input voltages
Maximum input voltage diode temperature measurement Maximum input current diode Maximum junction temperature Storage temperature
DIODE Tstg
Notes :Absolute maximum ratings limiting values, applied individually, while other parameters within specified operating conditions. Long exposure maximum rating effect device reliability. thermal heat sink mandatory.
Product Specification
Product specification
5.2. RECOMMENDED CONDITIONS
Symbol VPLUSD VPLUSD VPLUSD Comments output compatibility PECL output compatibility output compatibility Civil grade Industrial grade Typ. Max. 5.25 5.25 4.75 Min. 4.45 Unit
Parameter Positive supply voltage Positive output buffer supply voltage Negative supply voltage Operating temperature range
5.3.
ELECTRICAL OPERATING CHARACTERISTICS
(Typical) Full temperature range 110° (Guaranteed temperature range depending part number) POWER REQUIREMENT Parameter Symb Test Level Positive supply voltage 4.75 VPLUSDOUT VPLUSD 0.25 PECL VPLUSD 3.135 VPLUSD 3.135 Negative supply voltage 5.25 Supply currents PECL (for every configuration) IPLUSD 1:8, bits IPLUSD 1:8, bits IPLUSD 1:4, bits IPLUSD 1:4, bits (for every configuration) IPLUSD 1:8, bits IPLUSD 1:8, bits IPLUSD 1:4, bits IPLUSD 1:4, bits Nominal power dissipation 1:8, bits 1:8, bits 1:4, bits 1:4, bits PECL 1:8, bits 1:8, bits 1:4, bits 1:4, bits 1:8, bits 1:8, bits 1:4, bits 1:4, bits
5.25 0.25 3.465 3.465 4.75
Unit
1180 1440 1610 1770
1820 2240 1120
2440 3010 1220 1510
Note supply current IPLUSD power dissipation depend state output buffers: minimum values corresponding output buffers level maximum values corresponding output buffers high level typical values corresponding equal sharing output buffers between high level.
TS81102G0
TS81102G0
Delay Adjust Control DMUXDelAdjCtrl differential voltage Input current ADCDelAdjCtrl differential voltage Input current Output (assuming VPLUSD SWIADJ termination resistor board) logique voltage logique voltage reference voltage PECL Output (assuming VPLUSD SWIADJ termination resistor board) logique voltage logique voltage reference voltage Output assuming VPLUSD SWIADJ termination resistor board) logique voltage logique voltage reference voltage Output level drift with temperature (data outputs) Output level drift with temperature (reference outputs) DIGITAL INPUTS Parameters Input Voltages logique voltage logique voltage Input Voltages logique voltage logique voltage symb Test level Unit DDAC IDDAC ADAC IADAC
VREF
2.12 1.16 1.40
VREF
1.27 2.44 1.83
VREF
0.19 2.31
mV/°
Mv/°
Product Specification
Product specification
5.4. SWITCHING PERFORMANCE CHARACTERISTICS
clock duty cycle (CLKIN, CLKINB), (Typical) Full temperature range 110° (Guaranteed temperature range depending part number) Timing Diagrams Figure Parameters Symb Test level Input Clock Maximum clock frequency ratio FMAX ratio Clock pulse width (high) Clock pulse width (low) Clock Path pipeline delay TCPD input clock TCPD DR/2 input clock Clock rise/fall time TRCKIN TFCKIN Asynchronous Reset Asynchronous Reset pulse width PWAR 1000 Setup time from Asynchronous TSAR Clkln Rise/fall time (10% 90%) TRAR 1000 TFAR Synchronous Reset Setup time from SyncReset Clkln TSSR input clock DR/2 input clock Hold time from Clkln SyncReset THSR input clock DR/2 input clock Rise/fall (10% 90%) TSRR/ TFSR Input Data Setup time from I[0.9] Clkln TSCKIN input clock DR/2 input clock Hold time from Clkln I[0.9] THCKIN input clock DR/2 input clock Rise/fall (10% 90%) TRDI/ TFDI Output Data Data output delay input clock DR/2 input clock (13) Data pipeline delay input clock, ratio input clock, ratio DR/2 input clock, ratio DR:2 input clock, ratio Rise/fall (10% 90%) TROD/ tfod
Unit
1084
1500
-580 -477
(10)
1820 (11) 1717 (12) 497/ (14) Number input clock
TS81102G0
TS81102G0
Data Ready Data ready Falling edge input clock DR/2 input clock Data ready Rising edge input clock DR/2 input clock Asynchr; Reset DataReady delay Synchr. Reset DataReady delay Rise/fall (10% 90%) Rising edge uncertainly Built-In Self Test Hold time from Clkln Bist Setup time from Bist Clkln Rise/fall time (10% 90%) Delay Adjust Input frequency Input pulse width (high) Input pulse width (low) Input rise/fall time Output rise/fall time Data output delay (typical delay adjust setting) Output delay drift with temperature Output delay uncertainly TDRF 1856 (15) 1753 (16) TDRR 1828 (17) 1725 (18) 1918 (19) 1037 (20) (21)
(22)
TARDR TSRDR TRDR/ TFDR JITTER THBIST TSBIST TRBIST/ TFBIST FMADA TC1ADA TC2ADA TRIADA/ TFIADA TROADA/ TFOADA TADA TADAT JITADA
1000
1000
(23) (24) (25)
(TBD)
ps/°
NOTE TCPD tuned with DMUXDelAdjCtrl TCPD NOTE TCPD tuned with DMUXDelAdjCtrl TCPD 1084 NOTE TSSR depends DMUXDelAdjCtrl TSSR TSSR because Clock Path internal delay. NOTE TSSR depends DMUXDelAdjCtrl TSSR TSSR because Clock Path internal delay NOTE THSR depends DMUXDelAdjCtrl THSR NOTE THSR depends DMUXDelAdjCtrl THSR NOTE TSCKIN depends DMUXDelAdjCtrl TSCKIN TSCKIN because Clock Path internal delay. NOTE TSCKIN depends DMUXDelAdjCtrl TSCKIN TSCKIN because Clock Path internal delay. NOTE THCKIN depends DMUXDelAdjCtrl THCKIN NOTE THCKIN depends DMUXDelAdjCtrl THCKIN NOTE depends DMUXDelAdjCtrl 1820 given output load. NOTE depends DMUXDelAdjCtrl 1717 given output load. NOTE number Clkln clock cycle from selection Port selection Port conversion mode, from selection Port selection Port conversion mode. maximum number Clkln clock cycle, pipeline delay, that data stay DMUX before being sorted out. This maximum delay occurs data sent Port instance, data sent Port goes directly from input Port pipeline even this data, there additional delay physical propagation time DMUX. NOTE TROD TFOD given output load. NOTE TDRF depends DMUXDelAdjCtrl TDRF 1856 given output load. NOTE TDRF depends DMUXDelAdjCtrl TDRF 1753 given output load. NOTE TDRR depends DMUXDelAdjCtrl TDRR 1858 given output load. NOTE TDRR depends DMUXDelAdjCtrl TDRR 1725 given output load. NOTE TARDR given output load. NOTE TSRDR given output load. minimum value since RstSync clock synchronized with Clkln clock. NOTE TRDR TFDR given output load. NOTE THBIST depends configuration DMUX. There must enough Clkln clock cycles have codes, (see different timing diagrams). NOTE with transmission line output load NOTE without output load. NOTE with transmission line output load
Product Specification
Product specification
5.4.1. INPUT CLOCK TIMINGS
ClkInType DataReady Mode (DR)
ClkInType DataReady/2 Mode (DR/2)
Figure Input Clock
5.4.2.
DELAY ADJUST TIMING DIAGRAM
Figure ADCDelay Adjust timing diagram
TS81102G0
TS81102G0
5.4.3. TIMING DIAGRAMS WITH ASYNCHRONOUS RESET With nominal tuning DMUXDelAdj frequency Ghz, data lost because internal clock path propagation delay TCPD. TCPD tuned with DMUXDelAdjCtrl pins have good setup hold times between Clkln Data.
Figure Start with Asynchronous rest, ratio, mode
With nominal tuning DMUXDelAdj Ghz, data lost because internal clock path propagation delay TCPD. TCPD tuned with DMUXDelAdjCtrl pins have good setup hold times between Clkln input data. This timing diagram does change with opposite phase Clkln.
Figure Start with Asynchronous Rest, ratio, DR/2 mode
Product Specification
Product specification
With nominal tuning DMUXDelAdj, (1:4 mode) data lost because internal clock path propagation delay TCPD. TCPD tuned with DMUXDelAdjCtrl pins used have good setup hold times between Clkln input data.
Figure Start with Asynchronous Reset, ratio, mode
With nominal tuning DMUXDelAdj, (1:4 mode) data lost because internal clock path propagation delay TCPD. TCPD tuned with DMUXDelAdjCtrl pins used have good setup hold times between Clkln input data. This timing diagram does change with opposite phase Clkln.
Figure Start with Asynchronous Reset, ratio, DR/2 mode
TS81102G0
TS81102G0
5.4.4. TIMING DIAGRAMS WITH SYNCHRONOUS RESET Example Synchronous Reset usefulness case desynchronization DMUX output port selection. desynchronization event happens after selection Port DMUXDelAdjCtrl value nominal. TSSR because Clkln internal propagation delay TCPD.
Figure Synchronous Reset, ratio, mode
Example Synchronous Reset usefulness case desynchronization DMUX output port selection. desynchronization event happens after selection Port DMUXDelAdjCtrl value nominal. TSSR because Clkln internal propagation delay TCPD.
Figure Synchronous Reset, ratio, mode Example Synchronous Reset usefulness case desynchronization DMUX output port selection. desynchronization event happens after selection Port
Product Specification
Product specification
DMUXDelAdjCtrl value nominal. TSSR because Clkln internal propagation delay TCPD.
Figure Synchronous Reset, ratio, DR/2 mode
Example Synchronous Reset usefulness case desynchronization DMUX output port selection. desynchronization event happens after selection Port DMUXDelAdjCtrl value nominal. TSSR because Clkln internal propagation delay TCPD.
Figure Synchronous Reset, ratio, DR/2 mode Note case clock frequency start with asynchronous reset, only first data lost first data processed second one. This data DEMUX port
TS81102G0
TS81102G0
5.5.
EXPLANATION TEST LEVELS
100% production tested 100% production tested sample tested specified temperature. Sample tested only specified temperature. Parameter guaranteed design characterization testing (thermal steady-state conditions specified temperature). Parameter typical value only.
Only values guaranteed (typical values issuing from characterization results). level tests performed 50MHz.
Product Specification
Product specification
6.1.
PACKAGE DESCRIPTION
DESCRIPTION
Name I[0.9] Clkln Outputs A[0.9] H[0.9] RefA RefH Control Signals ClklnType RatioSel Bist SwiAdj Diode NbBit Synchronization AsyncReset SyncReset DMUXDelAdjCtrl Levels Differential Differential Adjustable Logic Single Adjustable Logic Differential Adjustable Single Comments Data input. On-chip ohms differential termination resistor Clock input (Data Ready ADC). On-chip ohms differential termination resistor Data ready port Common mode adjusted with VplusDOut. Swing adjusted with SwiAdj. termination possible. Data ready channel Common mode adjusted with VplusDOut. Swing adjusted with SwiAdj. termination possible. Reference voltage output channels Common mode adjustable with VplusDOut. termination possible. DataReady Dataready/2 logic Data Ready DMUX ratio logic Reset Switch built-in Self Test (BIST) logic BIST active Swing fine adjustment output buffers Diode chip temperature measurement. Number logic Asynchronous reset logic reset Synchronous reset active rising edge Control delay line DataReady input differential input delay differential input delay differential input delay Control delay line differential input delay differential input delay differential input delay Stand-alone delay adjust input ADC. Differential termination inside buffer. Stand-alone delay adjust output ADC. Common ground Digital negative power supply Common mode adjustment output buffers. Digital positive power supply.
Type Digital Inputs
Analog Differential Differential analog input around common mode. Differential analog input around common mode. Differential differential output Ground Power Adjustable power from Power
ADCDelAdjCtrl
ADCDelAdjln ADCDelAdjOut Power Supplies VPlusDOut
TS81102G0
TS81102G0
6.2. TBGA PACKAGE PINOUT
name VPLUSDOUT VPLUSDOUT VPLUSDOUT VPLUSDOUT VPLUSDOUT VPLUSDOUT CLKINB CLKIN REFG VPLUSDOUT SWIADJ name RATIOSEL VPLUSDOUT VPLUSDOUT VPLUSDOUT VPLUSDOUT VPLUSDOUT VPLUSDOUT ADCDELADJOUT ADCDELADJOUTB REFH VPLUSDOUT VPLUSDOUT VPLUSDOUT VPLUSDOUT VPLUSDOUT VPLUSDOUT name ADCDELADJIN ADCDELADJINB VPLUSDOUT VPLUSDOUT VPLUSDOUT VPLUSDOUT VPLUSDOUT VPLUSDOUT VPLUSDOUT VPLUSDOUT VPLUSDOUT REFD BIST CLKINTYPE ADCDELADJCTRL REFF REFB NBBIT ADCDELADJCTRLB name REFA DMUXDELADJCTRL RSTSYNCB REFC ASYNCRESET DMUXDELADJCTRLB RSTSYNC REFE VPLUSDOUT VPLUSDOUT VPLUSDOUT VPLUSDOUT VPLUSDOUT VPLUSDOUT VPLUSDOUT VPLUSDOUT VPLUSDOUT DIODE
Product Specification
Product specification
RstSyncb Demuxdeladjctrcl
VPLUSD
VPLUSD
VPLUSD
REFA
VPLUSD
VPLUSD
REFC
VPLUSD
VPLUSD
VPLUSD
REFG
RstSync Demuxdeladjctrclb Asyncreset
VPLUSD
VPLUSD
REFE
DIODE
VPLUSD
VPLUSD
VPLUSD
VPLUSD
VPLUSD
VPLUSD
VPLUSD
CLKb
BIST
SWIadj
REFH
VPLUSD RATIOSEL
VPLUSD
VPLUSD
VPLUSD
VPLUSD
ADCdelayadjoutB ADCdelayadjout
ADCdelayadjinB ADCdelayadjin
VPLUSD
VPLUSD
VPLUSD
VPLUSD
VPLUSD
VPLUSD
VPLUSD
VPLUSD
VPLUSD
VPLUSD
VPLUSD
VPLUSD
VPLUSD
VPLUSD
VPLUSD
ADCDELADJCTRL CLKINTYPE
REFB
REFD
REFF
ADCDELADJCTRLbNbBIT
TBGA PACKAGE BOTTOM VIEW
TS81102G0
TS81102G0
6.3. OUTLINE DIMENSIONS TAPE BALL GRID ARRAY
Product Specification
Product specification
6.4.
6.4.1.
THERMAL MOISTURE CHARACTERISTICS
THERMAL RESISTANCE FROM JUNCTION CASE RTHJC
from junction case TBGA package estimated 0.7dec/W which decomposed Silicon degC/W attach epoxy 0.5degC/W (thickness 50um) Copper block (back side package) 0.1degC/W. 6.4.2. THERMAL RESISTANCE FROM JUNCTION AMBIENT RTHJA
pin-fin type heatsink, size used reduce thermal resistance. This heatsink should glued package could guarantee attach board such configuration. heatsink could clipped screwed board. With such heatsink Rthj-a about 6degC/W. take degC/W through heatsink parallel with 15degC/W through balls). Without heatsink, junction package reported board estimated from 20degC/W (depending board used). worst value 20degC/W given 1-layer board (13degC 4-layer board).
6.4.3. TEMPERATURE DIODE CHARACTERISTIC
theoretical characteristic diode, function temperature when I=3mA depicted below
TEMPERATURE DIODE CHARACTERISTIC 6.4.4. MOISTURE CHARACTERISTICS
This device sensitive moisture (MSL3 according JEDEC standard). Shelj life sealed months <40°C <90% relative humidity (RH). After this opened, devices that will subjected infrared reflow, vapor-phase reflow, equivalent processing (peak package body temp. 220°C) must mounted within hours factory conditions 30°C/60% stored Devices require baking, before mounting, Humidity Indicator >20% when read 23°C 5°C. baking required, devices baked hours 40°C 5°C/-0°C temperature device containers, hours 125°C high-temperature device containers.
TS81102G0
TS81102G0
6.5. DETAILLED CROSS SECTION
Here detailed cross section DEMUX TBGA package
IMPORTANT NOTE DEMUX package (see above), backside attached copper heatspreader copper heatspreader -5V. necessary heatsink which will tied copper heatspeader. Moreover, there only little layer painting over copper heatspreader this isolating recommended either isolate heatsink from others components board isolate electrically copper heatspreader from heatsink. this second case, adequate electrical isolation.
Product Specification
Product specification
APPLYING TS81102G0 DEMUX
TSEV81102G0 DEMUX evaluation board been designed connected with TSEV8388G TSEV83102G0 evaluation boards.
VplusD 3.3V diff. (2GHz) CLOCK BUFFER (125 MHz) 8X8b/10b single A[0.9]H[0.9]
DEMUX
Clkln Analog Input GHz) 8b/10b diff Data Data Ready I[0.9] GHz) diff. Clkln delay RefA RefH
(250 MHz) diff.
8bits 1GHz TS8388B 10bits 2GHz TS83102G0
Rload
Delay adjust control Number bits (8/10)
VplusD ground Rload Synchronous Asynchronous Reset VplusD Rload ground PECL VplusD Rload
TS81102GO
specific document "DEMUX APPLICATION NOTES" will available soon.
DMUX connections DMUX inputs configuration been optimized connected TS8388B ADC. TBGA package down. ADC, different types packages used such CBGA with down CQFP68 with DMUX device being completely symmetrical, both packages connected TBGA package DMUX without crisscrossing lines (see table below). digital outputs CQFP68 package DMUX data inputs TBGA package connected connected digital outputs CBGA package DMUX data inputs TBGA package connected connected
TS81102G0
ASIC
(DC)
TS81102G0
TSEV81102G0TP DEVICE EVALUATION BOARD
TSEV81102 GENERAL DESCRIPTION
TSEV81102G0TP DMUX Evaluation Board (EB) been designed simplify characterization evaluation TS81102G0 device (2Gsps DMUX). DMUX enables test functions DMUX Synchronous Asynchronous reset functions, selection DMUX ratio (1:4 1:8), selection number bits 10), output data common mode swing adjustment, junction temperature measurements over military temperature range, etc. DMUX been designed enable easy connection with ATMEL-Grenoble Evaluation Boards (e.g. TSEV8388BG TSEV83102G0GL) extended functionality evaluation (ADC+DMUX multi-channels applications). DMUX comes fully assembled tested, with TS81102G0 device implemented board heatsink assembled device.
Product Specification
Product specification
9.1.
ORDERING INFORMATION
PACKAGE DEVICE
81120GO
Manufacturer prefix Device family
Screening level Standard
Temperature range 110°C Package Tape ball Grid Array (240 balls)
9.2.
FORM
81102GO
Revision mask
prefix Manufacturer prefix
Probe test temperature Tamb 25°C Tamb high temp.
Device family
Back side metallization Naked Silicon Screening levels visual inspection ATMEL-GRENOBLE availability different versions, contact your ATMEL-Grenoble sale office
9.3.
EVALUATION BOARD
83102G0
Manufacturer prefix Evaluation board prefix
output modes available Package Tape ball Grid Array (240 balls)
TS81102G0
TS81102G0
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