26COM/80SEG Controller/Driver JUL. 2001 Version SUNPLUS TECH
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SPLC093A1
26COM/80SEG Controller/Driver
JUL. 2001 Version
SUNPLUS TECHNOLOGY infringement patent other rights third parties which result from use. addition, SUNPLUS products authorized critical components life support devices/ systems aviation devices/systems, where malfunction failure product reasonably expected result significant injury user, without express written approval Sunplus.
SPLC093A1
Table Contents
PAGE
GENERIAL DESCRIPTION. FEATURES. BLOCK DIAGRAM SIGNAL DESCRIPTIONS FUNCTIONAL DESCRIPTIONS. 5.1. SYSTEM INTERFACE 5.2. ADDRESS COUNTER (AC) 5.3. DISPLAY DATA (DDRAM) 5.4. CHARACTER GENERATOR (CGRAM) 5.5. CHARACTER GENERATOR (CGROM) 5.6. SEGMENT ICON (ICONRAM) 5.7. DRIVER CIRCUIT 5.8. POWER CONSUMPTION MODE 5.9. INSTRUCTION DESCRIPTION 5.10. DD/CG ADDRESS 5.11. ICONRAM ADDRESS 5.12. WRITE DATA 5.13. READ DATA INITIALIZING POWER SAVE MODE SETUP 6.1. HARDWARE RESET 6.2. INITIALIZING POWER SAVE SETUP DRIVING POWER SUPPLY CIRCUIT 7.1. VOLTAGE CONVERTER 7.2. VOLTAGE REGULATOR 7.3. ELECTRONIC CONTRAST CONTROL STEPS) 7.4. VOLTAGE GENERATOR CIRCUIT 7.5. INTERFACE ELECTRICAL SPECIFICATIONS 8.1. ABSOLUTE MAXIMUM RATINGS 8.2. CHARACTERISTICS. 8.3. CHARACTERISTICS APPLICATION INFORMATION PANEL. 9.1. CHIP BOTTOM LOWER VIEW "0", DIRS "0"). 9.2. CHIP BOTTOM UPPER VIEW "1", DIRS "1") 9.3. CHIP LOWER VIEW "0", DIRS "1") 9.4. CHIP UPPER VIEW "1", DIRS "0") FRAME FREQUENCY. 10.1. 1/17 DUTY (2-LINE MODE) 10.2. 1/25 DUTY (3-LINE MODE)
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CHARACTER GENERATOR 11.1. SPLC093A1 PACKAGE/PAD LOCATIONS 12.1. ASSIGNMENT 12.2. SPLC093A1 DIMENSIONS 12.3. ORDERING INFORMATION 12.4. LOCATIONS DISCLAIMER. REVISION HISTORY
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26COM/80SEG CONTROLLER/DRIVER
GENERIAL DESCRIPTION
SPLC093A1, driver controller matrix character display system, designed display lines 16-character with dots format. Cooperating with microprocessors, supports 4-bit 8-bit parallel modes well clock synchronized serial mode. voltage converter, double oscillator, voltage regulator, voltage follower bias circuit have been built SPLC093A1 advanced functions. supported. strong height character mode line vertical scroll functions also With SUNPLUS state-of-the-art technology SPLC093A1 provides best cost backup, Built-in Analog Circuit Internal oscillator circuit external clock Electronic volume contrast control steps) Voltage converter voltage regulator voltage follower
bias circuit
Power Operation Sleep mode operation Normal mode operation Operating Voltage Range Power supply voltage (VDD): 2.4V 4.0V driving voltage (VLCD VSS): 6.0V Max. Applicable Panel Size
performance ratio industry.
FEATURES
Driver Output Common output: common Segment output: segment Internal Memory Character Generator (CGROM): 10,240 bits (256 characters dots) Character Generator (CGRAM): bits characters dots) Display Data (DDRAM): bits characters lines) Segment Icon (ICONRAM): bits icons) Interface busy interface busy check execution waiting time) 8-bit parallel interface mode: 68-series 80-Series. 4-bit parallel interface mode: 68-series 80-Series. Serial interface mode: pins clock synchronized serial interface. Function Various instruction set: display control, power save, power
Font
Display
Duty
Contents outputs
2-line characters 3-line characters
1/17 characters icons 1/25 characters icons
BLOCK DIAGRAM
RESET
DB7(SI) bit/8 Interface Parallel Instruction Register (IR)
Oscillator
Timing Generator
Instruction Decoder
Address Counter
bits Shift Register Display Data (DDRAM) bits
Common Driver
COM1 COM24
DB6(SCL)
Serial
Data Register (DR) Data Output Register (OR)
bits Shift Register bits Latch Circuit Segment Driver SEG1 SEG80
Interface
Input Buffer
Icon bits
Character Generator (CGRAM) bits
Character Generator (CGROM) 10240 bits
Cursor Blink Controller
Driver Voltage Selector
Segment Data Conversion
Driving Power Circuit Voltage Converter Voltage Regulator Voltage Follower Bias Resister
CAP1P
CAP1N CAP2P
CAP2N
VOUT
VEXT
DIRS
control, etc. bi-directional (4-type application available) Hardware reset RESET Package Type Gold bumped chip
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SIGNAL DESCRIPTIONS
Mnemonic Type Description
Power Power
Power supply Connect power supply pin. (GND) Bias voltage level driving Voltages should have following relationships: V0V1V2V3V4VSS When built-in power circuit active internal bias resistors used.
bias bias (4/5) (3/5) (2/5) (1/5)
When built-in power circuit active internal bias resistors used. bias bias CAP1P CAP1N CAP2P CAP2N VOUT VEXT (3/4) (2/4) (1/4)
Capacitor connecting internal voltage converter Capacitor connecting internal voltage converter Capacitor connecting internal voltage converter Capacitor connecting internal voltage converter DC/DC voltage converter output (7.2V) Voltage adjust This gives voltage between resistance-division voltage. External reference voltage internal regulator (instead internal VREF, 1.8V) "Low (VSS)": VEXT used (open). "High (VDD)": VEXT reference-input voltage internal voltage regulator.
Select input voltage internal voltage regulator "Low (VSS)": input voltage internal Voltage regulator internal VREF(1.8V). "High (VDD)": input voltage internal Voltage regulator voltage VEXT.
RESET
Reset input SPLC093A1 initialized while RESET low.
External clock input. must fixed "High" "Low" when internal case external clock mode, used
oscillation circuit used.
clock should OFF. interface selection input "Low": 80-series "High": 68-series Parallel serial selection input When "Low": serial mode When "High": 4-bit 8-bit mode Chip selection input SPLC093A1 selected while low.
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Mnemonic Type Description
Interface data length selection parallel data input When "Low" "Low" "High": serial interface mode When "High" "Low": 4-bit mode "High": 8-bit mode
DIRS
direction selection input When DIRS "Low" SEG1SEG2SEG79SEG80 When DIRS "High" SEG80SEG79SEG2SEG1
Register selection input When "Low", instruction register When "High", data register.
80-series interface mode This connected active write signal
68-series interface mode This connected When "Low", write mode When "High", read mode COMI1 COMI2 SEG1 SEG80 TEST1 TEST2 Common signal output icon display These same signal name different. Segment signal output driving Test This used normal operation. 80-series interface mode This connected active read signal 68-series interface mode This connected enabling read write command according signal. (SCL) (SI) COM21 COM24 COM17 COM20 COM9 COM16 COM1 COM8 When 8-bit mode, used bi-directional data During 4-bit mode, only used. this case pins used. When serial mode, DB6(SCL) used serial clock input DB7(SI) used serial data input pin. Common signal output driving (TEST1, TEST2: open)
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FUNCTIONAL DESCRIPTIONS
5.1. System Interface
types interface with available: mode serial mode. Serial mode selected pin. mode, 4-bit 8-bit selected pin, series series selected pin.
series
mode
series
(H)/(L)
(H)/(L)
(H)/(L)
Serial mode
(H)/(L)
Note1: Don't care (high, open) Note2: Fixed high (VDD) (VSS)
(DB6) (DB7)
"High" mode, "Low" serial mode "High" 68-series MPU, "Low" 80-series "High" 8-bit mode, "Low" 4-bit mode (PS: "High") "High" chip selected, "Low" chip selected "High" data register, "Low" instruction register Read Write indicating signal mode active signal enabling write mode Enable read write command according signal mode. Serial clock input Serial data input Active signal enabling read mode.
5.1.1. Interface with Parallel Mode "High")
During writing operation, 8-bit registers, Data Register (DR) Instruction Register (IR), used. Data Register (DR) used temporary data storage place being written into DDRAM CGRAM ICONRAM these RAMs selected address setting instruction. from MPU. Instruction Register (IR) used only storing instruction code transferred select register, input used. 4-bit mode, needs transfer 4-bit data (through DB7) twice. During reading operation, 8-bit register Output Data Register (OR) used. Output Data Register (OR) used temporary data storage place being read from DDRAM CGRAM ICONRAM these RAMs selected address setting instruction. After address setting, first 4-bit mode, after reading dummy cycle 8-bit mode (figure valid data comes from second reading. high bits (for 8-bit mode DB7) written before bits (for 8-bit mode DB3) write. 8-bit mode DB7) read transaction. floated this 4-bit mode. (figure valid data comes from third reading. dummy reading makes Address Counter (AC) increased Therefore, recommended address again before writing. instruction read cycle supported regarded operation cycle.
bits (for 8-bit mode DB3) read before high bits (for pins After RESET resets,
SPLC093A1 considers first 4-bit data from high bits.
address setting, first second reading dummy cycles
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Instruction Write Dummy Read
Valid Data
Read
Data Write
Figure 8-bit Parallel Mode Data Transfer (68-series Mode)
Instruction Write Dummy Read
Valid Data
Read
Data Write
Figure Timing Diagram 8-bit Parallel Mode Data Transfer (80-series Mode)
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upper 4-bit
lower 4-bit
lower 4-bit
upper 4-bit
upper 4-bit
lower 4-bit
Instruction Write
Dummy Read
Read
Data Write
Figure3: Timing Diagram 4-bit Parallel Mode Data Transfer (68-series Mode)
upper 4-bit
lower 4-bit
lower 4-bit
upper 4-bit
upper 4-bit
lower 4-bit
Instruction Write
Dummy Read
Read
Data Write
Figure Timing Diagram 4-bit Parallel Mode Data Transfer (80-series Mode)
5.1.2. Interface with serial mode "Low")
When input "Low", clock synchronized serial interface mode selected. this moment, RESET (reset input), from serial data input DB7) rising edge serial clock (SCL DB6). rising edge serial clock, serial data converted into 8-bit mode data. setting "Low", SPLC093A1 able receive input. "High", SPLC093A1 resets internal 8-bit shift register 3-bit counter. Serial data input order "D7, input DR/IR selection latched rising edge serial clock (SCL)
(DB6, synchronizing transfer clock), (DB7, serial input data), (register selection input) (chip selection input) used.
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SI(DB7) SCL(DB6)
Figure Timing Diagram Serial Data Transfer
5.2. Address Counter (AC)
Address Counter (AC) SPLC093A1 stores DDRAM/ CGRAM/ ICONRAM address. After writing into reading from DDRAM CGRAM ICONRAM, automatically incremented There only address counter that stores address among DDRAM/CGRAM/ICONRAM.
5.3. Display Data (DDRAM)
DDRAM stores display data maximum bits (Max. characters). DDRAM address Address Counter (AC) hexadecimal number.
COM1 COM8 COM9 COM16 Hidden Line
16th
Hidden Line
SEG1
line mode DDRAM Address
SEG80
COM1 COM8 COM9 COM16 COM17 COM24
Hidden Line
SEG1
SEG80
line mode DDRAM Address
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5.4. Character Generator (CGRAM)
CGRAM 8-dot characters. writing font data CGRAM, user-defined character applied. CGRAM written regardless instruction table.
5.4.1. Relationship between character code (DDRAM) character pattern (CGRAM)
Character code (DDRAM data) DD/CGRAM address CGRAM data Pattern number
Pattern Pattern Pattern Pattern
(00h)
(01h)
(02h)
(03h)
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5.4.2. Relationship between character code (DDRAM) character pattern (CGRAM) (continued)
Character code (DDRAM data) DD/CGRAM address CGRAM data Pattern number
Note: Don't care
Pattern Pattern Pattern Pattern
(04h)
(05h)
(06h)
(07h)
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5.5. Character Generator (CGROM)
CGROM 8-dot characters. (Code: instruction table selects characters (00h 07h) CGROM CGRAM.
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5.6. Segment Icon (ICONRAM)
ICONRAM contains segment control data segment pattern data. COMI1 COMI2 same signal name different. result, icons same displayed number icons same time.
COMI
COMI
SEG1 SEG2 SEG3 SEG4 SEG5
Relationship between ICONRAM Icon Display
5.6.1. Relationship between ICONRAM address display pattern
ICONRAM address ICONRAM bits
Note: Don't care
SEG76 SEG77 SEG78 SEG79 SEG80
5.7. Driver Circuit
Driver circuit involves commons segments drive LCD. Data from ICONRAM/ CGRAM/CGROM transferred 80-bit segment register serially, then they stored 80-bit shift latch. case 2-line display mode (COM1 COM16), COMI1 COMI2 1/17 duty. 3-line mode (COM1 COM24), COMI1 COMI2 1/25 duty ratio. direction selected function instruction bit.
5.7.2. data shift direction
Line mode data shift direction
2-line mode
(left)
COM1 COM2. .COM15 COM16 COMI1 (COMI2)
(right) COM16 COM15. .COM2 COM1 COMI1 (COMI2) (left) 3-line mode COM1 COM2. .COM23 COM24 COMI1 (COMI2) (right) COM24 COM23. .COM2 COM1 COMI1 (COMI2)
bi-directional function selected DIRS input pin, shift
5.7.1. data shift direction
DIRS data shift direction
High
SEG1SEG2SEG3.SEG78SEG7 SEG80 SEG80SEG79SEG78. .SEG3SEG2 SEG1
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5.8. Power Consumption Mode
SPLC093A1 provides sleep mode power saving during standby period. Liquid crystal display output COM1 COM24, COMI1, COMI2: level SEG1 SET80: level Data written DDRAM, CGRAM, ICONRAM registers remained previous values. Operation mode retained same prior execution sleep mode. internal circuits stopped. Power Circuit Oscillation Circuit built-in power supply circuit oscillation circuit turned power saving command power controlling command.
5.8.1. Sleep mode (Power Save Oscillation OFF)
Entering into sleep mode, power circuit oscillation circuit should turned through power saving command power controlling command. This mode saves power consumption reducing current reset level.
5.9. Instruction Description 5.9.1. Instruction table
Instruction Description
DDRAM address from cursor returns Return home position. contents DDRAM changed. Double height mode DH2, normal display (default) COM1 COM16 double height, Doubleheight mode COM17 COM24 normal 2-line mode: normal display 3-line mode: COM1 COM8 normal, COM9 COM24 double height normal display Power save oscillation circuit oscillator (default) Power save oscillator power save (default) power save Display line mode 2-line display mode (default) 3-line display mode shifting direction COM. 2-line mode: COM1 COM16 (default) Function 3-line mode: COM1 COM24 (default) 2-line mode: COM16 COM1 3-line mode: COM24 COM1 Select CGRAM CGROM CGROM (default), CGRAM Cursor blink display Display control cursor (default), cursor blink (default), blink display (default), display
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Instruction Description
Write Data
Write DDRAM CGRAM ICONRAM Non-operation Instruction Determination DDRAM line which displayed first line LS2, DDRAM line shows first line
Line shift mode
(default). DDRAM line shows first line LCD. DDRAM line shows first line LCD. DDRAM line shows first line Determination bias
Bias control
bias (default) bias power control voltage converter (default) voltage converter
Power control
voltage regulator (default) voltage regulator voltage follower (default) voltage follower DDRAM CGRAM address
DD/CGRAM address ICONRAM address Read Data Test
Note1: "-": Don't care Note2: "*": Don't
Range: DDRAM CGRAM ICONRAM address, electronic volume
Range: ICONRAM (electronic volume byte). Read DDRAM CGRAM ICONRAM registers data (Note1) Don't this Instruction.
Note3: Instruction execution time depends internal process time SPLC093A1; therefore, needs provide time period larger than interface cycle time(tc) between execution successive instructions.
5.9.2. Return home
5.9.3. Double height mode
Return Home instruction field makes cursor return home. DDRAM address from cursor returns position. contents DDRAM changed.
Double Height mode instruction field selects double height line type. DH2, normal display line mode (default) COM1 COM16 double height, COM17 COM24 normal 2-line mode: normal display 3-line mode: COM1 COM8 normal COM9 COM24 double height normal display
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Line Normal Mode Display (DH2,
COM1 COM16 Double Height Line, COM17 COM24 Normal (DH2,
COM1 COM8 Normal, COM9 COM24 Double Height Line (DH2,
2-line Normal Mode Display (DH2,
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COM1 COM16 Double Height Line (DH2,
5.9.4. Power save
When "High", right shift When "Low", left shift (default) CGRAM enable When "High", CGRAM accessed this used eight special characters area. (00h CGRAM font display) When "Low", CGRAM disabled. saved using this mode (default). (00h CGROM font display) CGROM (00h 07h)
Power Save instruction field controls oscillator sets resets power saving mode. oscillator control When "High", oscillator turned When "Low", oscillator turned (default) power save control When "High", power save mode turned When "Low", power save mode turned (default)
accessed additional current consumption
5.9.5. Function
5.9.6. Line shift mode
display line mode Instruction field selects lines lines display mode When "High", lines display mode When "Low", lines display mode (default) data shift direction common sets shift direction common display data
Line Shift mode instruction field selects displayed first line. LS2, DDRAM line shows first line (default). DDRAM line shows first line LCD. DDRAM line shows first line LCD. DDRAM line shows first line LCD.
Line1 (00h 0Fh)
Line2 (10h 1Fh)
Line3 (20h 2Fh)
Line4 (30h 3Fh)
Line2 (10h 1Fh)
Line3 (20h 2Fh)
Line4 (30h 3Fh)
Line1 (00h 0Fh)
Line3 (20h 2Fh)
Line4 (30h 3Fh)
Line1 (00h 0Fh)
Line2 (10h 1Fh)
Line4 (30h 3Fh)
Line1 (00h 0Fh)
Line2 (10h 1Fh)
Line3 (20h 2Fh)
LS2,
LS2,
LS2,
LS2,
Line Shift Mode Display Line
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Line1 (00h 0Fh)
Line2 (10h 1Fh)
Line3 (20h 2Fh)
Line4 (30h 3Fh)
Line2 (10h 1Fh)
Line3 (20h 2Fh)
Line4 (30h 3Fh)
Line1 (00h 0Fh)
Line3 (20h 2Fh) Line4 (30h 3Fh)
Line4 (30h 3Fh)
Line1 (00h 0Fh)
Line2 (10h 1Fh)
Line1 (00h 0Fh)
Line2 (10h 1Fh)
Line3 (20h 2Fh)
LS2,
LS2,
LS2,
LS2,
Line Shift Mode Display Line
5.9.7. Bias control
5.9.9. Display control
Bias Control instruction field sets bias voltages generated internally. This used when internal voltage follower bias (default) bias
Display Control instruction field controls cursor blink display OFF. cursor control When "High", cursor turned When "Low", cursor disappeared current display (default).
5.9.8. Power control
cursor blink control When "High" "High", SPL093A makes alternate between inverting display character normal display character cursor position with approx. second. contrast, "Low", only normal character displayed regardless flag. When "Low", blink (default). display control When "High", entire display turned When "Low", display turned OFF, display data remained DDRAM (default).
Power Control instruction field sets voltage regulator/ converter/ follower off. voltage converter circuit control When "High", voltage converter turned When "Low", voltage converter turned (default). voltage regulator circuit control When "High", voltage regulator turned When "Low", voltage regulator turned (default). voltage follower circuit control When "High", voltage follower turned When "Low", voltage follower turned (default).
Note: oscillation circuit must turned voltage converter circuit active.
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Display state
(Blinking mode)
Cursor Attributes
5.10. DD/CG Address
5.11. ICONRAM Address
DD/CG Address Instruction field sets DDRAM CGRAM address. Before writing reading data into from RAM, address Address instruction. Then, when data written read successfully, address automatically incremented After accessing 7Fh, address 00h. address range 7Fh.
ICONRAM Address instruction field sets ICONRAM Registers address. Before writing/reading data into/from ICON RAM, address ICONRAM Address instruction. Next, when data written/read successfully, address automatically increased icons time blink bits display blink attributes ICON DD/CGRAM Address After instructions enabled.
same cursor blink.
instruction should before accessing DD/CGRAM.
5.10.1. DD/CG address mapping
Address
accessing 0Fh, address ICONRAM address 00h. ICONRAM address ranges -1Fh.
DDRAM line (00h 0Fh) DDRAM line (10h 1Fh) DDRAM line (20h 2Fh) DDRAM line (30h 3Fh) CGRAM pattern CGRAM pattern CGRAM pattern CGRAM pattern CGRAM pattern CGRAM pattern CGRAM pattern CGRAM pattern
5.11.1. ICONRAM address mapping
Address
ICON (00h 0Fh) Reserved
Electronic Volume Register (10h) default (00000) Test Register use) (11h) When registers written, address counter (AC) increased.
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5.12. Write Data
5.13. Read Data
This instruction field makes SPLC093A1 writing binary 8-bit data DDRAM CGRAM ICONRAM register. ICONRAM Address instruction. address automatically increased address written determined previous DD/CGRAM Address After writing operation,
DDRAM CGRAM ICONRAM data read instruction. Each selected address instruction. data read. second read transaction. second read transaction. Then,
correct data obtained from first read data after setting After reading operation, address
address dummy data; correct data comes from increased automatically.
INITIALIZING POWER SAVE MODE SETUP
6.1. Hardware Reset
When RESET "Low", SPLC093A1 initialized following states. Control Display Instruction cursor blink display Power Saves Instruction oscillator power save Power control instruction voltage regulator voltage converter voltage follower
Note: initialization done RESE pin, unknown condition occurred. also initialize instructions.
Function instruction 2-line display mode left shift CGRAM used. Return Home Address counter Electronic contrast control register: case 4-bit interface mode selection SPLC093A1 considers first 4-bit data from high order bits.
tRESET
RESET RESET pulse width RESET start time
RESET Timing
tRESET
10µs 50ns
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6.2. Initializing Power Save Setup 6.2.1. Initializing instruction 6.2.2. Sleep mode release instruction 6.2.2.1. Sleep mode
Power
Initialization
Keep RESET
Normal Operation Status (Power save Oscillator ON.)
When power stable, release reset state (RESET "H").
Command Input
Waiting 10us more
Display Control OFF) Power Save (PS: Power Save OFF) Power Control (VC, OFF)
Command Input Function Electronic Volume Register Setup (ICONRAM 10h) Power Save (PS: Power Save OFF, Power Control (VC,
Enter Sleep Mode
Waiting 20ms more
6.2.2.2. Sleep mode release
Command Input Address
Sleep Mode
Command Input Data Writing (RAM Clear) (DDRAM 20h, CG/ICONRAM 00h)
Command Input Power Save (PS: Power Save OFF, Power Control (VC,
Command Input Display Control
Waiting 20ms more
Initialization
Command Input Display Control
Note: command internal should cleared. clear DDRAM, address (first DDRAM) then write (space character code) times clear CGRAM, address (first CGRAM) then write (null data) times clear ICONRAM, ICONRAM address (first ICONRAM) then write (null data) times.
Return Normal Operation
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6.2.3. Recommendation Power Sequence 6.2.3.1. Power sequence 6.2.3.2. Power sequence
Power
Operation Command Input
Display
Voltage Converter [VC,
Waiting for1ms
Voltage Regulator [VC,
Voltage Regulator [VC,
Waiting for50ms
Voltage Follower [VC,
Waiting for1ms
Waiting for1ms
Voltage Follower [VC,
Voltage Converter [VC,
Waiting for1ms
Operation Command Input
Operation Command Input
DRIVING POWER SUPPLY CIRCUIT
Power Supply Circuit produces panel driving voltage power consumption. Driving Power Supply circuit consists Voltage converter, Voltage regulator, Voltage
Power Supply Control Mode Voltage converter Voltage regulator Voltage follower VOUT
follower.
controlled power control instruction.
following table shows Driving Power Supply circuit works power control instruction sets.
Internal Enable Enable Enable voltage output External Disable Enable Enable voltage input Disable Disable Disable Disable Enable Disable Open Open
Used voltage Adjustment Used Voltage Adjustment Open Open
Internal voltage output
Internal voltage output internal voltage output external voltage input external voltage input
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7.1. Voltage Converter
Voltage Converter circuit generates positive voltage level times 1.8V that generated internally. from voltage converter. built-in Voltage regulator circuit. same 3-times DC/DC converter. VOUT generated This conversion voltage used This application circuit
internal VREF voltage regulator temperature compensation function, temperature coefficient is±0.03%/
VOUT
VOUT SPLC093A1 CAP1P 1.8V 7.2V 1.8V (Internal) CAP1N CAP2P CAP2N VOUT
VEXT VREF Inside Chip
DC/DC Converter Output Circuit
7.2. Voltage Regulator
Voltage Regulator circuit used obtain appropriate panel driving voltage. This voltage obtained adjusting
Voltage Regulator Circuit
7.3. Electronic Contrast Control Steps)
Electronic Contrast Control data bits (C4, C0). Voltage regulation adjusted 32-contrast steps according value Electronic Contrast Control data bits. driving voltage, voltage values 5-bit data electronic contrast control register (ICONRAM address 10h). When using Electronic Contrast Control function, voltage regulators need turned power control instruction.
resistors shown equation (2), setting electronic contrast control data bits, equation (4). potential adjusted within VOUT VREF. VREF internal constant voltage source chip this value 1.8V condition VDD2.4V
selects which voltage used voltage regulator between external VEXT internal VREF.
Voltage regulation adjusting resistors
When "Low" VREF
VREF /150
When "Low" VREF When "High" VEXT
When "High" VEXT
VEXT /150
Electronic Contrast Control Register Contrast
("-": Don't care)
0(default)
Maximum Minimum
High
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VOUT
VEXT VREF
Inside Chip
Electronic Contrast Control Circuit
7.4. Voltage Generator Circuit
SPLC 093A1 CAP1P CAP1N CAP2P CAP2N VOUT
When Built-in Power Supply used (VC,
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CAP1P CAP1N CAP2P External Power Supply CAP2N VOUT CAP1P CAP1N CAP2P CAP2N VOUT CAP1P CAP1N CAP2P CAP2N VOUT
(VC, External Power Supply (VC, capacitor 4.7µF External Power Supply
(VC,
When External Power Supply used
7.5. Interface
IORQ
Decoder
SPLC093A1
DB[7:0] RESET
RESET
Parallel Interfacing with 8080-series Microprocessors
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Decoder
DB[7:0]
SPLC093A1
RESET RESET
Parallel Interfacing with 6800-series Microprocessors
PORT4 PORT3
PORT1 PORT2
SPLC093A1
SCL(DB6) SI(DB7)
RESET
RESET
Clock Synchronized Serial Interfacing with Microprocessors
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ELECTRICAL SPECIFICATIONS
8.1. Absolute Maximum Ratings
Characteristic Symbol Value Unit
Power supply voltage Power supply voltage Power supply voltage Input voltage Operating temperature Storage temperature
conditions AC/DC Electrical Characteristics. Note2: voltage levels based
VOUT, TOPR TSTG
-0.3 -0.3 -0.3 -0.3 VDD+0.3 +125
normal operational
Note1: Stresses beyond those given Absolute Maximum Rating table cause operational errors damage device.
Voltage greater than above damage circuit. Voltage level: VOUTV0VDDVSS. Voltage level: V0V1V2V3V4VSS.
8.2. Characteristics
(VDD 2.4V 4.0V, +70)
Item Symbol Condition Min. Typ. Max. Unit
Operating Voltage
IDD1
Display operation VLCD 6.0V without load access from Access operation from (FCYC 200KHz) Sleep operation without load Oscillator off, Power save -1.0mA, 2.4V 1.0mA, 2.4V ±50µA ±50µA 3.0V, 1.0µF VLCD
Supply Current (VDD 3.0V,
IDD2 IDDS1
0.7VDD VDD-0.4 -1.0 -3.0 1.70
1.75
0.3VDD 1.80
Input Voltage
RCOM RSEG VOUT VREF VLCD
Output Voltage Input Leakage Current Output Leakage Current Resistance Frame frequency (Internal OSC) Voltage Converter Conversion Efficiency Output Voltage
Voltage regulator reference Voltage Driving Voltage
Note RESET schmitt input (0.8VDDVIHVDD, VSSVIL0.2VDD).
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8.3. Characteristics 8.3.1. Parallel write interface Mode)
(VDD 2.4V 4.0V, +70)
Symbol Min. Typ. Max. Unit
Cycle Time Pulse Rise Fall Time Pulse Width High pulse Width Setup Time Hold Time Setup Time Hold Time
tSU1 tSU2
tSU1 tSU2
Valid Data
Write Timing Diagram Series)
8.3.2. Parallel read interface Mode)
(VDD 2.4V 4.0V, +70)
Symbol Min. Typ. Max. Unit
Cycle Time Pulse Rise Fall Time Pulse Width High pulse Width Setup Time Hold Time Output delay Time Output Hold Time
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Valid Data
Read Timing Diagram Series)
8.3.3. Parallel write interface Mode)
(VDD 2.4V 4.0V, +70)
Characteristic Symbol Min. Typ. Max. Unit
Cycle Time Pulse Rise Fall Time Pulse Width High Pulse Width Setup Time Hold Time Setup Time Hold Time
tSU1 tSU2
tSU1 tSU2 Valid Data
Write Timing Diagram Series)
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8.3.4. Parallel read interface Mode)
(VDD 2.4V 4.0V, +70)
Characteristic Symbol Min. Typ. Max. Unit
Cycle Time Pulse Rise Fall Time Pulse Width High Pulse Width Setup Time Hold Time Output delay Time Output Hold Time
Valid Data
Read Timing Diagram Series)
8.3.5. Clock synchronized serial mode
(VDD 2.4V 4.0V, +70)
Characteristic Symbol Min. Typ. Max. Unit
Clock Cycle Time Pulse Rise Fall Time Clock Width (High, Low) Setup Time Hold Time Data Setup Time Data Hold Time Data Setup Time Data Hold Time
tSU1 tSU2 tSU3
1000
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tSU1
tSU2
tSU3
Clock synchronized serial Interface Mode Timing Diagram
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APPLICATION INFORMATION PANEL
9.1. Chip Bottom Lower View "0", DIRS "0")
COM20 COM19 COM18 COM17 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COMI1
SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1
SEG80 SEG79 SEG78 SEG77 SEG76
BOTTOM VIEW
COMI2 COM24 COM23 COM22 COM21 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9
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9.2. Chip Bottom Upper View "1", DIRS "1")
COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM21 COM22 COM23 COM24 COMI2
BOTTOM VIEW
SEG71 SGE72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG1 SEG2 SEG3 SEG4 SEG5
COMI1 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM17 COM18 COM19 COM20
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9.3. Chip Lower View "0", DIRS "1")
COMI2 COM24 COM23 COM22 COM21 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9
SEG1 SEG2 SEG3 SEG4 SEG5
SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80
VIEW
COM20 COM19 COM18 COM17 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COMI1
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9.4. Chip Upper View "1", DIRS "0")
COMI1 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM17 COM18 COM19 COM20
VIEW
SEG80 SEG79 SEG78 SEG77 SEG76 SEG10 SGE9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1
COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM21 COM22 COM23 COM24 COMI2
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FRAME FREQUENCY
10.1. 1/17 Duty (2-line mode)
1-line Selection Period Clocks Frame Frame Frequency 36.8µs 10ms Clock 36.8µs =27.2KHz) 10ms 100Hz
10.2. 1/25 Duty (3-line mode)
1-line Selection Period Clocks Frame Frame Frequency 25µs 10ms Clock 25µs =40KHz) 10.0
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CHARACTER GENERATOR
11.1. SPLC093A1
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PACKAGE/PAD LOCATIONS
12.1. Assignment
SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80
COMI2 COM24 COM23 COM22 COM21 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9
COM20 COM19 COM18 COM17 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COMI1 TEST2
SPLC093A1
RESET
VEXT
VEXT
CAP2N
CAP2N
CAP1N
CAP1N
CAP2P
CAP2P
CAP1P
12.2. SPLC093A1 Dimensions
Item Size Unit
Chip Size pitch
6320 75.6 85.5 50.4 60.3
2020 75.6 50.4 85.5 85.5
Bumped size
Bumped height
Note1: Chip size included scribe line.
Note2: ensure function properly, please bond pins. Note3: 0.1µF capacitor between should placed close possible.
12.3. Ordering Information
Product Number Package Type
SPLC093A1-nnnnV-C
Note1: Code number (nnnnV) assigned customer. Note2: Code number (nnnn 0000 9999); version
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CAP1P
Chip form
JUL. 2001 Version:
TEST1
VOUT
VOUT
DIRS
SPLC093A1
12.4. Locations
Name Name
COMI2 COM24 COM23 COM22 COM21 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9
-3002 -3002 -3002 -3002 -3002 -3002 -3002 -3002 -3002 -3002 -3002 -3002 -3002 -2926 -2840 -2623 -2537 -2347 -2205 -2061 -1918 -1774 -1632 -1487 -1345 -1214 -1129 -1043 -958 -872 -787 -701 -616 -530 -445 -359 -274 -188 -103
-175 -251 -326 -402 -477 -845 -845 -845 -845 -845 -845 -845 -845 -845 -845 -845 -845 -845 -845 -845 -845 -845 -845 -845 -845 -845 -845 -845 -845 -845 -845 -845 -845 -845 -845
VOUT VOUT CAP2N CAP2N CAP2P CAP2P CAP1N CAP1N CAP1P CAP1P VEXT VEXT DIRS RESET TEST1 TEST2 COMI1 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM17 COM18 COM19 COM20 SEG1 SEG2 SEG3
1008 1093 1179 1264 1370 1451 1536 1622 1707 1912 1999 2084 2170 2374 2460 2677 2762 3002 2995 3002 3002 3002 3002 3002 3002 3002 3002 3002 3002 3002 3002 3002 2974 2899 2823
-845 -845 -845 -845 -845 -845 -845 -845 -845 -845 -845 -845 -845 -845 -845 -845 -845 -845 -845 -845 -845 -845 -845 -845 -845 -845 -616 -522 -447 -371 -296 -220 -144
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Name Name
SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42
2748 2672 2596 2521 2445 2370 2294 2218 2143 2067 1992 1916 1840 1765 1689 1614 1538 1462 1387 1311 1236 1160 1084 1009 -124
SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80
-200 -275 -351 -427 -502 -578 -653 -729 -805 -880 -956 -1031 -1107 -1183 -1258 -1334 -1409 -1485 -1561 -1636 -1712 -1787 -1863 -1939 -2014 -2090 -2165 -2241 -2317 -2392 -2468 -2543 -2619 -2695 -2770 -2846 -2921 -2997
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DISCLAIMER
information appearing this publication believed accurate. Integrated circuits sold Sunplus Technology covered warranty patent indemnification provisions stipulated terms sale only. SUNPLUS makes warranty, express, statutory implied description regarding information this publication regarding freedom described chip(s) from patent infringement. prices time without notice. FURTHER, SUNPLUS MAKES WARRANTY MERCHANTABILITY FITNESS PURPOSE. SUNPLUS reserves right halt production alter specifications Accordingly, reader cautioned verify that data sheets other information this Products described herein intended normal commercial applications. publication current before placing orders.
Applications involving unusual environmental reliability requirements, e.g. military equipment medical life support equipment, specifically recommended without additional processing SUNPLUS such applications. Please note that application circuits illustrated this document reference purposes only.
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REVISION HISTORY
Date Revision Description Page
JAN. 2001 MAY. 2001
Original Change "Code: "Code: "CHARACTER GENERATOR (CGROM)" Delete repeated figure INITIALIZING POWER SAVE SETUP" "Note2: 0.1µF capacitor between VSS." Delete "CHARACTER GENERATOR (SPLC093A1-04)" "REVISION HISTORY" Renew document format
JUL. 2001
Delete "PRELIMINARY" Note1 "12.2 SPLC093A1 Dimensions" "12.3 Ordering Information" Renew document format
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