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Driver with 112-Channel Outputs OCT. 2001 Version SUNPLUS TE


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SPLD112A1
Driver with 112-Channel Outputs
OCT. 2001 Version
SUNPLUS TECHNOLOGY reserves right change this documentation without prior notice. Information provided SUNPLUS TECHNOLOGY believed accurate reliable. However, SUNPLUS TECHNOLOGY makes warranty errors which appear this document. Contact SUNPLUS TECHNOLOGY obtain latest version device specifications before placing your order. responsibility assumed SUNPLUS TECHNOLOGY infringement patent other rights third parties which result from use. addition, SUNPLUS products authorized critical components life support devices/ systems aviation devices/systems, where malfunction failure product reasonably expected result significant injury user, without express written approval Sunplus.
SPLD112A1
Table Contents
PAGE
GENERAL DESCRIPTION. FEATURES. BLOCK DIAGRAM 3.1. BLOCK FUNCTION DESCRIPTION SIGNAL DESCRIPTIONS FUNCTIONAL DESCRIPTIONS. ELECTRICAL SPECIFICATIONS 6.1. ABSOLUTE MAXIMUM RATINGS 6.2. CHARACTERISTICS. APPLICATION CIRCUITS. 7.1. APPLICATION CIRCUIT (1). 7.2. APPLICATION CIRCUIT (2). 7.3. APPLICATION CIRCUIT (3).11 7.4. APPLICATION CIRCUIT (4). 7.5. TIMING PANEL DIMENSION SEGMENTS COMMONS) 7.6. TIMING CHARACTERISTIC OPERATION PACKAGE/PAD LOCATIONS 8.1. ASSIGNMENT 8.2. ORDERING INFORMATION 8.3. LOCATIONS DISCLAIMER. REVISION HISTORY
Sunplus Technology Co., Ltd. Proprietary Confidential
OCT. 2001 Preliminary Version:
SPLD112A1
DRIVER WITH 112-CHANNEL OUTPUTS
GENERAL DESCRIPTION
SPLD112A1, versatile matrix driver with power CMOS technology from Sunplus, capable providing varieties common/segment combinations application development. Ease use, high performance cost make SPLD112A1 ideal most related products. Level Driver Charge Pump. data shifting. This includes four primary blocks: 112-bit Shift Register, 112-bit Data Latch, 112-bit 112-bit Shift Register allows users select different common/segment types well 112-bit Data Latch basically responsible block Charge Moreover, loading data from Shift Register 112-bit Level Driver generate corresponding voltage level. Pump capable raising voltage level double triple (negative voltage level) original voltage level. waveform LCD. SPLD112A1 also converts serial data parallel data outputs
FEATURES
Operating voltage: 2.4V 6.0V driver voltage: Bias voltage supplied externally Built-in voltage converter( double triple) Serial data input Chain function (only segment) 1/48, 1/32 1/16 duty Segment common driver, combinations provided: Mode Mode0 Mode1 Common Segment
BLOCK DIAGRAM
D[112:1] 4-level Driver X112(seg/com) CUP2 charge Level shift selector pump CUP1 VSS2 112-bit Latch 112-bit shift register DO112 MODE0 MODE1
Sunplus Technology Co., Ltd. Proprietary Confidential
OCT. 2001 Preliminary Version:
SPLD112A1
3.1. Block Function Description
112-bit Shift Register Basically, this block data shift register. that defines various segment common ranges. functionality level Driver *112 block process example, when Mode0 Mode1 mode defined ModeB. ModeB, segments data segment enters from common enters from DO112. purpose Charge Pump Block generate double triple voltage level. signal control signal. When Charge When Charge Pump will enabled generate double/triple voltage. grounded. Pump will disabled voltage level VSS2 clock signal Charge Pump whose frequency suggested from 50KHz 300KHz D112 commons. data
Level Shift Selector Block uses DF(Frame Signal) needs data 112-bit-latch decode types voltage level control signals.
cooperate with Mode0 Mode1 select mode
control signal from Level Shift turns certain order corresponding voltage level.
Furthermore, according signal, data segment will enter into Shift Register continuously
shifting after another until
Shift Register.
other hand, data common will enter into 81th Shift Register continuously shifting until Shift Register. 112-bit-latch will load data Register from Shift Register when hold data when
Sunplus Technology Co., Ltd. Proprietary Confidential
OCT. 2001 Preliminary Version:
SPLD112A1
SIGNAL DESCRIPTIONS
Mnemonic Type Description
D112
Segment/Common output data shift clock; also used clock double/triple voltage generator. required between `DIN' `CP'. data
shifted 112-bit latch falling edge `CP'. data setup time data hold time alternate signal data load. When `LOAD' `HIGH', shift register contents transferred driver through level shifter. When `LOAD' `LOW', last display data which transferred when `LOAD' high, held. DO112 Segment data input. data applied this shifted transferred driver.
When `Mode-D' selected, content 112th Shift Register output from DO112. When Mode-A, Mode-B Mode-C selected, data applied `DO112' will shifted -65, bit-81 bit-
MODE0 MODE1 CUP1 CUP2
Mode-A, Mode-B, Mode-C Mode-D selector Power input Coupling capacitor change pump reference voltage input; highest: lowest:
Master enable: generate voltage tripler disable This should controlled CPU. programmed master. Before entering standby mode, `MEN' must Only driver programmed `LOW' turn double/triple voltage generator.
VSS2
Double voltage output Triple voltage output, `MEM' assigned `LOW', VSS2 will keep same voltage ground. This clock needed double/triple voltage generator. frequency suggested between 50KHz 300KHz depending loading between VEE.
Sunplus Technology Co., Ltd. Proprietary Confidential
OCT. 2001 Preliminary Version:
SPLD112A1
FUNCTIONAL DESCRIPTIONS
Four combinations provided different applications.
Mode Mode0 Mode1 Segment Common
O[64:1] SEG[1:64] O[112:65] COM[48:1] O[80:1] SEG[1:80] O[112:81] COM[32:1] O[96:1] SEG[1:96] O[112:97] COM[16:1] O[112:1] SEG[1:112]
COM/SEG
Data
Display Output Level
COMMON SEGMENT
Mode
Mode0
Mode1
D[64:1]
D[80:65]
D[96:81]
D[112:97]
Mode D112
BIT1
BIT2
BIT3
BIT4
BIT64
BIT65
BIT66
BIT112
DO112
Sunplus Technology Co., Ltd. Proprietary Confidential
OCT. 2001 Preliminary Version:
SPLD112A1
Mode D112
BIT1
BIT2
BIT3
BIT4
BIT80
BIT81
BIT82
BIT112
DO112
Mode D112
BIT1
BIT2
BIT3
BIT4
BIT96
BIT97
BIT98
BIT112
DO112
Mode D112 DO112
BIT1
BIT2
BIT3
BIT4
BIT80
BIT81
BIT82
BIT112
Sunplus Technology Co., Ltd. Proprietary Confidential
OCT. 2001 Preliminary Version:
SPLD112A1
ELECTRICAL SPECIFICATIONS
6.1. Absolute Maximum Ratings
Characteristics Symbol Ratings
supply Voltage supply Voltage input Voltage Range
conditions AC/DC Electrical Characteristics.
|VEE|
7.0V -0.5V VDD+0.5V
normal operational
Note: Stresses beyond those given Absolute Maximum Rating table cause operational errors damage device.
6.2. Characteristics
Characteristics Symbol Min. Limit Typ. Max. Unit Test Condition
Operating voltage Standby current Consumption current Input high level (CP, DIN, MODE0, MODE1, MEN, CKV) Input level Output high level Output level resister
ISTYB IGND
3.0V 3.0V, (see note) 100KHz 3.0V 3.0V
VDD-0.5
Note: resister 100K between VEE.
Sunplus Technology Co., Ltd. Proprietary Confidential
OCT. 2001 Preliminary Version:
SPLD112A1
0.1µ 0.1µ 0.1µ
0.1µ 0.1µ
VSS2
0.1µ
Doubler short VSS2 Tripler short LCDEN
SPL512A RESBP D[80:1] D[112:1] DO112
0.1µ
SPLD112A1
CUP1
VSS2
0.1µ
MODE0
MODE1
D[112:81] SEG[80:1] COM[32:1]
RESBP ROSC/32
APPLICATION CIRCUITS
7.1. Application Circuit
PANEL
Figure SPLD112A1, 1/32 duty, segments APPLICATION CIRCUIT
Sunplus Technology Co., Ltd. Proprietary Confidential
CUP2
0.1µ
OCT. 2001 Preliminary Version:
SPLD112A1
VSS2
0.1µ 0.1µ
0.1µ 0.1µ
0.1µ
0.1µ
Doubler short VSS2 Tripler short
LCDEN
VSS2
RESBP
VSS2
VSS2
0.2µ
SPL512A
SPLD112A
CUP2 MODE0 MODE1 DO112 O[112:1]
SPLD112A
0.1µ
CUP2
MODE0
MODE1
DO112
O[112:1]
O[64:1]
O[112:65] SEG[112:1] SEG[176:113]
RESBP ROSC/32
7.2. Application Circuit
COM[48:1]
PANEL
Figure SPLD112A, 1/48 duty, segments, APPLICATION CIRCUIT
Sunplus Technology Co., Ltd. Proprietary Confidential
CUP1
0.2µ
CUP1
OCT. 2001 Preliminary Version:
SPLD112A1
VSS2
0.1µ
0.1µ 0.1µ 0.1µ
0.1µ
0.1µ
Doubler short VSS2 Tripler short
LCDEN
0.1µ VSS2 0.1µ
RESBP
VSS2
VSS2
0.1µ
SPL512A
SPLD80A
CUP1 CUP2 MODE DO80 O[80:1]
0.1µ
SPLD112A1
CUP1
0.1µ
CUP2
MODE0
MODE1
DO112
D[112:1]
D[80:1]
D[112:81] SEG[80:1]
7.3. Application Circuit
RESBP ROSC/32
PANEL
Figure Application circuit SPLD80A SPLD112A1 driver panel
Sunplus Technology Co., Ltd. Proprietary Confidential
SEG[160:81]
COM[32:1]
OCT. 2001 Preliminary Version:
SPLD112A1
VSS2
0.1µ
0.1µ
0.1µ
0.1µ
0.1µ
0.1µ
Doubler short VSS2 Tripler short
LCDEN
VSS2 VSS2 CUP1
RESBP
0.1µ
VSS2
SPL512A
SPLD80A
SPLD80A
CUP2 MODE DO80 O[80:1]
CUP1 CUP2 MODE DO80 O[80:1]
SPLD112A1
CUP1
CUP2
MODE1 MODE0
DO112
D[112:1]
RESBP
7.4. Application Circuit
SEG[256:161]
COM[16:1]
PANEL
Figure Application circuit SPLD80A SPLD112A1 driver panel
Sunplus Technology Co., Ltd. Proprietary Confidential
SEG[80:1]
SEG[160:81]
OCT. 2001 Preliminary Version:
SPLD112A1
application circuit Figure uses SPL512A control SPLD112A1.
Connect substrate floating depending type panel used. example, panel with bias, must respectively. 1/7; contrast adjustment `LCDEN' SPLD512A connected `MEN' SPLD112A1 enabling disabling display avoid path current sleep mode. That is,R1/(4R1+R2) should
`CP' shift register clock data shifting. `CKV' source supplying Charge Pump generate double/triple voltage level (The range between 50KHz 300KHZ; value depended loading between VEE). frequency range closed CKV, possible short together.
Figure Timing Charts Application Example segment Driver Operation
DO112
Figure Timing Charts Application Example Common Driver Operation
Sunplus Technology Co., Ltd. Proprietary Confidential
OCT. 2001 Preliminary Version:
SPLD112A1
Followed recommended frequency range.
Rload Range (Depend Panel Size) Better Range (Hz) Available Range
120K Rload 300K Rload 120K Rload
Note: Rload
150K 100K 200K 200K 300K
200K 100K 300K 200K 400K
7.5. Timing Panel Dimension Segments Commons)
Assignments: DO112 Mode[1,0] [High,High] SEGMENTS[80.1] O[80.1] COMMONS[32.1] O[112.81] Voltage Define:
DF=1 DF=0
COMMON-Selection Alternative Voltage COMMON-NonSelection Alternative Voltage SEGMENTS Turn Voltage SEGMENTS Turn Voltage Pixel Turn Differential Voltage (VDD
Note: Data COM1 should shifted SPLD112 before Change High. (Which indicate Start Frame).
Sunplus Technology Co., Ltd. Proprietary Confidential
OCT. 2001 Preliminary Version:
SPLD112A1
Frame Duty COM1 Selected Period COM2 Selected Period
COM1
COM2
Sunplus Technology Co., Ltd. Proprietary Confidential
OCT. 2001 Preliminary Version:
SPLD112A1
7.6. Timing Characteristic Operation
(Operation Condition: Voltage 5.0V, Frequency 5.0MHz)
Parameter Symbol Min. Max. Unit
Data Latch Setup Time Data Latch Hold Time High High Width Common-Outputs High Segment-Outputs transition High (Hold Time)
Note: that Signal must "NonOverlap"
TWLD TLCOM TLSEG TDFFP TLDFP
Depend Load Depend Load
TWCP CP80
TWLD
TLSEG
TLCOM
SEGMENTS
COMMONS
TLDFP
TDFFP
Sunplus Technology Co., Ltd. Proprietary Confidential
OCT. 2001 Preliminary Version:
SPLD112A1
PACKAGE/PAD LOCATIONS
8.1. Assignment
Chip Size: 6510µm 3920µm This substrate should connected
Note1: Chip size included scribe line. Note2: 0.1µF capacitor between should placed close possible.
8.2. Ordering Information
Product Number Package Type
SPLD112A1-nnnnV-C
Note1: Code number (nnnnV) assigned customer. Note2: Code number (nnnn 0000 9999); version
Chip form
Sunplus Technology Co., Ltd. Proprietary Confidential
OCT. 2001 Preliminary Version:
SPLD112A1
8.3. Locations
Name Name
-3059 -3059 -3059 -3059 -3059 -3059 -3059 -3059 -3059 -3059 -3059 -3059 -3059 -3059 -3059 -3059 -3059 -3059 -3059 -3059 -3059 -3059 -3059 -3059 -2872 -2719 -2566 -2413 -2278 -2143 -2008 -1873 -1738 -1603 -1468 -1333 -1198 -1063 -928 -793 -658 -523 -388 -253
1763 1412 1277 1142 1007 -207 -342 -477 -612 -747 -882 -1017 -1152 -1287 -1422 -1764 -1764 -1764 -1764 -1764 -1764 -1764 -1764 -1764 -1764 -1764 -1764 -1764 -1764 -1764 -1764 -1764 -1764 -1764 -1764 -1764
D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 MODE0 MODE1 DO112 CUP2 CUP1 VSS2
-118 1096 1231 1366 1501 1636 1771 1906 2041 2176 2311 2464 2617 2770 3056 3056 3056 3056 3056 3056 3056 3056 3056 3056 3056 3056 3056 3056 3056 3056 3056 3056 3056 3056 3056 3056
-1764 -1764 -1764 -1764 -1764 -1764 -1764 -1764 -1764 -1764 -1764 -1764 -1764 -1764 -1764 -1764 -1764 -1764 -1764 -1764 -1764 -1764 -1764 -1611 -1458 -1305 -1152 -999 -846 -693 -540 -387 -234 1142 1295 1448
Sunplus Technology Co., Ltd. Proprietary Confidential
OCT. 2001 Preliminary Version:
SPLD112A1
Name Name
3056 3056 2770 2617 2464 2311 2176 2041 1906 1771 1636 1501 1366 1231 1096
1601 1754 1763 1763 1763 1763 1763 1763 1763 1763 1763 1763 1763 1763 1763 1763 1763 1763 1763 1763 1763 1763
-118 -253 -388 -523 -658 -793 -928 -1063 -1198 -1333 -1468 -1603 -1738 -1873 -2008 -2143 -2278 -2413 -2566 -2719 -2872
1763 1763 1763 1763 1763 1763 1763 1763 1763 1763 1763 1763 1763 1763 1763 1763 1763 1763 1763 1763 1763 1763
Sunplus Technology Co., Ltd. Proprietary Confidential
OCT. 2001 Preliminary Version:
SPLD112A1
DISCLAIMER
information appearing this publication believed accurate. Integrated circuits sold Sunplus Technology covered warranty patent indemnification provisions stipulated terms sale only. SUNPLUS makes warranty, express, statutory implied description regarding information this publication FURTHERMORE, SUNPLUS MAKES WARRANTY SUNPLUS reserves right halt production alter specifications regarding freedom described chip(s) from patent infringement. MERCHANTABILITY FITNESS PURPOSE. prices time without notice. publication current before placing orders.
Accordingly, reader cautioned verify that data sheets other information this Products described herein intended normal commercial applications.
Applications involving unusual environmental reliability requirements, e.g. military equipment medical life support equipment, specifically recommended without additional processing SUNPLUS such applications. Please note that application circuits illustrated this document reference purposes only.
Sunplus Technology Co., Ltd. Proprietary Confidential
OCT. 2001 Preliminary Version:
SPLD112A1
REVISION HISTORY
Date Revision Description Page
FEB. 2000 OCT. 2001
Original Revise segment output signal sequence from O[1:64] O[64:1], O[1:80] O[80:1], O[96:1] O[1:96] O[112:1] O[1:112] Correct chip size Note1 Note2 "8.1 Assignment" Renew document format
Sunplus Technology Co., Ltd. Proprietary Confidential
OCT. 2001 Preliminary Version:

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