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16COM/80SEG Controller/Driver OCT. 2001 Version SUNPLUS TECH


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SPLC783A
16COM/80SEG Controller/Driver
OCT. 2001 Version
SUNPLUS TECHNOLOGY infringement patent other rights third parties which result from use. addition, SUNPLUS products authorized critical components life support devices/ systems aviation devices/systems, where malfunction failure product reasonably expected result significant injury user, without express written approval Sunplus.
SPLC783A
Table Contents
PAGE
GENERAL DESCRIPTION. BLOCK DIAGRAM FEATURES. SIGNAL DESCRIPTIONS FUNCTIONAL DESCRIPTIONS. 5.1. OSCILLATOR 5.2. CONTROL DISPLAY INSTRUCTIONS 5.3. INSTRUCTION TABLE. 5.4. 8-BIT OPERATION 8-DIGIT 1-LINE DISPLAY (USING INTERNAL RESET). 5.5. 4-BIT OPERATION 8-DIGIT 1-LINE DISPLAY (USING INTERNAL RESET). 5.6. 8-BIT OPERATION 8-DIGIT 2-LINE DISPLAY (USING INTERNAL RESET). 5.7. RESET FUNCTION 5.8. DISPLAY DATA RAM) 5.9. TIMING GENERATION CIRCUIT. 5.10. DRIVER CIRCUIT 5.11. CHARACTER GENERATOR ROM) 5.12. CHARACTER GENERATOR RAM) 5.13. CURSOR/BLINK CONTROL CIRCUIT 5.14. INTERFACING 5.15. SUPPLY VOLTAGE DRIVE 5.16. REGISTER (INSTRUCTION REGISTER) (DATA REGISTER) 5.17. BUSY FLAG (BF) 5.18. ADDRESS COUNTER (AC). 5.19. PORT CONFIGURATION ELECTRICAL SPECIFICATIONS 6.1. ABSOLUTE MAXIMUM RATINGS 6.2. CHARACTERISTICS (VDD 2.7V 4.5V, 6.3. CHARACTERISTICS (VDD 2.7V 4.5V, 6.4. CHARACTERISTICS (VDD 4.5V 5.5V, 6.5. CHARACTERISTICS (VDD 4.5V 5.5V, APPLICATION CIRCUITS. 7.1. R-OSCILLATOR 7.2. INTERFACE MPU. 7.3. SPLC783A APPLICATION CIRCUIT 7.4. APPLICATIONS CHARACTER GENERATOR 8.1. SPLC783A 8.2. SPLC783A PACKAGE/PAD LOCATIONS 9.1. ASSIGNMENT 9.2. ORDERING INFORMATION 9.3. LOCATIONS DISCLAIMER. REVISION HISTORY
Sunplus Technology Co., Ltd. Proprietary Confidential
OCT. 2001 Version:
SPLC783A
16COM/80SEG CONTROLLER/DRIVER
GENERAL DESCRIPTION
SPLC783A, dot-matrix controller driver from SUNPLUS, unique design displaying alpha-numeric, Japanese-Kana characters symbols. SPLC783A single provides types interfaces MPU: 4-bit 8-bit interfaces. transferring speed 8-bit twice faster than 4-bit. SPLC783A able display 16-character lines. extended. rank.
FEATURES
Character generator ROM: 10880 bits Character font dots: characters Character font dots: characters Character generator RAM: bits Character font dots: characters Character font dots: characters 4-bit 8-bit interfaces Direct driver LCD: COMs SEGs Duty factor (selected program): duty: line dots 1/11 duty: line dots 1/16 duty: lines dots line
cascading with SPLC100 SPLC063, display capability CMOS technology ensures power saves most efficient performance keeps highest
BLOCK DIAGRAM
OSC1 OSC2 Timing Generation Circuit 80-bit Shift Register Latch Circuit Segments Commons Driver CLK1, CLK2
Built-in power automatic reset circuit Built-in oscillator circuit (with external resistor) Support external clock operation Power Consumption Package form: bare chip available
COM1COM16
Parallel Serial Data Conversion Circuit Busy Flag Character Generator Character Generator Cursor Blink Control Circuit
DB0-DB3 DB4-DB7 Power Supply Drive (V1-V5) Buffer Instruction Register Instruction Decorder Data Register
Display Data Bytes 16-bit Shift Register
SEG1SEG80
Address Counter
Sunplus Technology Co., Ltd. Proprietary Confidential
OCT. 2001 Version:
SPLC783A
SIGNAL DESCRIPTIONS
Mnemonic OSC1 OSC2 Type Power input Ground Both OSC1 OSC2 connected resistor internal oscillator circuit. external clock operation, clock input OSC1. Supply voltage driving. start signal reading writing data. signal selecting read write actions. Read, Write. signal selecting registers. Data Register (for read write) Instruction Register (for write), Busy flag Address Counter (for read). CLK1 CLK2 SEG1 SEG33 SEG34 SEG80 COM1 COM16 TEST Common signals LCD. TEST pin. This must fixed open. 4-bit data High 4-bit data Clock latch serial data Clock shift serial data Switch signal convert waveform Sends character pattern data corresponding each common signal serially. Selection, Non-selection. Segment signals LCD. Description
Sunplus Technology Co., Ltd. Proprietary Confidential
OCT. 2001 Version:
SPLC783A
FUNCTIONAL DESCRIPTIONS
5.1. Oscillator
SPLC783A oscillator supports only internal oscillator operation, also external clock operation. I/D=1 I/D=0 shifts display left shifts display right
5.2. Control Display Instructions
Control display instructions described details follows:
5.2.4. Display ON/OFF control
5.2.1. Clear display
Code
Code
Display Display Cursor Cursor Blinks Blinks
clears entire display sets Display Data Address Address Counter.
character font
character font
5.2.2. Return home
Code
line Cursor 11th line
care
sets Display Data Address Address Counter display returns original position. displayed). change. cursor blink goes most-left side display line lines contents Display Data
5.2.5. Cursor display shift
Without changing data, moves cursor shifts display.
Code
5.2.3. Entry mode
During writing reading data, defines cursor moving direction shifts display.
Code
Blink display alternately
Increment, Decrement. display shift, display does shift.
Shift cursor left Shift cursor right Shift display left. Shift display right.
Description
Address Counter
Cursor follows display shift Cursor follows display shift
Sunplus Technology Co., Ltd. Proprietary Confidential
OCT. 2001 Version:
SPLC783A
5.2.6. Function
Code
Display data read written after this setting. one-line display (aaaaaaa)2: (00)16 (4F)16. two-line display (aaaaaaa)2: (00)16 (27)16 first line, (aaaaaaa)2: (40)16 (67)16 second line.
care sets interface data length. Data transferred with 8-bit length (DB7 Data transferred with 4-bit length (DB7 requires times accomplish data transferring. sets number display line. One-line display. Two-line display. sets character font. dots character font. dots character font.
Code
5.2.9. Read busy flag address
Display Lines
Character Font Duty Factor dots dots dots When indicates system busy will accept instruction until busy same time, content Address Counter (aaaaaaa)2 read.
cannot display lines with dots character font.
5.2.10. Write data character generator 5.2.7. character generator address
Code Code
display data
sets Character Generator Address (aaaaaa)2 Address Counter. Character Generator data read written after this setting.
writes data (dddddddd)2 character generator display data RAM.
5.2.11. Read data from character generator display data
Code
5.2.8. display data address
Code
reads data (dddddddd)2 from character generator display data RAM. sets Display Data Address (aaaaaaa)2 Address Counter. read data correctly, following: address Character Generator Display Data shift cursor instruction. Read instruction.
Sunplus Technology Co., Ltd. Proprietary Confidential
OCT. 2001 Version:
SPLC783A
5.3. Instruction Table
Instruction Clear Display Return Home Instruction Code Description Write "20H" DDRAM DDRAM address "00H" from DDRAM address "00H" from return cursor original position shifted. contents DDRAM changed. Entry Mode Display Control Cursor Display Shift Function Assign cursor moving direction enable shift entire display display(D), cursor(C), blinking cursor(B) on/off control bit. cursor moving display shift control bit, direction, without changing DDRAM data. interface data length (DL: 8-bit/4-bit), numbers display line 2-line/1-line) and, display font type (F:5x10 dots/5x8 dots) CGRAM Address DDRAM Address Read Busy Flag Address Counter Write Data Read Data from
Note: "-": don't care
Execution time (fosc=270KHz) 1.52ms 1.52ms
38µs 38µs 38µs
38µs
CGRAM address address counter.
38µs 38µs
DDRAM address counter
Whether during internal operation known reading read. contents address counter also
Write data into internal (DDRAM/CGRAM). Read data from internal (DDRAM/CGRAM).
38µs 38µs
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OCT. 2001 Version:
SPLC783A
5.4. 8-Bit Operation 8-Digit 1-Line Display (Using Internal Reset)
Instruction Power (SPLC783A starts initializing) Function
Display Power reset. display.
Operation
8-bit operation select 1-line display line character font.
Display control
Display Cursor appear. Increase address one.
Entry mode
will shift cursor right when writing RAM/CG RAM. display shift.
Write data
Write cursor incremented shifted right. Write cursor incremented shifted right.
Write data
Write data
WELCOME_
Write cursor incremented shifted right. mode display shift when writing
Entry mode
WELCOME_
Write data
ELCOME
Write
"(space).
cursor incremented shifted right. Write cursor incremented shifted right.
Write data
LCOME
Write data
COMPAMY_
Write cursor incremented shifted right.
Cursor display shift
COMPAMY_
Only shift cursor's position left (Y).
Cursor display shift
COMPAMY_
Only shift cursor's position left (M).
Write data
OMPANY_
Write display moves left.
Cursor display shift
COMPAMY_
Shift display cursor's position right.
Cursor display shift
OMPANY_
Shift display cursor's position right.
Write data
COMPAMY_
Write
(space).
cursor incremented shifted right.
Return home
WELCOME_
Both display cursor return original position (address
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OCT. 2001 Version:
SPLC783A
5.5. 4-Bit Operation 8-Digit 1-Line Display (Using Internal Reset)
Power (SPLC783A starts initializing) Instruction Display Operation
Power reset. display.
Function
4-bit operation.
4-bit operation select 1-line display line character font.
Display Cursor appears.
Increase address one.
will shift cursor right when writing RAM. display shift.
Write cursor incremented shifted right.
5.6. 8-Bit Operation 8-Digit 2-Line Display (Using Internal Reset)
Power (SPLC783A starts initializing) Function
Instruction
Display Power reset. display.
Operation
8-bit operation select 2-line display line character font.
Display Cursor appear. Increase address one.
Display control
Entry mode
will shift cursor right when writing RAM. display shift.
Write data
Write cursor incremented shifted right. Write cursor incremented shifted right.
Write data
WELCOME_
address
WELCOME
sets RAM's address. cursor moved beginning position line. Write cursor incremented shifted right.
Write data
WELCOME
Write data
WELCOME PART_
Write cursor incremented shifted right.
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OCT. 2001 Version:
SPLC783A
Entry mode
Instruction
Display
WELCOME PART_
Operation When writing, sets mode display shift.
Write data
ELCOME PARTY_
Write cursor incremented shifted right. Both display cursor return original position (address
Return home
WELCOME PARTY
5.7. RESET Function
power SPLC783A starts internal auto-reset circuit executes initial instructions. follows: initial procedures shown
8-Bit Interface
Power
time after 4.5V
time 40ms After 2.7V
cannot checked before this instruction Function Interface bits length
time
cannot checked before this instruction Function Interface bits length
time
cannot checked before this instruction Function Interface bits length
checked after following instructions Function Interface bits length Specify number display lines character font number display lines character font cannot changed afterwards Display Display clear
Initialization Ends
Entry mode
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SPLC783A
4-Bit Interface
Power
time after 4.5V
time 40ms After 2.7V
cannot checked before this instruction Function Interface bits length
time
cannot checked before this instruction Function Interface bits length
time
cannot checked before this instruction Function Interface bits length
checked after following instructions Function interface bits length) Interface bits length
Function Interface bits length Specify number display lines character font
number display lines character font cannot changed afterwards Display Display clear
Initialization Ends
Entry mode
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OCT. 2001 Version:
SPLC783A
5.8. Display Data RAM)
80-bit normally used storing display data. Those used display data used general data RAM. address configured Address Counter. relationships between Display Data Address LCDs position depicted follows.
1-line display display characters
Display position Display data address
Example 1-line display display characters
Display position Display data address
When display shift operation performed display data RAM's address moves Left shift Right shift
5.9. Timing Generation Circuit
timing generating circuit able generate timing signals internal circuits. order prevent internal timing interface, access timing access timing generated independently.
5.11. Character Generator ROM)
Using 8-bit character code, character generator generates dots dots character patterns. dots character patterns. also generate 192's dots character patterns 64's
5.10. Driver Circuit
Total commons segments signal drivers valid driver circuit. When program specifies character fonts line numbers, corresponding common signals output drive-waveforms others still output unselected waveforms.
5.12. Character Generator RAM)
Users easily change character patterns character generator through program. written dots, 8-character patterns dots 4-character patterns.
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OCT. 2001 Version:
SPLC783A
following diagram shows SPLC783A character patterns: Correspondence between Character Codes Character Patterns.
Higher 4-bit Character Code (Hexadecimal)
Lower 4-bit Character Code (Hexadecimal)
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OCT. 2001 Version:
SPLC783A
relationships between Character Generator Addresses, Character Generator Data (character patterns), Character Codes depicted follows: character patterns
Character Code Data
Address
Character Patterns Data Character Pattern Example Cursor Position Character Pattern Example
Note1:
means that bit0~2 character code correspond bit3~5 address.
Note2:
These areas used display, used general data RAM.
Note3: When bit4-7 character code character patterns selected. Note4: Selected selected care Note5: example (1), character code b7-b4 display display character. Note6: bits character code character pattern line position. with cursor. line cursor position display formed logical That means character code (00) 16,and (08)
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OCT. 2001 Version:
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character patterns
Character Code Data
Address
Character Patterns Data Cursor Position Character Pattern Example
Note1:
means that bit1~2 character code correspond bit4~5 address.
Note2:
These areas used display, used general data RAM.
Note3: When bit4-7 character code character patterns selected. Note4: Selected, selected, care Note5: example (1), character code b7-b4 display (08) 16,and (09) display character. Note6: bits character code character pattern line position. with cursor. 11th line cursor position display formed logical That means character codes (00) (01)
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5.13. Cursor/Blink Control Circuit
This circuit generates cursor blink cursor blink control circuit. cursor blink appears digit Display Data Address defined Address Counter. When Address Counter (07) cursor position shown belows:
1-line display digit Display position Display data address Hexadecimal cursor position 2-line display digit line line Display position Display data address Hexadecimal
cursor position
5.14. Interfacing
There types data operations: 4-bit 8-bit operations. Using 4-bit MPU, interfacing 4-bit data transferred 4-busline (DB4 DB7). used. transferring. Thus, lines Using 4-bit interface 8-bit data requires times First, higher 4-bit data transferred Secondly, lower
5.15. Supply Voltage Drive
Different voltages supplied SPLC783A's pins obtaining drive-waveform. relationships between bias, duty factor supply voltages shown belows:
Duty Factor Supply Voltage
1/8, 1/11 VLCD VLCD VLCD VLCD VLCD
1/16 VLCD VLCD VLCD VLCD VLCD
4-busline (for 8-bit operation, DB4). DB0).
4-bit data transferred 4-busline (for 8-bit operation, 8-bit MPU, 8-bit data transferred 8-buslines (DB0 DB7).
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5.15.1. power connections (1/4 Bias, Bias) shown belows:
+5.0V +5.0V
Bias (1/8,1/11 Duty) Bias
(1/16 Duty)
bypass-capacitor improves display quality.
+5.0V
+5.0V
Bias (1/8,1/11 Duty) Bias
(1/16 Duty)
bias voltage must have following relations:
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5.15.2. relationship between frames frequency oscillators frequency.
(Assume oscillation frequency 250KHz, clock cycle time 4.0µs)
5.15.2.1. duty, TYPE-B waveform
clocks COM1 V2(V3) Frame Frame
frame 4(µs) 12800(µs) 12.8ms Frame frequency 78.1(Hz) 12.8(ms)
5.15.2.2. 1/11 duty, TYPE-B waveform
clocks COM1 V2(V3) Frame frame 4(µs) 17600(µs) 17.6ms Frame frequency 17.6(ms) .8(Hz) Frame
5.15.2.3. 1/16 duty, TYPE-B waveform
clocks COM1 Frame frame 4(µs) 12800(µs) 12.8ms Frame frequency 78.1(Hz) 12.8(ms) Frame
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5.16. REGISTER (Instruction Register) (Data Register)
SPLC783A contains 8-bit registers: Instruction Register (IR) Data Register (DR). Using combinations selects below:
5.19. Port Configuration 5.19.1. Input port:
PMOS
Operation
write (Display clear, etc.) Read busy flag (DB7) Address Counter (DB0 DB6) write Display data Character generator RAM) read (Display data Character generator
NMOS
5.19.2. Input port:
PMOS PMOS
written MPU, cannot read MPU.
NMOS
5.17. Busy Flag (BF)
When busy flag output DB7. busy flag SPLC783A busy state does accept instruction until busy flag
5.19.3. Output port: CLK1, CLK2,
5.18. Address Counter (AC)
Address Counter assigns addresses Display Data Character Generator RAM. When instruction address
NMOS PMOS
written address information sent from After writing to/reading from Display Data Character Generator RAM, automatically incremented decremented one). contents output when
5.19.4. Input Output port:
Enable
PMOS
PMOS
NMOS
Data
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OCT. 2001 Version:
SPLC783A
ELECTRICAL SPECIFICATIONS
6.1. Absolute Maximum Ratings
Characteristics Symbol Ratings
Operating Voltage Driver Supply Voltage Input Voltage Range Operating Temperature Storage Temperature
conditions AC/DC Electrical Characteristics.
VLCD TSTO
-0.3V +7.0V 0.3V -0.3V 0.3V +125
normal operational
Note: Stresses beyond those given Absolute Maximum Rating table cause operational errors damage device.
6.2. Characteristics (VDD 2.7V 4.5V,
Characteristics Symbol Limit Min. Typ. Max. Unit Test Condition
Operating Current Input High Voltage Input Voltage Input High Voltage Input Voltage Input High Current Input Current Output High Voltage (TTL) Output Voltage (TTL) Output High Voltage (CMOS) Output Voltage (CMOS) Driver Resistance (COM) Driver Resistance (SEG) Voltage
VIH1 VIL1 VIH2 VIL2 VOH1 VOL1 VOH2 VOL2 RCOM RSEG VLCD
0.7VDD -0.3 0.7VDD -0.2 -1.0 -5.0 0.8VDD
0.2VDD 0.2VDD 0.2VDD
External clock (Note) Pins:(E, R/W, DB7)
OSC1 Pins: (RS, R/W, DB7) 3.0V 0.1mA Pins: 0.1mA Pins: 40µA, Pins: CLK1, CLK2, 40µA, Pins: CLK1, CLK2, ±50µA, VLCD 4.0V Pins: COM1 COM16 ±50µA, VLCD 4.0V Pins: SEG1 SEG80 VDD-V5, bias bias
Note: FOSC 270KHz, 3.0V, "L", R/W, open, outputs loads.
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6.3. Characteristics (VDD 2.7V 4.5V, 6.3.1. Internal clock operation
Characteristics Symbol Limit Min. Typ. Max. Unit Test Condition
Frequency
FOSC1
3.0V, 75K±2%
6.3.2. External clock operation
Characteristics Symbol Limit Min. Typ. Max. Unit Test Condition
External Frequency Duty Cycle Rise/Fall Time
FOSC2
6.3.3. Write mode (Writing data from SPLC783A)
Characteristics Symbol Limit Min. Typ. Max. Unit Test Condition
Cycle Time Pulse Width Rise/Fall Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time
tSP1 tHD1 tSP2 tHD2
1400
Pins: R/W, Pins: R/W, Pins: Pins:
6.3.4. Read mode (Reading data from SPLC783A MPU)
Characteristics Symbol Limit Min. Typ. Max. Unit Test Condition
Cycle Time Pulse Width Rise/Fall Time Address Setup Time Address Hold Time Data Output Delay Time Data hold time
tSP1 tHD1 tHD2
1400
Pins: R/W, Pins: R/W, Pins:
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6.4. Characteristics (VDD 4.5V 5.5V,
Characteristics Symbol Limit Min. Typ. Max. Unit Test Condition
Operating Current Input High Voltage Input Voltage Input High Voltage Input Voltage Input High Current Input Current Output High Voltage (TTL) Output Voltage (TTL) Output High Voltage (CMOS) Output Voltage (CMOS) Driver Resistance (COM) Driver Resistance (SEG) Voltage
VIH1 VIL1 VIH2 VIL2 VOH1 VOL1 VOH2 VOL2 RCOM RSEG VLCD
-0.3 VDD-1 -0.2 -1.0 0.9VDD
-100 0.1VDD
External clock (Note) Pins:(E, R/W, DB7)
OSC1 OSC1 Pins: (RS, R/W, DB7) 5.0V
-0.205mA Pins: 1.2mA Pins: -40µA, Pins: CLK1, CLK2, 40µA, Pins: CLK1, CLK2, ±50µA, VLCD 4.0V Pins: COM1 COM16 ±50µA, VLCD 4.0V Pins: SEG1 SEG80 VDD-V5, bias bias
Note: FOSC 270KHz, 5.0V, "L", R/W, open, outputs loads.
6.5. Characteristics (VDD 4.5V 5.5V, 6.5.1. Internal clock operation
Characteristics Symbol Limit Min. Typ. Max. Unit Test Condition
Frequency
FOSC1
5.0V, 91K±2%
6.5.2. External clock operation
Characteristics Symbol Limit Min. Typ. Max. Unit Test Condition
External Frequency Duty Cycle Rise/Fall Time
FOSC2
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6.5.3. Write mode (Writing Data from SPLC783A)
Characteristics Symbol Limit Min. Typ. Max. Unit Test Condition
Cycle Time Pulse Width Rise/Fall Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time
tSP1 tHD1 tSP2 tHD2
Pins: R/W, Pins: R/W, Pins: Pins:
6.5.4. Read mode (Reading Data from SPLC783A MPU)
Characteristics Symbol Limit Min. Typ. Max. Unit Test Condition
Cycle Time Pulse Width Rise/Fall Time Address Setup Time Address Hold Time Data Output Delay Time Data hold time
tSP1 tHD1 tHD2
Pins: R/W, Pins: R/W, Pins:
6.5.5. Interface mode with Driver (SPLC100A1)
Characteristics Symbol Limit Min. Typ. Max. Unit Test Condition
Clock pulse width high Clock pulse width Clock setup time Data setup time Data hold time delay time
tPWH tPWL tCSP tDSP
-1000
1000
Pins: CLK1, CLK2 Pins: CLK1, CLK2 Pins: CLK1, CLK2 Pins: Pins: Pins:
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6.5.6. Write mode timing diagram (Writing Data from SPLC783A)
tSP1
tHD1
tHD1
tHD2
tSP2
Valid Data
6.5.7. Read mode timing diagram (Reading Data from SPLC783A MPU)
tSP1
tHD1
tHD1
tHD2
Valid Data
6.5.8. Interface mode with SPLC100A1 timing diagram
0.9VDD
tPWH tCSP
0.9VDD
tPWH
0.9VDD 0.1VDD 0.1VDD
tCSP
0.9VDD 0.1VDD
tPWL
0.9VDD 0.1VDD
tDSP
0.1VDD
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APPLICATION CIRCUITS
7.1. R-Oscillator
oscillation resistor used only internal oscillaotr operation mode.
OSC1 when 3.0V) when 5.0V) Since oscillation frequency varies depending OSC1 OSC2 capacitance, wiring length these pins should minimized.
OSC2
Fosc
Fosc
Rosc Kohms
Rosc Kohms
3.0V
5.0V
7.2. Interface 7.2.1. Interface 8-bit (6805)
6805
COM1 COM16
PANEL COMMONS
SPLC783A
SEG1 SEG80
SEGMENTS
7.2.2. Interface 8-bit (Z80)
PANEL
SPLC783A
ENTS
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7.3. SPLC783A Application Circuit
MATRIX PANEL
COM16 (COM8) COM1
SEG80 SEG1
Y1-Y40 SHL1 SHL2
SPLC100A1
CLK1 CLK2 SHL1 SHL2
Y1-Y40
SPLC100A1
CLK1 CLK2 SHL1 SHL2
Y1-Y40
SPLC100A1
CLK1 CLK2
CLK1 CLK2
SPLC783A +5.0V
7.4. Applications
SPLC783A COM1 Panel COM8 SEG1 characters line
SEG80 Example dots characters line Bias Duty
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SPLC783A COM1 Panel characters line COM11 SEG1
SEG80 Example dots characters line Bias Duty
SPLC783A COM1 Panel COM8 COM9 characters lines
COM16 SEG1
SEG80 Example dots characters lines Bias Duty
SPLC783A COM1
COM8 SEG1 SEG80 COM9
COM16 Example dots characters line Bias Duty
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SPLC783A
SEG1 SEG40 COM1 Panel COM8 characters lines
SEG41 SEG80 Example dots characters lines Bias Duty
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CHARACTER GENERATOR
8.1. SPLC783A
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8.2. SPLC783A
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PACKAGE/PAD LOCATIONS
9.1. Assignment
Chip Size: 3210µm 4520µm Size: 90µm 90µm This substrate should connected
Note1: Chip size included scribe line. Note2: 0.1µF capacitor between should placed close possible.
9.2. Ordering Information
Product Number Package Type
SPLC783A-nnnnV-C
Note1: Code number (nnnnV) assigned customer. Note2: Code number (nnnn 0000 9999); version
Chip form
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9.3. Locations
Name Name
SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 OSC2 OSC1 CLK1 CLK2
-1444 -1444 -1444 -1444 -1444 -1444 -1444 -1444 -1444 -1444 -1444 -1444 -1444 -1444 -1444 -1444 -1444 -1444 -1444 -1444 -1444 -1444 -1444 -1444 -1444 -1444 -1444 -1444 -1444 -1444 -1444 -1444 -1444 -1444 -1444 -1444 -1231 -1106 -980 -855 -740 -625 -510
1878 1744 1624 1504 1389 1275 1160 1050 -160 -270 -380 -490 -601 -710 -820 -931 -1040 -1150 -1261 -1370 -1485 -1600 -1716 -1836 -1956 -2076 -2076 -2076 -2076 -2076 -2076 -2076 -2076
TEST COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 SEG80 SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72 SEG71 SEG70 SEG69
-396 -283 -172 1089 1215 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444
-2076 -2076 -2076 -2076 -2076 -2076 -2076 -2076 -2076 -2076 -2076 -2076 -2076 -2076 -2076 -2076 -1956 -1836 -1716 -1600 -1485 -1370 -1261 -1150 -1040 -931 -820 -710 -601 -490 -380 -270 -160
Sunplus Technology Co., Ltd. Proprietary Confidential
OCT. 2001 Version:
SPLC783A
Name Name
SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51
1444 1444 1444 1444 1444 1444 1444 1444 1444 1442 1317 1192 1068
1050 1160 1269 1384 1500 1615 1735 1855 1975 2100 2100 2100 2100 2100 2100 2100 2100 2100
SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34
-165 -274 -385 -495 -608 -722 -837 -952 -1069 -1194 -1318 -1444
2100 2100 2100 2100 2100 2100 2100 2100 2100 2100 2100 2100 2100 2100 2100 2100 2100
Sunplus Technology Co., Ltd. Proprietary Confidential
OCT. 2001 Version:
SPLC783A
DISCLAIMER
information appearing this publication believed accurate. Integrated circuits sold Sunplus Technology covered warranty patent indemnification provisions stipulated terms sale only. SUNPLUS makes warranty, express, statutory implied description regarding information this publication FURTHER, SUNPLUS MAKES WARRANTY SUNPLUS reserves right halt production alter specifications regarding freedom described chip(s) from patent infringement. MERCHANTABILITY FITNESS PURPOSE. prices time without notice. publication current before placing orders.
Accordingly, reader cautioned verify that data sheets other information this Products described herein intended normal commercial applications.
Applications involving unusual environmental reliability requirements, e.g. military equipment medical life support equipment, specifically recommended without additional processing SUNPLUS such applications. Please note that application circuits illustrated this document reference purposes only.
Sunplus Technology Co., Ltd. Proprietary Confidential
OCT. 2001 Version:
SPLC783A
REVISION HISTORY
Date Revision Description Page
OCT. 2001
Original
Sunplus Technology Co., Ltd. Proprietary Confidential
OCT. 2001 Version:

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