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16COM/80SEG Controller/Driver NOV. 2001 Version SPLC782A


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SPLC782A
16COM/80SEG Controller/Driver
NOV. 2001 Version
SPLC782A
Table Contents
PAGE
GENERAL DESCRIPTION. FEATURES. BLOCK DIAGRAM SIGNAL DESCRIPTIONS FUNCTIONAL DESCRIPTIONS. 5.1. OSCILLATOR 5.2. CONTROL DISPLAY INSTRUCTIONS 5.3. INSTRUCTION TABLE. 5.4. 8-BIT OPERATION 16-DIGIT 1-LINE DISPLAY (USING INTERNAL RESET). 5.5. 4-BIT OPERATION 16-DIGIT 1-LINE DISPLAY (USING INTERNAL RESET). 5.6. 8-BIT OPERATION 16-DIGIT 2-LINE DISPLAY (USING INTERNAL RESET). 5.7. RESET FUNCTION 5.8. DISPLAY DATA RAM) 5.9. TIMING GENERATION CIRCUIT. 5.10. DRIVER CIRCUIT 5.11. CHARACTER GENERATOR ROM) 5.12. CHARACTER GENERATOR RAM) 5.13. CURSOR/BLINK CONTROL CIRCUIT 5.14. INTERFACING MPU. 5.15. SUPPLY VOLTAGE DRIVE 5.16. REGISTER (INSTRUCTION REGISTER) (DATA REGISTER) 5.17. BUSY FLAG (BF) 5.18. ADDRESS COUNTER (AC). 5.19. SEGMENT DATA DIRECTION 5.20. COMMON DATA DIRECTION 5.21. PORT CONFIGURATION ELECTRICAL SPECIFICATIONS 6.1. ABSOLUTE MAXIMUM RATINGS 6.2. CHARACTERISTICS (VDD 2.4V 4.5V, 6.3. CHARACTERISTICS (VDD 4.5V 5.5V, 6.4. CHARACTERISTICS (VDD 4.5V 5.5V, 6.5. CHARACTERISTICS (VDD 2.4V 4.5V, 6.6. WRITE MODE TIMING DIAGRAM (WRITING DATA FROM SPLC782A) 6.7. READ MODE TIMING DIAGRAM (READING DATA FROM SPLC782A MPU). APPLICATION CIRCUITS. 7.1. INTERFACE MPU. 7.2. APPLICATIONS CHARACTER GENERATOR 8.1. SPLC782A
Sunplus Technology Co., Ltd. Proprietary Confidential
NOV. 2001 Version:
SPLC782A
PACKAGE/PAD LOCATIONS 9.1. ASSIGNMENT 9.2. SPLC782A DIMENSIONS 9.3. ORDERING INFORMATION 9.4. LOCATIONS DISCLAIMER. REVISION HISTORY
Sunplus Technology Co., Ltd. Proprietary Confidential
NOV. 2001 Version:
SPLC782A
16COM/80SEG CONTROLLER/DRIVER
GENERAL DESCRIPTION
SPLC782A, dot-matrix controller driver, low-power CMOS integrated circuit. designing low-cost products. SPLC782A capable connecting with application easily used Provide connecting 4-bit 8-bit Direct driver LCD: COMs SEGs 80-channel Bi-Direction segment driver 16-channel Bi-direction common driver Duty factor (selected program): duty: line dots
FEATURES
Character generator ROM: 10880 bits Character font dots: characters Character font dots: characters type CGROM mode, Max. characters used. Character generator RAM: bits Character font dots: characters Character font dots: characters
1/11 duty: line dots 1/16 duty: lines dots line type-A, type-B waveform selected. Built-in power automatic reset circuit Built-in oscillator circuit (with internal resistor) Built-in Bias resistor Support external clock operation Package form: bump chip
BLOCK DIAGRAM
OSC1 MOD0 MOD1 DB0-DB3 DB4-DB7 Buffer Instruction Register Instruction Decorder Timing Generation Circuit 80-bit Bi-Direction Shift Register Latch Circuit Segments Commons Driver TYPE DIRC COM1COM16
Parallel Serial Data Conversion Circuit Busy Flag Character Generator Character Generator Cursor Blink Control Circuit
Data Register
Display Data Bytes 16-bit Shift Register
SEG1SEG80
Address Counter
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NOV. 2001 Version:
SPLC782A
SIGNAL DESCRIPTIONS
Mnemonic Type Logic Power input Ground Voltage; VLCD Bias Voltage Control. Open Bias, Short Bias start signal read data write data. signal select read write. Read, Write. signal select register. Data register (for read write) Instruction register (for write), Busy flag address counter (for read). SEG80 SEG1 COM16 COM9 COM8 COM1 TYPE Low-order data bits High-order data bits Segment signals LCD. Common signals LCD. Common signals LCD. Alternate Signals. TYPE Type-A TYPE Type-B DIRC Common Scan Direction DIRC COM1 COM2 DIRC COM16 COM15 Segment Shift Direction SEG1 SEG2 SEG80 SEG79 MOD1 MOD0 CGROM CGRAM Mode Select
MOD1 MOD0 Function CGRAM CGRAM, CGROM CGRAM, CGROM CGROM
Description
COM15 COM16 COM2 COM1
SEG79 SEG80 SEG2 SEG1
OSC1
internal clock operation, leave this open. external clock operation, clock input OSC1. Test Mode Clock Output; Open normally use. Test Mode Data Output; Open normally use.
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SPLC782A
FUNCTIONAL DESCRIPTIONS
5.1. Oscillator
built-in oscillator generates suitable clock SPLC782A operation. I/D=1 I/D=0 shifts display left shifts display right
5.2. Control Display Instructions
Control display instructions shown follows:
5.2.4. Display ON/OFF control
5.2.1. Clear display
Code
Code
Display Display Cursor Cursor Blinks Blinks
clears whole display sets display data RAMs address address counter.
5.2.2. Return home
Code
character font
character font
line
Curso 11th line
care
5.2.5. Cursor display shift
sets display data RAMs address address counter display returns original position. cursor blink goes left edge display line lines displayed). content Display Data does change.
Code
Without changing RAMs data, move cursor shift display.
5.2.3. Entry mode
During writing reading data, sets cursor move direction shifts display.
Code
Blink display alternately
Increment, Decrement. display shift, display does shift.
Shift cursor left Shift cursor right Shift display left. Shift display right.
Description
Address Counter
Cursor follows display shift Cursor follows display shift
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SPLC782A
5.2.6. Function
Display data read write after this setting.
Code
one-line display (aaaaaaa)2: (00)16 (4F)16.
care sets interface data length. Datas transferred with 8-bit lengths (DB0 DB7). Datas transferred with 4-bit lengths (DB4 DB7). requires times transfer data) sets number display line. One-line display. Two-line display. sets character font. dots character font. dots character font.
two-line display (aaaaaaa)2: (00)16 (27)16 first line, (aaaaaaa)2: (40)16 (67)16 second line.
5.2.9. Read busy flag address
Code
When indicates that system busy now; will accept instruction until busy same time, address counter contents (aaaaaaa)2 read out.
Display Lines Character Font dots dots dots
Duty Factor
5.2.10. Write data character generator display data
cannot display lines with character font.
Code
5.2.7. character generator address
Code
writes data (dddddddd)2 character generator display data RAM.
5.2.11. Read data from character generator
sets character generator address (aaaaaa)2 address counter. Character generator data read write after
Code
display data
this setting.
5.2.8. display data address
reads data (dddddddd)2 from character generator
Code
display data RAM. correct data readout shown belows: address character generator display
sets display data address (aaaaaaa)2 address counter.
data shift cursor instruction. Send Read instruction.
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SPLC782A
5.3. Instruction Table
Instruction Clear Display Instruction Code Description Write "20H" DDRAM DDRAM address "00H" from Return Home DDRAM address "00H" from return cursor original position shifted. changed. Entry Mode Display Control Cursor Display Shift Assign cursor moving direction enable shift entire display display(D), cursor(C), blinking cursor(B) on/off control bit. cursor moving display shift control bit, direction, without data. Function interface data length (DL: 8-bit/4-bit), numbers display line 2-line/1-line) and, display font type (F:5x10 dots/5x8 dots) CGRAM Address DDRAM Address Read Busy Flag Address Counter Write Data Read Data from
Note: "-": don't care
Execution time (fosc 270KHz) 1.52ms
1.52ms
contents DDRAM 38µs
38µs
38µs
changing
DDRAM 38µs
CGRAM address address counter. DDRAM address address counter Whether during internal operation known reading contents address counter also read.
38µs 38µs
Write data into internal (DDRAM/CGRAM). Read data from internal (DDRAM/CGRAM).
38µs 38µs
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SPLC782A
5.4. 8-Bit Operation 16-Digit 1-Line Display (Using Internal Reset)
Instruction Display Power reset. display.
8-bit operation select 1-line display line character font.
Operation
Power (SPLC782A starts initializing) Function
Display control
Display Cursor appear. Increase address one.
Entry mode
will shift cursor right when writing RAM/CG RAM. display shift. Write cursor incremented shifted right. Write cursor incremented shifted right.
Write data
Write data
Write data
WELCOME
Write cursor incremented shifted right.
mode display shift when writing
Entry mode
WELCOME
Write data
ELCOME
Write
"(space).
cursor incremented shifted right. Write cursor incremented shifted right.
Write data
LCOME
COMPAMY
Write data
Write cursor incremented shifted right. Only shift cursor's position left (Y).
Cursor display shift
COMPAMY
Cursor display shift
COMPAMY
Only shift cursor's position left (M).
Write data
COMPAMY
Write display moves left. Shift display cursor's position right.
Cursor display shift
COMPAMY
Cursor display shift
COMPAMY
Shift display cursor's position right.
Write data
OMPANY
Write
(space).
cursor incremented shifted right.
Return home
WELCOME
Both display cursor return original position (address
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5.5. 4-Bit Operation 16-Digit 1-Line Display (Using Internal Reset)
Power initializing) Function
Instruction (SPLC782A starts
Display Power reset. display. 4-bit operation.
Operation
Function
4-bit operation select 1-line display line character font.
Display control
Display
Cursor appears.
Entry mode
Increase address one.
will shift cursor right when writing RAM/CG RAM. display shift.
Write data
Write
cursor incremented shifted right.
5.6. 8-Bit Operation 16-Digit 2-Line Display (Using Internal Reset)
Instruction Power (SPLC782A starts initializing) Function
Display Power reset. display.
Operation
8-bit operation select 2-line display line character font.
Display control
Display Cursor appear.
Entry mode
Increase address one. will shift cursor right when writing RAM/CG RAM. display shift. Write cursor incremented shifted right.
Write data
Write data
WELCOME_
Write cursor incremented shifted right.
address
WELCOME
sets RAM's address. cursor moved beginning position line. Write cursor incremented shifted right. Write cursor incremented shifted right. Write cursor incremented shifted right. NOV. 2001 Version:
Write data
WELCOME
WELCOME PART_ WELCOME PART_
Write data
Write data
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SPLC782A
Instruction Entry mode
Display
WELCOME PART_ ELCOME PARTY_
Operation When writing, sets mode display shift.
Write data
Write cursor incremented shifted right.
Return home
WELCOME PARTY
Both display cursor return original position (address
5.7. Reset Function
power starts internal auto-reset circuit executes initial instructions. There initial procedures shown belows:
8-Bit Interface Power Wait time after 4.5V
Wait time 40ms After 2.7V cannot checked before this instruction Function Interface bits length
Wait time
cannot checked before this instruction Function Interface bits length
Wait time
cannot checked before this instruction Function Interface bits length checked after following instructions Function Interface bits length Specify number display lines character font number display lines character font cannot changed afterwards Display Display clear Entry mode
Initialization Ends
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4-Bit Interface Power Wait time after 4.5V Wait time Wait time cannot checked before this instruction Function Interface bits length checked after following instructions Function interface bits length) Interface bits length Function Interface bits length Specify number display lines character font number display lines character font cannot changed afterwards Display Display clear Initialization Ends Entry mode cannot checked before this instruction Function Interface bits length Wait time 40ms After 2.7V cannot checked before this instruction Function Interface bits length
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5.8. Display Data RAM)
stores display data size bytes. area that used display used general data RAM. address address counter. There relations between display data RAMs address LCDs position shown belows.
1-line display display characters
Display position
Display data address
Example 1-line display display characters
Display position
Display data address
When display shift operation performed display data RAM's address moves Left shift
Right shift
5.9. Timing Generation Circuit
timing generation circuit generate needed timing signals internal circuits. generated. prevent internal timing interface, access timing access timing separately
5.11. Character Generator ROM)
Using 8-bit character code, character generator generates character patterns. character patterns. also generate character patterns
5.10. Driver Circuit
There commons segments signal drivers driver circuit. When program specifies character fonts line numbers, corresponding common signals will output drive waveforms others still output unselected waveforms.
5.12. Character Generator RAM)
Using programs, users easily change character patterns character generator RAM. character patterns. written with dots, character patterns written with dots,
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Here SPLC782As character patterns shown belows: Correspondence between Character Codes Character Patterns.
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relations between character generator addresses, character generator data (character patterns) character codes shown belows:
5.12.1. character patterns
Character Code Data
Address
Character Patterns Data Character Pattern Example Cursor Position Character Pattern Example
Note1:
means that bit0~2 character code correspond bit3~5 address.
Note2:
These areas used display, used general data RAM.
Note3: When bit4-7 character code character patterns selected. Note4: Selected, selected care Note5: example (1), character code b7-b4 display display character. Note6: bits character code character pattern line position. with cursor. line cursor position display formed logical That means character code (00) 16,and (08)
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5.12.2. character patterns
Character Code Data
Address
Character Patterns Data Cursor Position Character Pattern Example
Note1:
means that bit1~2 character code correspond bit4~5 address.
Note2:
These areas used display, used general data RAM.
Note3: When bit4-7 character code character patterns selected. Note4: Selected, selected, care Note5: example (1), character code b7-b4 display (08) 16,and (09) display character. Note6: bits character code character pattern line position. with cursor. 11th line cursor position display formed logical That means character codes (00) (01)
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5.13. Cursor/Blink Control Circuit
generate cursor blink cursor blink control circuit. cursor blink appears digit display data address address counter. When address counter (07) follows:
cursor's position shown
1-line display digit 2-line display digit line line Display position Display data address Hexadecimal
cursor position Display position Display data address Hexadecimal
cursor position
5.14. Interfacing
There types data operations: 4-bit operation 8-bit operation. Using 4-bit MPU, interfacing 4-bit data Using 4-bit transferred lines (for 8-bit operation, DB4). lines used. interface 8-bit data needs times.
5.15. Supply Voltage Drive
bias selected open/short pins. Duty Factor Supply Voltage 1/8, 1/11 Short 1/16 Open
First, higher 4-bit data
transferred 4-busline (for 8-bit operation, DB4). Secondly, lower 4-bit data transferred lines (for 8-bit operation, DB0). Using 8-bit MPU, interfacing 8-bit data transferred lines (DB0 DB7).
SPLC782A
SPLC782A
short
open
Bias (1/8, 1/11 Duty)
Bias (1/16 Duty)
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5.15.1. relations between frames frequency oscillators frequency
(Assume oscillation frequency 250KHz, clock cycle time 4.0µs)
5.15.2. Duty, type-A waveform
clocks
COM1 V2(V3) frame frame (µs) 12800 (µs) 12.8 Frame frequency 78.1 (Hz) 12.8 (ms)
5.15.3. 1/11 Duty, type-A waveform
clocks
COM1 V2(V3) frame (µs) 17600 (µs) 17.6 56.8 (Hz) Frame frequency 17.6 (ms) frame
5.15.4. 1/16 Duty, type-A waveform
clocks
COM1 frame frame (µs) 12800 (µs) 12.8 78.1 (Hz) Frame frequency 12.8 (ms)
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5.15.5. Duty, type-B waveform
clocks COM1 V2(V3) Frame Frame
frame 4(µs) 12800(µs) 12.8ms Framefrequ ency 78.1(Hz) 12.8(ms)
5.15.6. 1/11 Duty, type-B waveform
clocks COM1 V2(V3) Frame frame 4(µs) 17600(µs) 17.6ms Framefrequency 17.6(ms) 56.8(Hz) Frame
5.15.7. 1/16 Duty, type-B waveform
clocks COM1 Frame frame 4(µs) 12800(µs) 12.8ms Framefrequ ency 78.1(Hz) 12.8(ms) Frame
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5.16. Register (Instruction Register) (Data Register)
SPLC782A 8-bit registers (instruction register) (data register). followings, combinations select
5.20. Common Data Direction
TYPE common data shift direction control pin. common scan sequence from COM1 COM16 connecting TYPE VSS, reversed connecting TYPE VDD.
5.21. Port Configuration
Operation write (Display clear, etc.) Read busy flag (DB7) address counter (DB0 DB6) write Display data Character generator RAM) read (Display data Character generator
NMOS PMOS
5.21.1. Input port:
5.17. Busy Flag (BF)
When busy flag output DB7. instructions until busy flag
PMOS PMOS
5.21.2. Input port: R/W,
busy flag SPLC782A busy state does accept
5.18. Address Counter (AC)
address counter assigns addresses display data character generator RAM. When instruction address After
NMOS
written address information sent from
writing into reading from)display data character generator RAM, automatically incremented decremented -1). contents output when
5.21.3. Output port: CL2,
5.19. Segment Data Direction
segment data shift direction control pin. data shifted from SEG1 SEG80 connecting VSS, reversed connecting VDD.
PMOS
NMOS
5.21.4. Input Output port:
PMOS PMOS Enable
NMOS
Data
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ELECTRICAL SPECIFICATIONS
6.1. Absolute Maximum Ratings
Characteristics Operating Voltage Driver Supply Voltage Input Voltage Range Operating Temperature Storage Temperature
conditions AC/DC Electrical Characteristics.
Symbol TSTO
Ratings -0.3V +7.0V VDD-0.3V VDD+7.0V -0.3V 0.3V +125
normal operational
Note: Stresses beyond those given Absolute Maximum Rating table cause operational errors damage device.
6.2. Characteristics (VDD 2.4V 4.5V,
Characteristics Operating Voltage Operating Current Input High Voltage Input Voltage Input High Current Input Current Output High Voltage Output Voltage Voltage Drop Voltage Symbol VIH1 VIL1 VOH1 VOL1 VDCOM VDSEG Limit Min. 0.7VDD -0.3 -5.0 0.75VDD Typ. Max. 0.55 0.2VDD Unit Internal clock (Note) Pins:(E, R/W, DB7) Pins: (RS, R/W, DB7) 3.0V 0.1mA, Pins: 0.1mA, Pins: 0.1mA, Pins: COM1 COM16 0.1mA, Pins: SEG1 SEG80 bias bias Test Condition
Note: "L", R/W, open, outputs loads.
6.3. Characteristics (VDD 4.5V 5.5V,
Characteristics Operating Voltage Operating Current Input High Voltage Input Voltage Input High Current Input Current Output High Voltage (TTL) Output Voltage (TTL) Voltage Drop Voltage Symbol VIH1 VIL1 VOH1 VOL1 VDCOM VDSEG Limit Min. -0.3 Typ. Max. -125 Unit Internal clock (Note) Pins:(E, R/W, DB7) Pins: (RS, R/W, DB7) 5.0V 0.1mA, Pins: 0.1mA, Pins: 0.1mA, Pins: COM1 COM16 0.1mA, Pins: SEG1 SEG80 bias bias Test Condition
Note: "L", R/W, open, outputs loads.
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6.4. Characteristics (VDD 4.5V 5.5V, 6.4.1. Internal clock operation
Characteristics Frequency Symbol FOSC1 Limit Min. Typ. Max. Unit
6.4.2. bias resistor
Characteristics Bias Resistor Symbol Limit Min. Typ. Max. Unit K-ohm
6.4.3. Write mode (Writing data from SPLC782A)
Characteristics Cycle Time Pulse Width Rise/Fall Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Symbol tSP1 tHD1 tSP2 tHD2 Limit Min. Typ. Max. Unit Test Condition Pins: R/W, Pins: R/W, Pins: Pins:
6.4.4. Read mode (Reading Data from SPLC782A MPU)
Characteristics Cycle Time Pulse Width Rise/Fall Time Address Setup Time Address Hold Time Data Output Delay Time Data hold time Symbol tSP1 tHD1 tHD2 Limit Min. Typ. Max. Unit Test Condition Pins: R/W, Pins: R/W, Pins: Pins:
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6.5. Characteristics (VDD 2.4V 4.5V, 6.5.1. Internal clock operation
Characteristics Frequency Symbol FOSC1 Limit Min. Typ. Max. Unit
6.5.2. bias resistor
Characteristics Bias Resistor Symbol Limit Min. Typ. Max. Unit K-ohm
6.5.3. Write mode (Writing data from SPLC782A)
Characteristics Cycle Time Pulse Width Rise/Fall Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Symbol tSP1 tHD1 tSP2 tHD2 Limit Min. 1000 Typ. Max. Unit Test Condition Pins: R/W, Pins: R/W, Pins: Pins:
6.5.4. Read mode (Reading data from SPLC782A MPU)
Characteristics Cycle Time Pulse Width Rise/Fall Time Address Setup Time Address Hold Time Data Output Delay Time Data hold time Symbol tSP1 tHD1 tHD2 Limit Min. 1000 Typ. Max. Unit Test Condition Pins: R/W, Pins: R/W, Pins:
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6.6. Write Mode Timing Diagram (Writing Data from SPLC782A)
tSP1
tHD1
tHD1
tHD2
tSP2
Valid Data
6.7. Read Mode Timing Diagram (Reading Data from SPLC782A MPU)
VIH1 VIL1 tSP1
VIH1
VIH1 VIL1
tHD1
VIH1
VIH1 VIL1
VIH1 VIL1
VIH1 VIL1
tHD1
VIL1
tHD2
Valid Data
VIH1 VIL1
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APPLICATION CIRCUITS
7.1. Interface 7.1.1. Interface 8-bit (6805)
6805
COM1 COM16 SEG1 SEG80
PANEL COMMONS
SPLC782A
SEGMENTS
7.1.2. Interface 8-bit (Z80)
IORQ
COM1 COM16
PANEL COMMONS
SPLC782A SEG1 SEG80
SEGMENTS
7.2. Applications 7.2.1. Chip bottom lower view (DIRC "0", "0")
Panel characters line
SEG80
Example dots characters line Bias Duty
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SEG1 COM8 COM1
SPLC782A BOTTOM VIEW
DIRC
NOV. 2001 Version:
SPLC782A
Panel characters line
SEG80
Example dots characters line Bias Duty
Example dots characters lines Bias Duty
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SEG1 COM8 COM1 DIRC
COM8 COM1 SEG1
SPLC782A BOTTOM VIEW
COM11 COM9
Panel characters line
SEG80
SPLC782A BOTTOM VIEW
DIRC
COM16 COM9
NOV. 2001 Version:
SPLC782A
7.2.2. Chip bottom upper view (DIRC "1", "1")
DIRC
COM1 COM8 SEG1
Panel characters line Example dots characters line Bias Duty
SEG80
SPLC782A BOTTOM VIEW
COM1 COM8 SEG1
COM9 COM11 SEG80
DIRC
SPLC782A BOTTOM VIEW
Panel characters line
Example dots characters line Bias Duty
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SPLC782A
COM9 COM16 SEG80
DIRC
COM1 COM8 SEG1
SPLC782A BOTTOM VIEW
Panel characters line
Example dots characters lines Bias Duty
7.2.3. Chip lower view (DIRC "0", "1")
Panel characters line
Example dots characters line Bias Duty
SEG80
SEG1
SPLC782A VIEW
DIRC
COM8 COM1
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SPLC782A
Panel characters line
Example dots characters line Bias Duty
SEG80 COM11 COM9
SEG1
SPLC782A VIEW
COM8 DIRC COM1
Panel characters line
Example dots characters lines Bias Duty
SEG80 COM16 COM9
SEG1
SPLC782A VIEW
COM8 DIRC COM1
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7.2.4. Chip upper view (DIRC "1", "0")
COM1 COM8 SEG1
DIRC
SPLC782A VIEW
Example dots characters line Bias Duty
SEG80 Panel characters line
COM1 COM8 SEG1
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DIRC
COM9 COM11 SEG80
SPLC782A VIEW
Panel characters line
Example dots characters line Bias Duty
NOV. 2001 Version:
SPLC782A
COM1 COM8 SEG1
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DIRC
COM9 COM16 SEG80
SPLC782A VIEW
Panel characters line Example dots characters lines Bias Duty
NOV. 2001 Version:
SPLC782A
CHARACTER GENERATOR
8.1. SPLC782A
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PACKAGE/PAD LOCATIONS
9.1. Assignment
9.2. SPLC782A Dimensions
Item Chip Size Pitch Bumped Size Bumped Height
Note1: Chip size included scribe line. Note2: ensure that functions properly, please bond pins. Note3: 0.1µF capacitor between should placed close possible.
Size 5120 61.2 85.1 40.3 59.2 1690 61.2 40.3 85.1 112.0
Unit
9.3. Ordering Information
Product Number SPLC782A-nnnnV-C
Note1: Code number (nnnnV) assigned customer. Note2: Code number (nnnn 0000 9999); version
Package Type Chip form with gold bump
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SPLC782A
9.4. Locations
Name COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 OSC1 TYPE DIRC MOD0 MOD1 COM9 COM10 COM11 COM12 COM13 COM14 COM15 -2394 -2394 -2394 -2394 -2394 -2394 -2394 -2394 -2327 -2175 -2040 -1959 -1825 -1744 -1568 -1487 -1070 -990 -799 -718 -584 -503 -310 -229 1090 1344 1471 1726 1853 2025 2386 2386 2386 2386 2386 2386 2386 -130 -191 -252 -313 -694 -694 -694 -694 -694 -694 -694 -694 -694 -694 -679 -679 -694 -694 -688 -688 -694 -694 -694 -679 -694 -694 -694 -694 -694 -694 -694 -694 -693 -294 -233 -172 -111 Name COM16 SEG80 SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 2386 2438 2376 2315 2254 2193 2132 2070 2009 1948 1887 1826 1764 1703 1642 1581 1520 1458 1397 1336 1275 1214 1152 1091 1030 -132 NOV. 2001 Version:
Sunplus Technology Co., Ltd. Proprietary Confidential
SPLC782A
Name SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 -193 -254 -315 -377 -438 -499 -560 -621 -683 -744 -805 -866 -927 -989 -1050 -1111 -1172 -1233 -1295 Name SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 -1356 -1417 -1478 -1539 -1601 -1662 -1723 -1784 -1845 -1907 -1968 -2029 -2090 -2151 -2213 -2274 -2335 -2396
Sunplus Technology Co., Ltd. Proprietary Confidential
NOV. 2001 Version:
SPLC782A
DISCLAIMER
information appearing this publication believed accurate. Integrated circuits sold Sunplus Technology covered warranty patent indemnification provisions stipulated terms sale only. SUNPLUS makes warranty, express, statutory implied description regarding information this publication FURTHER, SUNPLUS MAKES WARRANTY SUNPLUS reserves right halt production alter specifications regarding freedom described chip(s) from patent infringement. MERCHANTABILITY FITNESS PURPOSE. prices time without notice. publication current before placing orders.
Accordingly, reader cautioned verify that data sheets other information this Products described herein intended normal commercial applications. Please note that application circuits
Applications involving unusual environmental reliability requirements, e.g. military equipment medical life support equipment, specifically recommended without additional processing SUNPLUS such applications. illustrated this document reference purposes only.
Sunplus Technology Co., Ltd. Proprietary Confidential
NOV. 2001 Version:
SPLC782A
REVISION HISTORY
Date MAY. 2001 JUL. 2001 Revision Original Delete "PRELIMINARY" "with gold bump" "9.3 Ordering Information" Renew document format NOV. 2001 Modify "MODE1" "MOD1", "MODE2" "MOD0" SIGNAL DESCRIPTIONS" Modify pins "CL2" description: "normal mode" "normally use" SIGNAL DESCRIPTIONS" Modify OSC1 description SIGNAL DESCRIPTIONS" Modify Characteristics ELECTRICAL SPECIFICATIONS" Description Page
Sunplus Technology Co., Ltd. Proprietary Confidential
NOV. 2001 Version:

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