80ch Common/Segment Driver Matrix OCT. 2001 Version SUNPLUS

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80ch Common/Segment Driver Matrix OCT. 2001 Version SUNPLUS

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SPLC086A
80ch Common/Segment Driver Matrix
OCT. 2001 Version
SUNPLUS TECHNOLOGY reserves right change this documentation without prior notice. Information provided SUNPLUS TECHNOLOGY believed accurate reliable. However, SUNPLUS TECHNOLOGY makes warranty errors which appear this document. Contact SUNPLUS TECHNOLOGY obtain latest version device specifications before placing your order. responsibility assumed SUNPLUS TECHNOLOGY infringement patent other rights third parties which result from use. addition, SUNPLUS products authorized critical components life support devices/ systems aviation devices/systems, where malfunction failure product reasonably expected result significant injury user, without express written approval Sunplus.
SPLC086A
Table Contents
PAGE
GENERAL DESCRIPTION. FEATURES. BLOCK DIAGRAM 3.1. BLOCK DESCRIPTIONS SIGNAL DESCRIPTIONS 4.1. OUTPUT LEVEL CONTROL. 4.2. DRIVING VOLTAGE APPLICATION CIRCUITS 4.3. DATA SHIFT DIRECTION ACCORDING CONTROL SIGNALS ELECTRICAL SPECIFICATIONS 5.1. MAXIMUM ABSOLUTE LIMIT 5.2. CHARACTERISTICS.11 5.3. CHARACTERISTICS 5.4. POWER DOWN FUNCTION 5.5. OPERATION TIMING DIAGRAM APPLICATION CIRCUITS. 6.1. 1-BIT SERIAL INTERFACE MODE (80-CH SEGMENT DRIVER) 6.2. 4-BIT PARALLEL INTERFACE MODE (80-CH SEGMENT DRIVER) 6.3. SINGLE-TYPE INTERFACE MODE (80-CH COMMON DRIVER). 6.4. DUAL-TYPE INTERFACE MODE (40-CH 40-CH COMMON DRIVER) 6.5. APPLICATION CIRCUIT EXAMPLE PACKAGE/PAD LOCATIONS 7.1. ASSIGNMENT (SPLC086A). 7.2. ORDERING INFORMATION 7.3. LOCATIONS (SPLC086A). 7.4. SPLC086A LQFP TYPE (SPLC086A): 100LQFP 7.5. PACKAGE INFORMATION DISCLAIMER. REVISION HISTORY
Sunplus Technology Co., Ltd. Proprietary Confidential
OCT. 2001 Preliminary Version:
SPLC086A
80CH COMMON/SEGMENT DRIVER MATRIX
GENERAL DESCRIPTION
SPLC086A driver which fabricated power CMOS high voltage process technology. segment driver mode, interfaced 1-bit serial 4-bit parallel method controller. common driver mode, dual type mode applicable. segment mode application, power down function reduces power consumption. 4-bit parallel/1-bit serial data processing segment mode) Single mode operation/dual mode operation common mode) Power down function segment mode) Applicable Duty: 1/64 1/256 Interface Drivers (cascade) (cascade) SPLC086A
FEATURES
Power supply voltage: +5.0V +3.0V Supply voltage display: 6.0V (VDD-VEE)
SPLC086A High voltage CMOS process Available type: bare die, LQFP
BLOCK DIAGRAM
SC78 SC79 SC80
80-bit 4-level driver
80-bit level shifter DISPOFFB Output level selector D1_SID D2_DL D3_DM D4_DR
80-bit data latch/common data bi-directional shift register
4-bit segment data bi-directional shift register
Data latch control Clock control
Power down function
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SPLC086A
3.1. Block Descriptions
Name Clock control Function Generates latch clock (LCK), shift clock (SCK) control clock timing according input CL1, control inputs (CS, AMS). common driver application mode, this block generates shift clock (LCK) common data Bi-directional shift register. Data latch control Determines direction segment data shift, input data each Bi-directional shift register. 4-bit segment data parallel transfer mode, data shifted 4-bit unit. common driver application mode, data transferred common data shift register directly, which disables this block. Power down function Controls clock enable state current driver according input value enable (ELB ERB). enable input value "Low", every clock current driver enabled clock control block works. enable input "High", current driver disabled input data value effect output level. power consumption lowered. Output level selector 20x4-bit segment data bi-directional shift register 80-bit data latch/ common data bi-directional shift register 80-bit level shifter Controls output voltage level according input control DISPOFFB) (refer DESCRIPTION). Stores output data value shifting input values. 1-bit serial interface mode application, 4-bit parallel transfer shift clocks (SCK) needed store display data. does work. segment driver application mode, data from 20x4-bit segment data shift register latched segment driver output. signal input. single-type common driver application, 1-bit input data (from pin) shifted latched direction according dual-type common application mode, 80-bit registers divided blocks COM/SEG controlled independently (refer Data shift direction according control signals). Voltage level shifter block high voltage part. inputs this block logical voltage level outputs this block high voltage level value. These values input driver. 80-bit 4-level driver Selects output voltage level according latched data value. data value "High" driver output selected voltage level V5), reverse case driver output value non-selected level (V12 V43). mode, non-selected output value value becomes segment driver application when common driver application, this COM/SEG COM/SEG COM/SEG COM/SEG COM/SEG
mode application, only clocks needed. common driver application mode, this block
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SPLC086A
SIGNAL DESCRIPTIONS
Mnemonic V43, SC80 Output Input driver output voltage level driver output Input/ Output Name Function Logical "High" input port (+5.0V 10%, +3.0V 10%) (GND) Logical "Low" high voltage part Bias supply voltage input drive LCD. Bias voltage divided resistance usually used supply voltage source (refer Driving Voltage Application Circuit). Display data output which corresponds respective latch contents. V12, selected display driving voltage source according combination latched data level signal (refer Output level control). Input Data shift clock Clock pulse input bi-directional shift register. segment driver application mode, data shifted 4-bit segment data shift register falling edge this clock pulse. clock pulse, which input when enable Controller (ELB/ERB) active condition, invalid. common driver application mode, data shifted 80-bit common data bi-directional shift register clock. Hence, this clock used (Open connect this VDD). Input Input signal Alternate signal input driving. Normal frame inversion signal input this pin. segment driver application mode, this signal used latching shift register contents falling edge this clock pulse. block. common driver application mode, used shifting clock common output data. DISPOFFB Input Display Control Control input driver output (SC1~SC80) level, during "Low" value input. becomes non-selected level output from every output segment drivers every output common drivers. Input COM/SEG mode Control When "Low", SPLC086A used 80-bit segment driver. When "High", SPLC086A 80-bit common driver. According input value pin, application mode SPLC086A differs shown below. VDD/VSS VDD/VSS Controller pulse "High" level initializes power-down function Controller driver output Data latch clock Controller Power Interface Power
Input
Application mode select
Application mode 4-bit parallel interface mode
COM/SEG
1-bit serial interface mode Signal-type application mode Dual-type application mode
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SPLC086A
Mnemonic D1_SID D2_DL D3_DM D4_DR Input/ Output Name Display data input/serial input data/left, right data input output Function segment driver application mode, these pins used 4-bit data input (when 4-bit parallel interface mode: "Low"), D1_SID used serial data input other pins used (connect these VDD) (when 1-bit serial interface mode: "High"). common driver application mode, data shifted from D2_DL (D4_DR) D4_DR (D2_DL), when single type interface mode (AMS "Low"). dual-type application case, data shifted from D2_DL D3_DM (D4_DR D3_DM) D4_DR (D2_DL). each case direction data shift connection data pins determined input (refer Data Shift Direction According Control Interface Controller
Signals Usage Data PINs)
Input Shift direction control Enable data Input/output When "Low", data shifted from left right. When "High", direction reversed. (refer Data Shift Direction According Control Signals) segment driver application mode, internal operation enabled only when enable input (ELB ERB) "Low" (power down function). When several drivers serially connected, enable state each driver shifted according input. Connect these pins below. VDD/VSS
Application mode Output (open) Input (VSS) Input (VSS) Output (open)
common driver application mode, power down function used. Open these pins.
4.1. Output Level Control
Latched data DISPOFFB Output level (SC1 SC80) Mode (V2) (V3) Mode (V1) (V4)
"X": don't care
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SPLC086A
4.2. Driving Voltage Application Circuits 4.2.1. Segment driver application "Low")
SEG1~ SEG80
Panel
Driver
(n-4)
SPLC086A
Driver
V0,V5 Selection level
V2,V3 Non-selection level *n=9(when 1/64 duty) 17(when 1/256 duty)
4.2.2. Common driver application "High")
driver
Panel
(n-4)R
SPLC086A
V0,V5 V1,V4 Selection level Non-selection level
*n=9(when 1/64 duty) 17(when 1/256 duty)
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SPLC086A
4.3. Data Shift Direction According Control Signals 4.3.1. When "Low" (segment driver application)
Application Mode
Data Direction
Input
4-Bit Parallel Data Transfer Mode (SEG)
Shift direction last data first data
D1_SID, D2_DL,
D3_DM, D4_DR,
Shift direction first data
last data
1-Bit Serial Data Transfer Mode (SEG)
last data (D1_SID)
Shift direction
first data
D1_SID
first data
Shift direction
last data
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SPLC086A
4.3.2. When "High" (common driver application)
Application Mode Data Direction
Shift direction
Input
D2_DL
Input data (D2_DL)
Output data (D4_DR)
Single-type Application Mode (COM)
Shift direction
D4_DR
Output data (D2_DL)
Input data (D4_DR)
Shift direction
D2_DL D3_DM
Input data1 (D2_DL)
Input data2 (D3_DM)
Output data (D4_DR)
Dual-type Application Mode (COM)
Shift direction
D4_DR D3_DM
Output data (D2_DL)
Input data2 (D3_DM)
Input data1 (D4_DR)
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SPLC086A
4.3.3. Usage Data PINs
COM/SEG pin) Application mode (AMS pin) 4-bit parallel interface ="Low") mode (AMS "Low") 1-bit serial interface mode (AMS "High") Single-type application "High") mode (AMS "Low") Dual-type application mode (AMS "High") Data interface D1_SID (input) (input) Open (input) (output) (input1) (output2) D2_DL (input2) D3_DM (input3) Connect Open (input2) (input2) (output) (input) (output2) (input1) D4_DR (input4) don't care
Open
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SPLC086A
ELECTRICAL SPECIFICATIONS
5.1. Maximum Absolute Limit
Characteristic Power supply voltage Driver supply voltage Input voltage Operating temperature Storage temperature
Note: Voltage greater than above damage circuit.
Symbol VLCD TOPR TSTG
Value -0.3 +7.0 -0.3 +150
Unit
5.2. Characteristics 5.2.1. Segment driver application
(VSS +85°C) Characteristic Operating voltage1 Symbol VLCD IIL1 IIL2 ISTBY Supply current -0.4mA 0.4mA 100µA fCL1 32KHz fCL1 32KHz 80Hz 5.0V 3.0V 5.0V Test Condition Min. 0.8VDD VDD-0.4 Typ. Max. 0.2VDD Unit
Input voltage
Output voltage Input leakage current Input leakage current resistance
Note1: Applied CL1, CL2, ELB, ERB, D1_SID~D4_DR, SHL, DISPOFFB, Note2: ELB, Note3: V12, V43, Note4: VLCD VEE, 5.0V, -23V VDD-2/n (VLCD), VEE+2/n (VLCD), (1/256 duty, 1/17 bias) Note5: VDD, 1.71V (VDD 5.0V) 0.06V (VDD 3.0V), -19.71V (VDD 5.0V) -19.94V (VDD 3.0V), -23V, no-load condition (1/256 duty, 1/17 bias) 4-bit parallel interface mode ISTBY: 5.0V, fCL2 5.12MHz, VSS, DISPOFFB VDD, VSS, display data pattern 0000 3.0V, fCL2 4.0MHz, display data pattern 0101 fCL2 5.12MHz, display data pattern 0101 IEE: 5.0V, fCL2 5.12MHz, display data pattern 0101,
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5.2.2. Common driver application
(VSS +85°C) Characteristic Operating voltage Symbol VLCD IIL1 IIL2 IIL3 ISTBY Supply current
Test Condition -0.4mA 0.4mA 5.0V (PULL 100µA fCL1 32kHz fCL1 32kHz 80Hz 5.0V 3.0V 5.0V
Min. 0.8VDD VDD-0.4
Typ. -125
Max. 0.2VDD -250
Unit
Input voltage
Output voltage Input leakage current Input leakage current Input leakage current resistance
Note1: Applied CL1, D2_DL (SHL LOW), D4_DR (SHL HIGH), SHL, DISPOFFB, Note2: Pull-up input pins: CL2, D1_SID, D3_DM (AMS HIGH), (SHL LOW), (SHL HIGH) Note3: D2_DL (SHL HIGH), D4_DR (SHL LOW) Note4: V12, V43, Note5: VLCD VDD-VEE, 5.0V, -23V VDD-1/n(VLCD), VEE+1/n(VLCD), 17(1/256 duty, 1/17 bias) Note6: VDD, 3.35V (VDD 5.0V) 1.47V (VDD 3.0V), -21.35V (VDD 5.0V) -21.47V (VDD 3.0V), -23V, no-load condition (1/256 duty, 1/17 bias) single-type mode operation: VSS, VSS, DISPOFFB D1_SID D3_DM VDD, D4_DR OPEN, OPEN, ISTBY: 5.0V, VSS, D2_DL IDD: 80Hz, D2_DL 3.0V, display data pattern 10000000., 01000000., 00100000., 00010000., 5.0V, display data pattern 10000000., 01000000., 00100000., 00010000., IEE: 80Hz, D2_DL 5.0V, current through Pin, display data pattern 10000000., 01000000., 00100000., 00010000.
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5.3. Characteristics 5.3.1. Segment driver application
(VSS 30°C +85°C) Characteristic Clock cycle time Clock pulse width Clock rise/fall time Data set-up time Data hold time Clock set-up time Clock hold time Propagation delay time Symbol tWCK tR/tF tPHL tPSU tWDL tPD1 tPD2 tPD3 15pF Test Condition Duty Output Output Input Input 5.0V ±10% Min. Typ. Max. 3.0V ±10% Min. Typ. Max. Unit
ELB, set-up time DISPOFFB pulse width DISPOFFB clear time propagation delay time propagation delay time DISPOFFB propagation delay time
5.3.2. Common driver application
(VSS 30°C +85°C) Characteristic Clock cycle time Clock pulse width Clock rise fall time Data set-up time Data hold time DISPOFFB pulse width DISPOFFB clear time Output delay time propagation delay time propagation delay time DISPOFFB propagation delay time Symbol tWCK tR/tF tWDL tPD1 tPD2 tPD3 15pF Test Condition Duty 5.0V ±10% Min. Typ. Max. 3.0V ±10% Min. Typ. Max. Unit
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5.3.3. Segment driver application timing
0.8VDD 0.2VDD
tWCK
tWCK
0.8VDD 0.2VDD
0.8VDD 0.2VDD
0.8VDD 0.2VDD
0.8VDD 0.2VDD
tWCK
0.8VDD 0.2VDD
D1_SID~ D4_DR
tWDL
0.8VDD 0.2VDD
DISPOFFB
0.2VDD
tPHL
0.8VDD
ELB,ERB (Output ELB,ERB (Input
0.8VDD 0.2VDD 0.2VDD
0.8VDD 0.2VDD
tPD3
tPD2
0.2VDD
tPSU 0.2VDD
tPD1
DISPOFFB
SC1-SC80 (Latched data)
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5.3.4. Common driver application timing
0.8VDD
tWCKH
0.8VDD 0.2VDD
0.2VDD
0.8VDD
(*1)
0.2VDD
0.8VDD 0.2VDD
(*1)
0.8VDD 0.2VDD
DISPOFFB
tWDL
(*1)When single-type interface mode D2_DL (SHL "L"), D4_DR (SHL "H") D4_DR (SHL "L"), D2_DL (SHL ="H") When dual-type interface mode D2_DL D3_DM (SHL "L"), D4_DR D3_DM (SHL= "H") D4_DR (SHL "L"), D2_DL (SHL "H") 0.8VDD 0.2VDD
tPD1
tPD2 0.2VDD
0.8VDD
DISPOFFB
0.2VDD
tPD3
SC1-SC80 (Latched data)
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5.4. Power Down Function
case cascade connection segment mode drivers, SPLC086A "power down function" order reduce power consumption.
Enable input
Enable output
Current driver status While ="Low", current driver enabled. While ="Low", current driver enabled.
other drivers status Disabled Disabled
Note: case common driver application, power down function does work.
ELB1 (Input1) ERB1/ELB2 (Output1/Input2)
ERB2/ELB3 (Output2/Input3) ERB3/ELB4 (Output3/Input4)
ELB4 (Output4) Note1: "High" (ELB Input, Output) Current SPLC086A's must connected next SPLC086A's ELB. Note2: When 4-bit parallel interface mode: When 1-bit serial interface mode:
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5.5. Operation Timing Diagram 5.5.1. 4-bit parallel mode interface segment driver
When "Low"
D1_SID
SC77
SC73
SC69
SC77
SC73
D2_DL
SC78
SC74
SC70
SC78
SC74
D3_DM
SC79
SC75
SC71
SC79
SC75
D4_DR
SC80
SC76
SC72
SC80
SC76
ERB(Input) ELB(Output)
SC1_SC80
When "High"
D1_SID
SC76
SC80
SC12
SC76
SC80
D2_DL
SC75
SC79
SC11
SC75
SC79
D3_DM
SC74
SC78
SC10
SC74
SC78
D4_DR
SC73
SC77
SC73
SC77
ELB(Input) ERB(Output)
SC1_SC80
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5.5.2. 1-bit serial mode interface segment driver
When "Low"
D1_SID (Input)
SC80
SC79
SC78
SC80
SC79
ELB(Output)
SC1_SC80
When "High"
D1_SID (Input)
SC79
SC80
SC79
SC80
ERB(Output)
SC1_SC80
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5.5.3. Single-type interface mode common driver
When "Low"
urre drive
When "High"
4_DR
D2_DL
M_DATA1
M_DATA2
M_DATA3
M_DATA79
M_DATA80
urrent driver's area
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5.5.4. Dual-type interface mode common driver
When "Low"
D2_DL D3_DM D4_DR
COM_DATA1 COM_DATA2 COM_DATA3 COM_DATA39 COM_DATA40 COM_DATA41 COM_DATA42 COM_DATA43
COM_DATA79 COM_DATA80
When "High"
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5.5.5. Common/segment driver timing (1/200 duty)
Latched Data (SEG)
COM_DATA1 COM_DATA199 COM_DATA200
COM1
COM199
COM200
SEG_DATA1
SEG1
D1~D4
Latched_Data
Enable
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APPLICATION CIRCUITS
6.1. 1-Bit Serial Interface Mode (80-ch Segment Driver)
Lower view (SHL
PANEL
S160
Sn+80
SC80 D1_SID
1-bit serial data input
SC80
SC80
D2_DL~ D4_DR
D1_SID
D2_DL~ D4_DR
D1-SID
D2_DL~ D4_DR
Upper view (SHL
1-bit serial data input
D4_DR D2_DL~
D1_SID
SC80
D4_DR D2_DL~
D1_SID
SC80
D4_DR D2_DL~
D1_SID
SC80
S160
Sn+80
PANEL
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6.2. 4-Bit Parallel Interface Mode (80-ch Segment Driver)
Lower View (SHL
PANEL
S160
Sn+80
SC80
SC80
SC80
D1_SID D4_DR
D1_SID D4_DR
D1_SID D4_DR
4-bit serial data input
Upper View (SHL
4-bit serial data input
D1_SID D4_DR
D1_SID D4_DR
D1_SID D4_DR
SC80
SC80
SC80
S160
Sn+80
PANEL
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6.3. Single-Type Interface Mode (80-ch Common Driver)
input data
D4_DR SC80 D2_DL
D4_DR D2_DL
SC80
PANEL
C160
D4_DR D2_DL
SC80
C161
C240
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6.4. Dual-Type Interface Mode (40-ch 40-ch Common Driver)
Input data
(1/2
(2/2
Note: Using this application mode (dual-type common mode), duty ratio reduced half. case, 1/200 duty used drive common panel.
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6.5. Application Circuit Example
/SEG
(n-4)R
V0~V5D1_SID D4_DR DISPLFFB SPLC086A
V0~V5 D1_SID D4_DR DISPOFFB SPLC086A
V0~V5 D1_SID D4_DR DISPLFFB SPLC086A
/SEG
SC80
SC80
SC80
SEG1~SEG80
SEG1~SEG80
S160
SEG1~SEG80
S161
DISPLFFB
D4_DR SC80
COM1~ COM80
SPLC086A
D2_DL
V0~V5
DISPLFFB
D4_DR SC80
COM1~ COM80
MODULE
C161
SPLC086A
D2_DL
V0~V5
DISPLFFB
Controller DISPOFFB FRAME(M) COM_DATA D1~D4
D4_DR SC80
COM1~ COM80
C161
SPLC086A
D2_DL
C240
V0~V5
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PACKAGE/PAD LOCATIONS
7.1. Assignment (SPLC086A)
SC75
SC74
SC73
SC59
SC58
SC57
SC54
SC77
SC76
SC72
SC70
SC69
SC68
SC65
SC63
SC62
SC61
SC60
SC56
SC55
SC71
SC67
SC66
SC64
SC53 SC52 SC51 SC50 SC49 SC48 SC47 SC46 SC45 SC44 SC43 SC42 SC41 SC40 SC39 SC38 SC37 SC36 SC35 SC34 SC33 SC32 SC31 SC30 SC29 SC28 SC27
SC78 SC79 SC80 DISPOFFB D4-DR D3-DM D2-DL D1-SID SPLC086A (0,0)
SC10
SC11
SC12
SC13
SC14
SC16
SC17
SC18
SC19
SC20
SC21
SC22
SC23
SC24
SC25
Chip Size: 3190µm 3260µm Size: 96µm 96µm This substrate should connected
Note1: Chip size included scribe line. Note2: 0.1µF capacitor between should placed close possible.
7.2. Ordering Information
Product Number SPLC086A-nnnV-C SPLC086A-nnnV-P
Note1: Code number (nnnV) assigned customer. Note2: Code number (nnnn 0000 9999); version
SC15
Package Type Chip form Package form 100LQFP
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SPLC086A
7.3. Locations (SPLC086A)
Name SC28 SC29 SC30 SC31 SC32 SC33 SC34 SC35 SC36 SC37 SC38 SC39 SC40 SC41 SC42 SC43 SC44 SC45 SC46 SC47 SC48 SC49 SC50 SC51 SC52 SC53 SC54 SC55 SC56 SC57 SC58 SC59 SC60 SC61 Locations 1445 1445 1445 1445 1445 1445 1445 1445 1445 1445 1445 1445 1445 1445 1445 1445 1445 1445 1445 1445 1445 1445 1445 1445 1445 1445 1318 1190 1064 -1360 -1240 -1120 -1005 -890 -775 -659 -549 -439 -329 -219 -109 1001 1116 1236 1356 1476 1476 1476 1476 1476 1476 1476 1476 1476 Name SC62 SC63 SC64 SC65 SC66 SC67 SC68 SC69 SC70 SC71 SC72 SC73 SC74 SC75 SC76 SC77 SC78 SC79 SC80 DISPOFFB D4-DR D3-DM D2-DL Locations -111 -227 -343 -459 -575 -691 -812 -933 -1054 -1180 -1308 -1445 -1445 -1445 -1445 -1445 -1445 -1445 -1445 -1445 -1445 -1445 -1445 -1445 -1445 -1445 -1445 -1445 -1445 -1445 1476 1476 1476 1476 1476 1476 1476 1476 1476 1476 1476 1476 1476 1476 1476 1476 1356 1236 1116 1001 -109 -219 -329 -439 -549 Name D1-SID SC10 SC11 SC12 SC13 SC14 SC15 SC16 SC17 SC18 SC19 SC20 SC21 SC22 SC23 SC24 SC25 SC26 SC27 Locations -1445 -1445 -1445 -1445 -1445 -1445 -1445 -1445 -1308 -1180 -1054 -933 -812 -691 -575 -459 -343 -227 -111 1064 1190 1318 1445 -659 -775 -890 -1005 -1120 -1240 -1360 -1480 -1480 -1480 -1480 -1480 -1480 -1480 -1480 -1480 -1480 -1480 -1480 -1480 -1480 -1480 -1480 -1480 -1480 -1480 -1480 -1480 -1480 -1480 -1480 -1480
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7.4. SPLC086A LQFP Type (SPLC086A): 100LQFP
D1_SID
D2_DL
D3_DM
D4_DR
DISPOFFB
SC80
SC79
SC78
SC10 SC11 SC12 SC13 SC14 SC15 SC16 SC17 SC18 SC19 SC20 SC21 SC22 SC23 SC24 SC25 SC26 SC27
SC77 SC76 SC75 SC74 SC73 SC72 SC71 SC70 SC69 SC68 SC67
SPLC086A
SC66 SC65 SC64 SC63 SC62 SC61 SC60 SC59 SC58 SC57 SC56 SC55 SC54 SC53
SC28
SC29
SC30
SC31
SC32
SC33
SC34
SC35
SC36
SC37
SC38
SC39
SC40
SC41
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Sunplus Technology Co., Ltd. Proprietary Confidential
SC52
OCT. 2001 Preliminary Version:
SPLC086A
7.5. Package Information
Sunplus Technology Co., Ltd. Proprietary Confidential
OCT. 2001 Preliminary Version:
SPLC086A
DISCLAIMER
information appearing this publication believed accurate. Integrated circuits sold Sunplus Technology covered warranty patent indemnification provisions stipulated terms sale only. SUNPLUS makes warranty, express, statutory implied description regarding information this publication FURTHERMORE, SUNPLUS MAKES WARRANTY SUNPLUS reserves right halt production alter specifications regarding freedom described chip(s) from patent infringement. MERCHANTABILITY FITNESS PURPOSE. prices time without notice. publication current before placing orders.
Accordingly, reader cautioned verify that data sheets other information this Products described herein intended normal commercial applications. Please note that application circuits
Applications involving unusual environmental reliability requirements, e.g. military equipment medical life support equipment, specifically recommended without additional processing SUNPLUS such applications. illustrated this document reference purposes only.
Sunplus Technology Co., Ltd. Proprietary Confidential
OCT. 2001 Preliminary Version:
SPLC086A
REVISION HISTORY
Date OCT. 2001 Revision Original Description Page
Sunplus Technology Co., Ltd. Proprietary Confidential
OCT. 2001 Preliminary Version:

80ch Common/Segment Driver Matrix OCT. 2001 Version SUNPLUS

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