Interface OCT. 2001 Version SPLC3508A Table Contents

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Interface OCT. 2001 Version SPLC3508A Table Contents

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SPLC3508A
Interface
OCT. 2001 Version
SPLC3508A
Table Contents
PAGE
GENERAL DESCRIPTION. FEATURES. STRUCTURE. BLOCK DIAGRAM SIGNAL DESCRIPTIONS 5.1. CONFIGURATION ELECTRICAL SPECIFICATIONS 6.1. ABSOLUTE MAXIMUM RATINGS 25). 6.2. RECOMMENDED OPERATING CONDITIONS 6.3. CHARACTERISTICS (VDD 3.0V 3.6V, +75) 6.4. CHARACTERISTICS (VDD 3.0V 3.6V, +75) 6.5. TIMING DEFINITION 6.6. PCI, 6.7.
6.8. SLIN 6.9. HORIZONTAL DIRECTION INPUT SIGNAL TIMING CHART 6.10. VERTICAL DIRECTION INPUT SIGNAL TIMING CHART 6.11. HORIZONTAL DIRECTION TIMING CHART 6.12. VERTICAL DIRECTION TIMING CHART APPLICATION CIRCUIT PACKAGE/PAD LOCATIONS 8.1. PACKAGE OUTLINE. DISCLAIMER. REVISION HISTORY
Sunplus Technology Co., Ltd. Proprietary Confidential
OCT. 2001 Version:
SPLC3508A
INTERFACE
GENERAL DESCRIPTION
SPLC3508A interface color module.
BLOCK DIAGRAM
B02, B12, B22, R01, R11, R21, XR01, XR11, XR21, XR31 R02, R12, R22, XR02, XR12, XR22, XR32 G01, G11, G21, XG01, XG11, XG21, XG31 G02, G12, G22,
FEATURES
DATA
Generates driving pulses color module. Standby mode function Thin package (100-pin TQFP)
Serial/ Parallel Conversion Block
XG02, XG12, XG22, XG32 B01, B11, B21, XB01, XB11, XB21, XB31
STRUCTURE
Silicon gate CMOS
XB02, XB12, X22, XB32
Power CTR.
Hsync/DENB SLIN
Counter
HST1 XHST1 HST2 XHST2 HCK1 XHCK1 HCK2 XHCK2 XOE1 XOE2 XVST XVCK XENB
Timing Pulse GEN.
Vsync
Counter
Timing Pulse GEN.
Timing Generator Block
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OCT. 2001 Version:
SPLC3508A
SIGNAL DESCRIPTIONS
Mnemonic Hsync/DENB Vsync SLIN XR31 XR21 XR11 XR01 XG31 Type connection connection System reset signal input (MSB) signal input signal input Signal input (LSB) Green signal input (MSB) Green signal input Green signal input Green signal input (LSB) Blue signal input (MSB) Blue signal input Blue signal input Blue signal input (LSB) Hsync/data enable pulse input Vsync pulse input clock input Power control signal input Sync input signal mode switch connection Data phase adjustment Power supply Power control signal output signal output signal output signal output signal output Green signal output Green signal output Green signal output Green signal output Blue signal output Blue signal output Blue signal output Blue signal output signal output (inverse) signal output (inverse) signal output (inverse) signal output (inverse) Green signal output (inverse) Description Input open status UP*2 DWN*1 DWN*1 OCT. 2001 Version:
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SPLC3508A
Mnemonic XG21 XG11 XG01 XB31 XB21 XB11 XB01 XVST XENB XVCK HCK1 XHCK1 HCK2 XHCK2 HST1 XHST1 HST2 XHST2 XOE1 XOE2 XB02 XB12 XB22 XB32 XG02 XG12 XG22 XG32 XR02 XR12 XR22 XR32 Type Description Green signal output (inverse) Green signal output (inverse) Green signal output (inverse) Blue signal output (inverse) Blue signal output (inverse) Power supply Blue signal output (inverse) Blue signal output (inverse) pulse output pulse output (inverse) pulse output pulse output (inverse) pulse output pulse output (inverse) HCK1 pulse output HCK1 pulse output (inverse) HCK2 pulse output HCK2 pulse output (inverse) HST1 pulse output HST1 pulse output (inverse) HST2 pulse output HST2 pulse output (inverse) pulse output pulse output (inverse) pulse output pulise output (inverse) Blue signal output (inverse) Blue signal output (inverse) Blue signal output (inverse) Power supply Blue signal output (inverse) Green signal output (inverse) Green signal output (inverse) Green signal output (inverse) Green signal output (inverse) signal output (inverse) signal output (inverse) signal output (inverse) signal output (inverse) Blue signal output Blue signal output Blue signal output Blue signal output Input open status OCT. 2001 Version:
Sunplus Technology Co., Ltd. Proprietary Confidential
SPLC3508A
Mnemonic Type Description Green signal output Green signal output Green signal output Green signal output signal output signal output signal output signal output Polarity inversion pulse signal output connection Power supply Input open status
Note*1: Built-in pull-down resistor (82.5K) Note*2: Built-in pull-up resistor (82.5K)
5.1. Configuration
XHCK2 XHCK1 XHST2 XHST1 XVCK XENB XOE2 XOE1 HCK2 HCK1 XVST HST2 HST1
XB22
XB12
XB02
XB01
XB11
XB32 XG02 XG12 XG22 XG32 XR02 XR12 XR22 XR32 Hsync/DENB Vsync SLIN XB21 XB31 XG01 XG11 XG21 XG31 XR01 XR11 XR21 XR31
Sunplus Technology Co., Ltd. Proprietary Confidential
OCT. 2001 Version:
SPLC3508A
ELECTRICAL SPECIFICATIONS
6.1. Absolute Maximum Ratings
Characteristics Supply voltage Input voltage Output voltage Operating temperature Storage temperature
conditions AC/DC Electrical Characteristics.
Symbol TOPR TSTG
Ratings +5.5 +150
Unit
normal operational
Note: Stresses beyond those given Absolute Maximum Rating table cause operational errors damage device.
6.2. Recommended Operating Conditions
Characteristics Supply voltage Operating temperature Symbol TOPR Ratings Unit
6.3. Characteristics (VDD 3.0V 3.6V, +75)
Characteristics Supply voltage Current consumption Input voltage Applicable pins Symbol VIH1 VIL1 VtVt+ Vt|IIL1| |IIH1| |IIL2| |IIH2| |IIL3| |IIH3| VOL1 VOH1 Limit Min. VDD-0.2 Typ. Max. Unit load, 3.3V MCK: 5.58MHz LVTTL level input Condition
Input voltage
input pins excluding
LVTTL level input Schmitt trigger input IOL1 0.75mA IOH1 -0.50mA
Input current
Hsync/DENB, Vsync, MCK,
Input current
Input current
SLIN,
Output voltage
ENB, XENB
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OCT. 2001 Version:
SPLC3508A
Characteristics
Applicable pins R01, R11, R21, R31, R02, R12, R22, R32, XR01, XR31, XR22, XR11, XR02, XR32, XR21, XR12, G01,
Symbol
Limit Min. Typ. Max.
Unit
Condition
VOL2
IOL2 1.5mA
G11, G21, G31, G02, G12, G22, G32, XG01, XG11, Output voltage XG02, XG21, XG12, XG31, XG22,
XG32, B01, B11, B21, B31, B02, B12, B22, B32, XB21, XB12, XVCK, XB01, XB31, XB22, OE1, XB11, XB02, XB32, XOE1, VOH2 VDD-0.2 IOH2 -1.0mA
PCO, VST, XVST, VCK, OE2, XOE2, Output voltage HST1, XHST1, HST2, XHST2 HCK1, XHCK1, HCK2, XHCK2 VOL3 VOH3 VOL4 VOH4 VDD-0.2 VDD-0.2 IOL3 3.0mA IOH3 -2.0mA IOL4 4.5mA IOH4 -3.0mA
Output voltage
6.4. Characteristics (VDD 3.0V 3.6V, +75)
Characteristics Applicable pins HCK1, HCK2, XHCK1, XHCK2, HST1, HST2, XHST1, XHST2 output HCK1, HCk2, XHCK1, XHCK2, HST1, HST2, XHST1, XHST2 VCK, XVST, XOE1, XVCK, OE1, XOE2, VST, OE2, FRP, tFHP tRVP tFVP Symbol Limit Min. Typ. Max. Unit Condition
HCK,
time
tHST-HCKU tHST-HCKD
difference pulse
15*2
rise time pulse output fall time pulse output rise time pulse output fall time
tRHP
GND-VDD 90%) VDD-GND (100 10%) GND-VDD 90%) VDD-GND (100 10%)
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OCT. 2001 Version:
SPLC3508A
Characteristics Applicable pins R01, R11, R21, R31, R02, R12, R22, R32, XR01, Data output rise time XR31, XR11, XR02, XR21, XR12, Symbol Limit Min. Typ. Max. Unit Condition
GND-VDD
XR22, XR32, G01, G11, G21, G31, G02, G12, G22, XG11, XG02, G32, XG21, XG12, XG01, XG31, XG22,
90%)
XG32, B01, B11, B21, Data output fall time B31, B02, B12, B22, B32, XB21, XB01, XB31, XB11, XB02,
VDD-GND
(100 10%)
XB12, XB22, XB31 pulse output rise time ENB, XENB pulse output fall time HCK1, HCK2, XHCK1, XHCK2, R01, R11, R21, R31, R02, R12, R22, R32, XR21, XR12, HCK1, HCK2, XHCK1, XHCK2/ DATA setup time XR01, XR31, XR22, XR11, XR02, XR32, tFEP tREP
GND-VDD 90%) VDD-GND (100 10%)
G01, G11, G21, G31, G02, G12, G22, G32, XG01, XG31, XG11, XG02, XG21, XG12, tSTP
XG22, XG32, B01, B11, B21, B31, B02, B12, B22, B32, XB01, XB11, XB21, XB31, XB02,
XB12, XB22, XB32 HCK1, HCK2, XHCK1, HCK, duty XHCK2, VCK, XVCK dVCK dHCK
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SPLC3508A
Note*1: (Capacitor Loading) each output shown below. R01, R11, R21, R31, R02, R12, R22, R32, XR01, XR11, XR21, XR31, XR02, XR12, XR22, XR32, G01, G11, G21, G31, G02, G12, G22, G32, XG01, XG11, XG21, X31, XG02, XG12, XG22, XG32, B01, B11, B21, B31, B02, B12, B22, B32, XB01, XB11, XB21, XB31, XB02, XB12, XB22, XB32, ENB, XENB: 70pF. HCK1, HCK2, XHCK1, XHCK2 HST, XHST, VCK, XVCK VST, XVST 150pF 100pF 85pF
OE1, XOE1, OE2, XOE2, PCO, 60pF Note2*: absolute value time difference (HST1, XHST1, HCK1, XHCK1) within 15ns. same, absolute value time difference (HST2, XHST2, HCK2, XHCK2) within 15ns. Note3*: tSTP: tST1D, tST1U, tST2D, tST2U 6.0MHz Note4*: dHCK (tHH/(tHH tHL)) 100, dVCK (tVH/(tVH tVL))
6.5. Timing Definition 6.5.1. system
HCK1 XHCK1
HCK2 XHCK2
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OCT. 2001 Version:
SPLC3508A
HST1 (HST2) XHST1 (XHST2) HCK1 (HCK2) XHCK1 (XHCK2) tHST-HCKU tHST-HCKD
6.5.2. system
XVCK
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SPLC3508A
6.5.3. DATA
HCK1 XHCK1
HCK2 XHCK2
DATA tST1D tST2D tST1U tST2U
tSTX1U
tSTX2U
tSTX1D
tSTX2D
6.6. PCI,
There input output power up/down sequence. Please connect system that control power on/off module SPLC2475A. (ex. DC-DC Converter)
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OCT. 2001 Version:
SPLC3508A
6.6.1. Power sequence
Inactive (low) Inactive (low) Active Active
Pulse*
Inactive (low)
Active
Data (out) Hsync Vsync DENB DATA (in)
Inactive (low)
White Data Fields
Valid
Invalid (low)
Valid
Field (typ.) 528H (min.)
6.6.2. Power down sequence (Standby)
Active (high) Active (high) Inactive (low) DATA Valid White Data Invalid (all low) Standby Mode
Inactive (low)
Pulse*
Valid
Invalid (all low)
Vsync
DENB Fields Fields
Note*: HST1, HST2, XHST1, XHST2, HCK1, HCK2, XHCK1, XHCK2, VST, XVST, VCK, XVCK, ENB, XENB, OE1, XOE1, OE2, XOE2,
Sunplus Technology Co., Ltd. Proprietary Confidential
OCT. 2001 Version:
SPLC3508A
6.7.
This selector switch phase relationship between data other pulse. (Normally, low)
HCK1 XHCK1 HCK2 XHCK2
(FA:L) Default
OUTPUT DATA R/G/B OUTPUT DATA R/G/B
Invalid Invalid
(FA:H)
OUTPUT DATA R/G/B OUTPUT DATA R/G/B
Invalid Invalid
6.8. SLIN
This selector switch input sync signal mode. SLIN: Hsync Vsync Mode SLIN: HIGH DENB ONLY Mode (Vsync input invalid.)
Sunplus Technology Co., Ltd. Proprietary Confidential
OCT. 2001 Version:
SPLC3508A
dots Hsync*
dots dots dots
DENB* DATA
dots
thss
tclk tdes thsw tdeh
Hsync* DENB*
6.9. Horizontal Direction Input Signal Timing Chart
DATA
Input either Hsync Vsync DENB sync signal.
Input Signal Characteristics
Item Item frequency low, high pulse width DATA setup time DATA hold time DENB setup time DENB hold time Hsync setup time Hsync pulse width Symbol ftclk tch, tdes tdeh thss thsw
(VDD 3.6V
Min.
Typ.
Max.
3MHz 5.58MHz 8MHz
0.5tclk
10ns
10ns
15ns
10ns
4tclk
16tclk
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15ns
Sunplus Technology Co., Ltd.
OCT. 2001
Version:
SPLC3508A
lines Hsync*
Vsync*
lines
lines
DENB*
Hsync* tvhde Vsync*
6.10. Vertical Direction Input Signal Timing Chart
DENB*
tvsw
DATA
Input either Hsync Vsync DENB sync signal.
Input Signal Characteristics
(VDD 3.6V Item Item Vsync falling edge Hsync rising edge Vsync pulse width Symbol tvhde tvsw
Min.
Typ.
Max.
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OCT. 2001
334tclk
349tclk
lines
lines
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Version:
SPLC3508A
Hsync DENB DATA R/G/B 01-31
Input
Output
R/G/B 02-32
HST1 XHST1 HCK1 XHCK1 HST2 XHST2 HCK2 XHCK2 XOE1 XOE2
6.11. Horizontal Direction Timing Chart
XENB
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XVST XVCK
OCT. 2001
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Version:
SPLC3508A
Hsync Vsync line line DENB
Input
Output
XVST VHCK XENB XOE1 line
line
line
line
6.12. Vertical Direction Timing Chart
XOE2 *FRP(O) *FRP(E) line line
Sunplus Technology Co., Ltd.
OCT. 2001
output timing field. output timing even field.
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SPLC3508A
APPLICATION CIRCUIT
module
XOE2
XOE1
XHST2
XHST1
XB22
XB12
XB02
XHCK2
XHCK1
XB01
XVCK
XENB
HCK2
HCK1
XVST
HST2
HST1
XB11
XB21 XB31
XB32 XG02 XG12 XG22 XG32 XR02 XR12 XR22 XR32 Hsync/DENB
XG01
XG11 XG21 XG31 XR01 XR11 XR21 XR31 Vsync SLIN
module
SPLC2475A (PINs Input DC-DC Converter
Connect system that control power on/off module SPLC2475A. (ex. DC-DC converter)
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OCT. 2001 Version:
module
SPLC3508A
PACKAGE/PAD LOCATIONS
8.1. Package Outline
100PIN TQFP (PLASTIC) Unit:
Sunplus Technology Co., Ltd. Proprietary Confidential
OCT. 2001 Version:
SPLC3508A
DISCLAIMER
information appearing this publication believed accurate. Integrated circuits sold Sunplus Technology covered warranty patent indemnification provisions stipulated terms sale only. SUNPLUS makes warranty, express, statutory implied description regarding information this publication FURTHERMORE, SUNPLUS MAKES WARRANTY SUNPLUS reserves right halt production alter specifications regarding freedom described chip(s) from patent infringement. MERCHANTABILITY FITNESS PURPOSE. prices time without notice. publication current before placing orders.
Accordingly, reader cautioned verify that data sheets other information this Products described herein intended normal commercial applications. Please note that application circuits
Applications involving unusual environmental reliability requirements, e.g. military equipment medical life support equipment, specifically recommended without additional processing SUNPLUS such applications. illustrated this document reference purposes only.
Sunplus Technology Co., Ltd. Proprietary Confidential
OCT. 2001 Version:
SPLC3508A
REVISION HISTORY
Date SEP. 2000 OCT. 2000 OCT. 2001 Revision Original Delete "PRELIMINARY" Renew document format Description Page
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OCT. 2001 Version:

Interface OCT. 2001 Version SPLC3508A Table Contents

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