500020D December 2001 Ordering Information Model Number M283

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500020D December 2001 Ordering Information Model Number M283

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M28335 Twelve Port T3/E3/STS-1 Line Interface Unit
500020D December 2001
Ordering Information
Model Number M28335-11p Package 580-pin TBGA Description Twelve Port T3/E3/STS-1 Operating Temperature
Revision History
Revision Level Advance Advance Advance Advance Date
February 2001 2001 October 2001 December 2001 Initial release. Changed document number from 101487B 500020B. Added number information M28335 Definitions table. Misc. updates. Updated register RLOS information. Added definition.
Description
2001, Mindspeed TechnologiesTM, Conexant Business Rights Reserved.
Information this document provided connection with Mindspeed Technologies ("Mindspeed") products. These materials provided Mindspeed service customers used informational purposes only. Mindspeed assumes responsibility errors omissions these materials. Mindspeed make changes specifications product descriptions time, without notice. Mindspeed makes commitment update information shall have responsibility whatsoever conflicts incompatibilities arising from future changes specifications product descriptions. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Mindspeed's Terms Conditions Sale such products, Mindspeed assumes liability whatsoever. THESE MATERIALS PROVIDED WITHOUT WARRANTY KIND, EITHER EXPRESS IMPLIED, RELATING SALE AND/OR MINDSPEED PRODUCTS INCLUDING LIABILITY WARRANTIES RELATING FITNESS PARTICULAR PURPOSE, CONSEQUENTIAL INCIDENTAL DAMAGES, MERCHANTABILITY, INFRINGEMENT PATENT, COPYRIGHT OTHER INTELLECTUAL PROPERTY RIGHT. MINDSPEED FURTHER DOES WARRANT ACCURACY COMPLETENESS INFORMATION, TEXT, GRAPHICS OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. MINDSPEED SHALL LIABLE SPECIAL, INDIRECT, INCIDENTAL, CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES LOST PROFITS, WHICH RESULT FROM THESE MATERIALS. Mindspeed products intended medical, lifesaving life sustaining applications. Mindspeed customers using selling Mindspeed products such applications their risk agree fully indemnify Mindspeed damages resulting from such improper sale. following trademarks Conexant Systems, Inc.: Mindspeed TechnologiesTM, Mindspeedlogo, "Build First"TM. Product names services listed this publication identification purposes only, trademarks third parties. Third-party brands names property their respective owners. additional disclaimer information, please consult Mindspeed Technologies Legal Information posted www.mindspeed.com which incorporated reference.
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Advance Information
This document contains information product under development. parametric information contains target parameters that subject change.
M28335 Twelve Port T3/E3/STS-1 Line Interface Unit
M28335 12-channel, T3/E3/STS-1 Line Interface Unit (LIU). configured parallel microprocessor interface hard-wired connections. Each channel independent equalizer receive side requiring user configuration. Also, each channel programmable transmit pulse shaper that ensure that cross-connect pulse mask requirement transmit cable lengths feet. M28335 provides user economies scale Metro-optical access switch applications where STS-1 channels aggregated into OC12/ OC48 connections single line card. Significant elimination external components achieved including twelve independent transceivers package. line interface reduced coupling transformers, termination resistors, supply bypass capacitors.
Distinguishing Features
XOE1 LBO1 E3MODE1 PDB1 TPOS TNEG TCLK TAIS Monitor TMONP TMONM TXMON TMONTST REFCLK
PDATA NDATA
PDATA/ NDATA Encoder TCLK Pulse Shaper Line Driver
TLINEP TLINEM/N
used data transceiver over maximum feet type 734/728 coaxial cable equivalent onpremise environment Programmable pulse filtering meet cross-connect pulse masks (ANSI T1.1021993) SRAM-like 8-bit parallel microprocessor interface Serial Peripheral Interface (SPI) support Meets jitter specifications Bellcore GR499, GR253, TBR24 (with external JAT) Alarms coding violation loss signal Full diagnostic loopback capability Uses minimum external components Compatible with ITU-T G.703, G.823, G.775 Independent power-down mode channel Easily interfaced T3/E3 framer (CX28342/3/4/6/8, CN8330 CX28365) Selectable B3ZS/HDB3 encoding/decoding Superior input receiver sensitivity (<25 peak) Transmit monitor inputs faulty transmit shorted output Programmable RLOS threshold
RLOOP1 LLOOP1
Data
ENDECDIS1
Physical Characteristics
RPOS RNEG RCLK RLOS
Decoder
Clock/ DATCLK Data RLOSMAX RLOSTHR Recovery RLOSMDIS
Receiver
RLINEP RLINEM/N REQH1
ALOS
TBGA package Single power supply maximum power dissipation temperature range V-tolerant pins digital pins
Applications
BDATA/PORTMODE[1:8] BADD/PORTMODE[9:12] BWR~/LMODE0 BOE~/LMODE1 BCS~/GRLOOP BINTR~ SDIN SDOUT
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Control Latches/ Command DEMUX
ENCDECDIS[1:12] LBO[1:12] PD~[1:12] RLOOP[1:12] LLOOP[1:12] REQH[1:12] E3[1:12] XOE[1:12] RLOSMAX[1:12] RLOSMDIS[1:12]
Digital cross-connect systems High-end routers Multi-service Aswitches Optical add-drop multiplexers Metro-optical Access Switches
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M28335
M28335 Evaluation Module (EVM)
NRZTX DATA NRZRX DATA
B3ZS/HDB3 analog B3ZS/HDB3 analog
M28335
CH12 NRZRX DATA Loss Signal Code Violation
NRZTX DATA
B3ZS/HDB3 analog CH12 B3ZS/HDB3 analog Clock Input Control
101487_002
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Contents
Figures Tables
CHAPTER
Description.
Assignments Logic Diagrams 1-18
Functional Description.
Overview Configuration Control 2.2.1 Hardware Mode. 2.2.2 Mode 2.2.3 Serial Mode. Transmitter 2.3.1 B3ZS/HDB3 Encoder 2.3.2 Pulse Shaper 2.3.3 Line Driver 2.3.3.1 Transmit Pulse Mask Templates 2.3.4 Alarm Indication Signal (AIS) Generator 2-10 2.3.5 Transmit Monitor Block. 2-11 2.3.6 Jitter Generation (Intrinsic) 2-11 Receiver. 2-12 2.4.1 Receive Sensitivity 2-12 2.4.2 AGC/VGA Block 2-12 2.4.3 Receive Equalizer 2-12 2.4.4 Clock Recovery Circuit 2-12 2.4.5 Loss Signal (LOS) Detector 2-13 2.4.6 B3ZS/HDB3 Decoder With Bipolar Violation Detector 2-13 2.4.7 Data Squelching 2-14
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M28335
Jitter Tolerance 2.5.1 Jitter Transfer Additional M28335 Functions 2.6.1 Bias Generator 2.6.2 External Reset 2.6.3 Power-On Reset (POR) 2.6.4 Interrupt 2.6.5 Loopback Multiplexers (MUXes) Mechanical Specifications Electrical Characteristics 2.8.1 Absolute Maximum Ratings 2.8.2 Recommended Operating Conditions Characteristics 2.10 Characteristics
2-14 2-16 2-17 2-17 2-17 2-17 2-18 2-18 2-19 2-20 2-20 2-20 2-21 2-22
Registers
Address Global Register 0x0-Global Control Register (GC) Port Registers 0x1-0xC-Portn Control Register (PCn) Interrupt Status Registers 0x14-RLOS Interrupt Status Register (RISR1) 0x15-RLOS Interrupt Status Register (RISR2) 0x16-TLOS Interrupt Status Register (TISR1) 0x17-TLOS Interrupt Status Register (TISR2) Interrupt Enable Registers 0x18-RLOS Interrupt Enable Register (RIER1) 0x19-RLOS Interrupt Enable Register (RIER2) 0x1A-TLOS Interrupt Enable Register (TIER1) 0x1B-TLOS Interrupt Enable Register (TIER2) RLOS Threshold Control Registers 0x0D-RMTR1 (RLOS Threshold Register 0x0E-RMTR2 (RLOS Threshold Register RLOS Data Squelch Disable Registers. 0x1C-RDR1 (RLOS Disable Register 0x1D-RDR2 (RLOS Disable Register
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M28335
Applications.
Line Interface Example Interface Example CX28365 Mode Interface Example CX28365 Hardware Mode Serial Mode Interface Example Design Considerations M28335 4.5.1 Power Supply Ground Plane. 4.5.2 Component Placement 4.5.2.1 VBIAS Resistor 4.5.2.2 Decoupling 4.5.2.3 Termination Resistors Capacitor. 4.5.3 Impedance Matching. 4.5.4 Other Passive Parts. 4.5.5 IBIS Models 4.5.6 Recommended Vendors
APPENDIX
Applicable Standards
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M28335
viii
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Figures
Figure 1-1. Figure 1-2. Figure 1-3. Figure 2-1. Figure 2-2. Figure 2-3. Figure 2-4. Figure 2-5. Figure 2-6. Figure 2-7. Figure 2-8. Figure 2-9. Figure 2-10. Figure 2-11. Figure 2-12. Figure 2-13. Figure 2-14. Figure 2-15. Figure 2-16. Figure 4-1. Figure 4-2. Figure 4-3. Figure 4-4.
Hardware Mode Logic Diagram 1-18 Mode Logic Diagram 1-19 Serial Mode Logic Diagram 1-20 Typical Application Single M28335 Channel Host Serial Port Signals Pulse Shaper Pulse Power Measurement Points Transmit Pulse Mask Rates Transmit Pulse Mask STS-1 Rates Transmit Pulse Mask Rate 2-10 Signal 2-11 Minimum Jitter Tolerance Requirement 2-15 Maximum Jitter Transfer Curve Requirement 2-16 M28335 Mechanical Drawing TBGA)-Dimensions 2-19 Timing Diagram 2-22 Mode Read Timing 2-23 Mode Write Timing 2-24 Serial Mode Register Read (see Note below) 2-25 Serial Mode Register Write (see Note below) 2-25 Line Interface Example Interface CX28365 Mode Interface CX28365 Hardware Mode Serial Mode Interface Example
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Figures
M28335
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Tables
Table 1-1. Table 2-1. Table 2-2. Table 2-3. Table 2-4. Table 2-5. Table 2-6. Table 2-7. Table 2-8. Table 2-9. Table 2-10. Table 2-11. Table 3-1. Table 3-2.
M28335 Definitions Redefinition Port Configuration Hardware Mode Transmit Template Specifications STS-1 Transmit Template Specifications Absolute Maximum Ratings 2-20 Recommended Operating Conditions. 2-20 Characteristics 2-21 Characteristics (Logic Timing) 2-22 Mode Timing-Read Cycles 2-23 Mode Timing-Write Cycles 2-24 Serial Mode Timing 2-25 Register Address RLOS Threshold Control Bits
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Tables
M28335
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Description
Assignments
Table illustrates M28335 descriptions. Input/Output (I/O) column coded follows: Input Output Bidirectional Power
NOTE:
digital inputs outputs contain pull-down resistors.
When channel disabled, receive transmit analog circuitry powers down. Analog inputs (RLINE) ignored analog outputs (TLINE) high impedance. Digital inputs powered-down channel still active, ignored. Overall noise device lowered driving digital inputs powered-down channel.
NOTE:
When channel reverted from power-down normal operation, TLINE pins impedance ground driven more than forward-bias diode voltage (0.7 below ground. Additionally, driving TLINE, forward-bias diode voltage above pin, creates impedance path from TLINE pin. Otherwise, TLINE pins high impedance.
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Description
M28335
Table 1-1. M28335 Definitions Signal Name Description Coaxial Line Pins
AF33 AF34 AC32 AC33 RLINE1P RLINE1M RLINE2P RLINE2M RLINE3P RLINE3M RLINE4P RLINE4M RLINE5P RLINE5M RLINE6P RLINE6M RLINE7P RLINE7M RLINE8P RLINE8M RLINE9P RLINE9M RLINE10P RLINE10M RLINE11P RLINE11M RLINE12P RLINE12M positive receive data negative receive data positive receive data negative receive data positive receive data negative receive data positive receive data negative receive data positive receive data negative receive data positive receive data negative receive data positive receive data negative receive data positive receive data negative receive data positive receive data negative receive data positive receive data negative receive data positive receive data negative receive data positive receive data negative receive data Differential inputs each channel from respective receive coax line. expects balanced differential inputs, usually achieved using transformer. inputs internally biased
I/O/P
Notes
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M28335
Description
Table 1-1. M28335 Definitions
AG31 AG32 AD31 AD32 AA31 AA32
Signal Name
TLINE1P TLINE1M TLINE2P TLINE2M TLINE3P TLINE3M TLINE4P TLINE4M TLINE5P TLINE5M TLINE6P TLINE6M TLINE7P TLINE7M TLINE8P TLINE8M TLINE9P TLINE9M TLINE10P TLINE10M TLINE11P TLINE11M TLINE12P TLINE12M
Description
positive transmit data negative transmit data positive transmit data negative transmit data positive transmit data negative transmit data positive transmit data negative transmit data positive transmit data negative transmit data positive transmit data negative transmit data positive transmit data negative transmit data positive transmit data negative transmit data positive transmit data negative transmit data positive transmit data negative transmit data positive transmit data negative transmit data positive transmit data negative transmit data
I/O/P
Notes
Differential, coax-driver balanced outputs pulse-shaped B3ZS/HDB3 encoded waveforms each channel. These pins should connected primary side transformer through backmatch resistors.
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Description
M28335
Table 1-1. M28335 Definitions Signal Name Description Digital Data Pins
AN27 AM27 AL23 AP24 AN20 AM20 AM10 AL10 AM14 AL14 AP27 AM23 AP20 AP10 AN14 RPOS1/RNRZ1 RNEG1/RLCV1 RPOS2/RNRZ2 RNEG2/RLCV2 RPOS3/RNRZ3 RNEG3/RLCV3 RPOS4/RNRZ4 RNEG4/RLCV4 RPOS5/RNRZ5 RNEG5/RLCV5 RPOS6/RNRZ6 RNEG6/RLCV6 RPOS7/RNRZ7 RNEG7/RLCV7 RPOS8/RNRZ8 RNEG8/RLCV8 RPOS9/RNRZ9 RNEG9/RLCV9 receive positive rail data receive negative rail line code violation receive positive rail data receive negative rail line code violation receive positive rail data receive negative rail line code violation receive positive rail data receive negative rail line code violation receive positive rail data receive negative rail line code violation receive positive rail data receive negative rail line code violation receive positive rail data receive negative rail line code violation receive positive rail data receive negative rail line code violation receive positive rail data receive negative rail line code violation Recovered clock each channel receiver, intended strobing corresponding RDAT into following framer logic. When ENDECDIS these outputs decoded data (RNRZ) line code violation (RLCV). line code violation indicated when RLCV notes ENDECDIS Chapter 3.0. Resynchronized receive data intended strobed corresponding RCLK. When ENDECDIS these outputs positive negative data (RPOS RNEG).
I/O/P
Notes
RPOS10/RNRZ10 receive positive rail data RNEG10/RLCV10 receive negative rail line code violation RPOS11/RNRZ11 receive positive rail data RNEG11/RLCV11 receive negative rail line code violation RPOS12/RNRZ12 receive positive rail data RNEG12/RLCV12 receive negative rail line code violation RCLK1 RCLK2 RCLK3 RCLK4 RCLK5 RCLK6 RCLK7 RCLK8 RCLK9 RCLK10 RCLK11 RCLK12 Receive Clock Receive Clock Receive Clock Receive Clock Receive Clock Receive Clock Receive Clock Receive Clock Receive Clock Receive Clock Ch10 Receive Clock Ch11 Receive Clock Ch12
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M28335
Description
Table 1-1. M28335 Definitions
AP25 AM25 AL21 AP22 AN18 AM18 AP12 AN12 AL16 AM16 AL24 AM21 AP18 AL13 AP16
Signal Name
TPOS1 TNEG1/NC1 TPOS2 TNEG2/NC2 TPOS3 TNEG3/NC3 TPOS4 TNEG4/NC4 TPOS5 TNEG5/NC5 TPOS6 TNEG6/NC6 TPOS7 TNEG7/NC7 TPOS8 TNEG8/NC8 TPOS9 TNEG9/NC9 TPOS10 TNEG10/NC10 TPOS11 TNEG11/NC11 TPOS12 TNEG12/NC12 TCLK1 TCLK2 TCLK3 TCLK4 TCLK5 TCLK6 TCLK7 TCLK8 TCLK9 TCLK10 TCLK11 TCLK12
Description
transmit Positive rail data transmit negative rail connect data transmit Positive rail data transmit negative rail connect data transmit Positive rail data transmit negative rail connect data transmit Positive rail data transmit negative rail connect data transmit Positive rail data transmit negative rail connect data transmit Positive rail data transmit negative rail connect data transmit Positive rail data transmit negative rail connect data transmit Positive rail data transmit negative rail connect data transmit Positive rail data transmit negative rail connect data transmit Positive rail data transmit negative rail connect data transmit Positive rail data transmit negative rail connect data transmit Positive rail data transmit negative rail connect data Transmit Clock Transmit Clock Transmit Clock Transmit Clock Transmit Clock Transmit Clock Transmit Clock Transmit Clock Transmit Clock Transmit Clock Transmit Clock Transmit Clock
I/O/P
Notes
Synchronized transmit data intended strobed corresponding TCLK. When ENDECDIS these inputs expected positive negative data (TPOS TNEG). When ENDECDIS these inputs expected uncoded data (TNRZ) connects (NC). notes ENDECDIS Chapter 3.0.
Transmit clock input strobing with transmit data into M28335.
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Description
M28335
Table 1-1. M28335 Definitions
AM26 AN23 AL19 AM11 AL15
Signal Name
RLOS1 RLOS2 RLOS3 RLOS4 RLOS5 RLOS6 RLOS7 RLOS8 RLOS9 RLOS10 RLOS11 RLOS12
Description
Loss Signal Loss Signal Loss Signal Loss Signal Loss Signal Loss Signal Loss Signal Loss Signal Loss Signal Loss Signal Loss Signal Loss Signal
I/O/P
Notes
Loss Signal (LOS) indication each channel, determined insufficient pulse density. Signal loss detected when RLOS will asserted when occur row, deasserted when pulse density between (DS3/STS-1) (i.e., density).
Control Signal
AN24 AP21 AP17 AP13 AL17 TAIS1 TAIS2 TAIS3 TAIS4 TAIS5 TAIS6 TAIS7 TAIS8 TAIS9 TAIS10 TAIS11 TAIS12 Transmit mode enable Transmit mode enable Transmit mode enable Transmit mode enable Transmit mode enable Transmit mode enable Transmit mode enable Transmit mode enable Transmit mode enable Transmit mode enable Transmit mode enable Transmit mode enable Transmission Alarm Indication Signal (AIS) given channel. Replace transmit data with signal. form supported alternating (+1, Looping takes precedence over AIS. mode enabled mode disabled
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M28335
Description
Table 1-1. M28335 Definitions Signal Name Description I/O/P Notes
Mode/Hardware Mode/Serial Mode Control Signals
BDATA0 /PORTMODE1 Data 0/PORTMODE1/SDIN Hardware mode (Pins BMODE[1:0] 00), pins defined PORTMODE[8:1], which select configurations Port[8:1]. mode (Pins BMODE[1:0] 10), pins defined eight bidirectional used transferring data from internal registers which configurations ports. Serial mode (Pins BMODE[1:0] 11), SDIN serial data input from Serial Master device. Serial mode (Pins BMODE[1:0] 11), SDOUT serial data output Serial Master device.
/SDIN
BDATA1 /PORTMODE2 Data 1/PORTMODE2/SDOUT
/SDOUT
BDATA2 /PORTMODE3 BDATA3 /PORTMODE4 BDATA4 /PORTMODE5 BDATA5 /PORTMODE6 BDATA6 /PORTMODE7 BDATA7 /PORTMODE8 BADD0 /PORTMODE9 BADD1 /PORTMODE10 BADD2 /PORTMODE11 BADD3 /PORTMODE12 BADDR4 /TMONTST Data 2/PORTMODE3 Data 3/PORTMODE4 Data 4/PORTMODE5 Data 5/PORTMODE6 Data 6/PORTMODE7 Data 7/PORTMODE8 Address 0/PORTMODE9 Address 1/PORTMODE10 Address 2/PORTMODE11 Address 3/PORTMODE12 Address 4/TX Monitor Test
Hardware mode (BMODE pins tied low), pins defined PORTMODE[12:9] which select configurations Port[12:9]. mode (BMODE tied high), pins defined four address lines identify internal register read/write data transfer cycle.
Hardware mode (BMODE pins tied low), defined monitor test which, when driven high, asserts TLOS outputs. This used test board level functionality downstream from TLOS outputs. mode (BMODE PINs tied high), defined address internal register access. Hardware mode (BMODE pins tied low), defined pins LMODE0 LMODE1 which common control lines together with PORTMODEx lines control configuration individual ports. mode (BMODE PINs tied high), indicates write cycle when low.
BWR~/LMODE1
Data Write Strobe /LMODE1
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Description
M28335
Table 1-1. M28335 Definitions
Signal Name
BOE~/LMODE0 /SCLK
Description
Data Output Enable /LMODE0
I/O/P
Notes
Hardware mode (BMODE pins tied low), defined pins LMODE0 LMODE1 which common control lines together with PORTMODEx lines control configuration individual ports. mode (BMODE PINs tied high), enables BDATA output during read operation when active low. When high, BDATA[7:0] high impedance state. serial mode (BMODE[1:0] 11), SCLK serial clock input from serial master device.
BCS~/GRLOOP
Chip select /GRLOOP
Hardware mode (BMODE pins tied low), defined GRLOOP (global remote loopback). twelve ports placed remote loopback when this tied high. normal operations, GRLOOP should tied low. mode (BMODE tied high), serves chip select. enables read/write operation when active low. When high, ends current read/write cycle returns BDATA[7:0] high impedance state.
BMODE0 BMODE1
Mode select Mode select
Mode Select pins control device configuration mode follows: BMODE1 BMODE0 Mode Operation Hardware Mode Reserved (for factory test) Mode Serial Mode Hardware mode (Pins BMODE[1:0] 00), control signals redefined configuration each channel determined associated dedicated PORTMODE pins. mode, internal registers that control operation each port accessed through SRAM-like parallel port. Serial mode, Control signals redefined support SPI.
BINTR~
Interrupt
Open drain active output signifies more pending alarm condition detected INTEN (bit address set.
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M28335
Description
Table 1-1. M28335 Definitions Signal Name Description Miscellaneous
AN26 AL22 AM19 AN11 AM15 AN29 REFCLK1 REFCLK2 REFCLK3 REFCLK4 REFCLK5 REFCLK6 REFCLK7 REFCLK8 REFCLK9 REFCLK10 REFCLK11 REFCLK12 RBIASA RBIASB RBIASC RBIASD RESET Reference Clock Reference Clock Reference Clock Reference Clock Reference Clock Reference Clock Reference Clock Reference Clock Reference Clock Reference Clock Reference Clock Reference Clock Bias Resistor Bias Resistor Bias Resistor Bias Resistor Reset Global Power Down Asynchronous reset (reset entire device). Power down (Static testing). Power down disable Power down active Four 12.1 resistors tied from each these pins ground provide current reference.(2) Reference clock from off-chip. This clock should following: rate (34.368 MHz) rate (44.736 MHz) STS-1 rate (51.84 MHz) clock rate should correspond mode operation chosen channel.
I/O/P
Notes
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Description
M28335
Table 1-1. M28335 Definitions
AH32 AG33 AE34 AD33 AB32 AA34 AL25 AM22 AL18 AM12 AP15
Signal Name
TMON1P TMON1M TMON2P TMON2M TMON3P TMON3M TMON4P TMON4M TMON5P TMON5M TMON6P TMON6M TMON7P TMON7M TMON8P TMON8M TMON9P TMON9M TMON10P TMON10M TMON11P TMON11M TMON12P TMON12M TLOS1 TLOS2 TLOS3 TLOS4 TLOS5 TLOS6 TLOS7 TLOS8 TLOS9 TLOS10 TLOS11 TLOS12
Description
transmit monitor positive input transmit monitor negative input transmit monitor positive input transmit monitor negative input transmit monitor positive input transmit monitor negative input transmit monitor positive input transmit monitor negative input transmit monitor positive input transmit monitor negative input transmit monitor positive input transmit monitor negative input transmit monitor positive input transmit monitor negative input transmit monitor positive input transmit monitor negative input transmit monitor positive input transmit monitor negative input transmit monitor positive input transmit monitor negative input transmit monitor positive input transmit monitor negative input transmit monitor positive input transmit monitor negative input loss signal output loss signal output loss signal output loss signal output loss signal output loss signal output loss signal output loss signal output loss signal output loss signal output loss signal output loss signal output
I/O/P
Notes
Transmit monitor input pins normally tied their respective transmit line outputs, i.e., (TMON1P TLINE1P TMON1M TLINE1M). Loss signal outputs active high when monitor inputs detect signal TCLK periods. monitor test asserts TLOS outputs when TMONTST high. This used test board level functionality downstream from TLOS outputs.
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M28335
Description
Table 1-1. M28335 Definitions
C28, AP28, AN6, D28, AL27, AP6,
Signal Name
FAC_TEST Test pins.
Description
I/O/P
Notes
factory test, leave unconnected.
Power/Ground
AF31 AD34 AH31 AE32 AB31 TVDD1 TVDD2 TVDD3 TVDD4 TVDD5 TVDD6 TVDD7 TVDD8 TVDD9 TVDD10 TVDD11 TVDD12 TVSS1 TVSS2 TVSS3 TVSS4 TVSS5 TVSS6 TVSS7 TVSS8 TVSS9 TVSS10 TVSS11 TVSS12 Power Power Power Power Power Power Power Power Power Power Power Power Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground pins transmit circuitry channel. Power pins transmit circuitry channel (3.3
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1-11
Description
M28335
Table 1-1. M28335 Definitions
AF32 AC31 AE31 AC34 AM28
Signal Name
RVDD1 RVDD2 RVDD3 RVDD4 RVDD5 RVDD6 RVDD7 RVDD8 RVDD9 RVDD10 RVDD11 RVDD12 RVSS1 RVSS2 RVSS3 RVSS4 RVSS5 RVSS6 RVSS7 RVSS8 RVSS9 RVSS10 RVSS11 RVSS12 VGGA VGGB VGGC VGGD Power Power Power Power Power Power Power Power Power Power Power Power Ground Ground Ground Ground Ground Ground Ground Ground Ground
Description
I/O/P
Notes
Power pins receive circuitry channel (3.3 Connect power.
Ground pins receive circuitry channel. Connect ground.
Ground Ground Ground V/3.3
V/3.3 pin(1) V/3.3 pin(1) V/3.3 pin(1)
supply V-tolerant, digital diodes. static power drawn from pin.
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M28335
Description
Table 1-1. M28335 Definitions
E10, E14, E18, E22, E26, F30, K30, P30, V30, AA5, AB30, AE5, AF30, AJ5, AK4, AK9, AK13, AK17, AK21, AK25, AK29, AL30
Signal Name
DVDD Power
Description
I/O/P
Notes
Connect power.
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1-13
Description
M28335
Table 1-1. M28335 Definitions
A13, A18, A22, A28, A30, A31, A32, A33, A34, B10, B11, B13, B16, B17, B19, B22, B25, B28, B29, B30, B31, B32, B33, B34, C10, C12, C17, C18, C26, C30, C31, C32, C33, C34, D15, D17, D18, D19, D24, D29, D30, D31, D32, D33, D34, E11, E12, E13, E15, E16, E17, E19, E20, E21, E23, E24, E25, E27, E28, E29, E30, E31, E32, E33, F32, G30, G32, G33, G34,
Signal Name
Description
Ground
I/O/P
Connect ground.
Notes
(List continued next page.)
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M28335
Description
Table 1-1. M28335 Definitions
H30, J30, J34, K33, K34, L30, L31, L33, M30, M31, N30, N33, P33, R30, T30, T33, U30, W30, W31, W33, Y30, AA30, AA33, AB1, AB2, AB5, AB33, AB34, AC2, AC5, AC30, AD4, AD5, AD30, AE2, AE30, AE33, AF5, AG1, AG5, AG30, AG34, AH1, AH2, AH5, AH30, AH33, AH34, AJ3, AJ4, AJ30, AJ31, AJ32, AJ33, AJ34, AK1, AK2, AK3,
Signal Name
Description
Ground
I/O/P
Connect ground.
Notes
(List continued next page.)
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1-15
Description
M28335
Table 1-1. M28335 Definitions
AK5, AK6, AK7, AK8, AK10, AK11, AK12, AK14, AK15, AK16, AK18, AK19, AK20, AK22, AK23, AK24, AK26, AK27, AK28, AK30, AK31, AK32, AK33, AK34, AL1, AL2, AL3, AL4, AL5, AL11, AL12, AL20, AL26, AL28, AL29, AL31, AL32, AL33, AL34, AM1, AM2, AM3, AM4, AM5, AM13, AM17, AM24, AM29, AM30, AM31, AM32, AM33, AM34, AN1, AN2, AN3, AN4, AN5, AN7, AN10, AN13,
Signal Name
Description
Ground
I/O/P
Connect ground.
Notes
(List continued next page.)
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M28335
Description
Table 1-1. M28335 Definitions
AN15, AN16, AN17, AN19, AN21, AN22, AN25, AN28, AN30, AN31, AN32, AN33, AN34, AP1, AP2, AP3, AP4, AP5, AP9, AP11, AP14, AP19, AP23, AP26, AP29, AP30, AP31, AP32, AP33, AP34
GENERAL NOTE:
Signal Name
Description
Ground
I/O/P
Connect ground.
Notes
This should connected all-3.3 design. Placing capacitor from this ground result instabilities. digital input pins contain pull-down resistor from input GND.
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Description
M28335
Logic Diagrams
Figure 1-1. Hardware Mode Logic Diagram
Port Mode Line Mode Global Remote Loopback Monitor Test
PORTMODE[1:12] LMODE[0:1] GRLOOP TMONTST BMODE1 BMODE0
Hardware Mode Configuration
Postive Receive Data Negative Receive Data RLINE[1:12]P RLINE[1:12]M RPOS[1:12]//RNRZ[1:12] NPOS[1:12]/RLCV[1:12] RCLK[1:12] RLOS[1:12] Receive Positive Rail/NRZ Data Receive Negative Rail/Line Code Violation Receive Clock Receive Loss Data
Receiver
Transmit Positive Rail/NRZ data Trasmit Negative Rail/NC Transmit Monitor Postive Input Transmit Monitor Negative Input Transmit Clock Transmit mode Enable
TPOS[1:12] TNEG[1:12]/NC[1:12] TMON[1:12]P TMON[1:12]M TCLK[1:12] Transmitter TAIS[1:12] REFCLK[1:12] RESET
TLINE[1:12]P TLINE[1:12]M TLOS[1:12]
Positive Transmit Data Negative Transmit Data Transmit Loss Data
Reference Clock Reset Global Power Down
RBIASA RBAISB RBAISC RBAISD
Bias Resistor Bias Resistor Bias Resistor Bias Resistor
Miscellaneous
Input, Output, Programmable I/O; controls located
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Description
Figure 1-2. Mode Logic Diagram
Data Address Chip Select Data Write Strobe Data Output Enable
BDATA[0:7] BADD[0:4] BCS~ BWR~ BOE~ BMODE1 BMODE0
BINTR~
Interrupt
Mode Interface
RPOS[1:12]//RNRZ[1:12] NPOS[1:12]/RLCV[1:12] RCLK[1:12] RLOS[1:12] Receive Positive Rail/NRZ Data Receive Negative Rail/Line Code Violation Receive Clock Receive Loss Data
Postive Receive Data Negative Receive Data
RLINE[1:12]P RLINE[1:12]M
Receiver
Transmit Positive Rail/NRZ data Trasmit Negative Rail/NC Transmit Monitor Postive Input Transmit Monitor Negative Input Transmit Clock Transmit mode Enable
TPOS[1:12] TNEG[1:12]/NC[1:12] TMON[1:12]P TMON[1:12]M TCLK[1:12] Transmitter TAIS[1:12] REFCLK[1:12] RESET
TLINE[1:12]P TLINE[1:12]M TLOS[1:12]
Positive Transmit Data Negative Transmit Data Transmit Loss Data
Reference Clock Reset Global Power Down
RBIASA RBAISB RBAISC RBAISD
Bias Resistor Bias Resistor Bias Resistor Bias Resistor
Miscellaneous
Input, Output, Programmable I/O; controls located
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Description
M28335
Figure 1-3. Serial Mode Logic Diagram
Chip Select Serial Clock Serial Data
BCS~ SCLK SDIN
SDOUT BINTR~
Serial Data Output Interrupt
BMODE1 BMODE0
Serial Peripheral Interface
Postive Receive Data Negative Receive Data RLINE[1:12]P RLINE[1:12]M RPOS[1:12]//RNRZ[1:12] NPOS[1:12]/RLCV[1:12] RCLK[1:12] RLOS[1:12] Receive Positive Rail/NRZ Data Receive Negative Rail/Line Code Violation Receive Clock Receive Loss Data
Receiver
Transmit Positive Rail/NRZ data Trasmit Negative Rail/NC Transmit Monitor Postive Input Transmit Monitor Negative Input Transmit Clock Transmit mode Enable
TPOS[1:12] TNEG[1:12]/NC[1:12] TMON[1:12]P TMON[1:12]M TCLK[1:12] TAIS[1:12] Transmitter REFCLK[1:12] RESET
TLINE[1:12]P TLINE[1:12]M TLOS[1:12]
Positive Transmit Data Negative Transmit Data Transmit Loss Data
Reference Clock Reset Global Power Down
RBIASA RBAISB RBAISC RBAISD
Bias Resistor Bias Resistor Bias Resistor Bias Resistor
Miscellaneous
Input, Output, Programmable I/O; controls located
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Functional Description
Overview
M28335 12-port E3/DS3/STS-1 Line Interface Unit (LIU). physical layer interface between data framer other terminal-side equipment) electrical cable used data transmission. M28335 consists independent data transceivers that operate over type 734/728 coaxial cable rates 34.368 Mbps (E3), 44.736 Mbps (DS3), 51.84 Mbps (STS-1). transmit side takes already-encoded dual rail input encodes into B3ZS (for DS3/STS-1) HDB3 (for analog waveforms transmitted over coaxial cable. receiver side takes attenuated distorted analog receive signal equalizes, slices, resynchronizes signal before decoding output sending nondecoded dual rail. architecture M28335 includes following internal functions each channel: Transmitter: B3ZS/HDB3 encoder pulse shaper line driver Alarm Indication Signal (AIS) insertion transmit monitor Receiver: receive sensitivity Automatic Gain Control (AGC) receive equalizer Clock Recovery circuit Loss Signal (LOS) detector B3ZS/HDB3 decoder with bipolar violation detector data squelching Additional Functions: bias generator power-on reset loopback MUXes
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M28335
addition, each channel ability perform remote local loopbacks. Figure illustrates typical application using M28335 channel. Each port controlled configured mode through parallel port hardware mode through dedicated pins. M28335 used data transceiver over coaxial cable that feet long feet from DSX) on-premise environment within public private networks that these data rates.
Figure 2-1. Typical Application Single M28335 Channel
0-450 COAX (type 734/728)
0-450 COAX (type 734/728)
0-450 COAX (type 734/728)
0-450 COAX (type 734/728)
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Functional Description
2.2.1
Configuration Control
Hardware Mode
When BMODE pins tied connected, device operates Hardware mode where control signals redefined configuration each channel determined associated dedicated PORTMODE pins. redefinition follows:
Table 2-1. Redefinition
Hardware Mode (BMODE
PORTMODE1 PORTMODE2 PORTMODE3 PORTMODE4 PORTMODE5 PORTMODE6 PORTMODE7 PORTMODE8 PORTMODE9 PORTMODE10 PORTMODE11 PORTMODE12 TMONTST LMODE0 LMODE1 GRLOOP
Mode (BMODE
BDATA0 BDATA1 BDATA2 BDATA3 BDATA4 BDATA5 BDATA6 BDATA7 BADD0 BADD1 BADD2 BADD3 BADD4 BOE~ BWR~ BCS~
Serial Mode (BMODE
SDIN SDOUT SCLK BCS~
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Functional Description
M28335
Pins LMODE0 LMODE1 common control lines. Together with PORTMODEx lines, they control configuration individual ports. device decodes three lines sets internal registers that determine configuration port according Table 2-2.
Table 2-2. Port Configuration Hardware Mode Pins PORTMODEn
Internal Registers Description E3MODE
LMODE[1:0]
REQH
ENDECDIS
DS3/STS-1, square receive pulse (low eq), ENDECDIS DS3/STS-1, square receive pulse (low eq), ENDECDIS DS3/STS-1, normal receive pulse (high eq), ENDECDIS DS3/STS-1, normal receive pulse (high ENDECDIS off, mode, encode/decode mode, encode/decode (same DS3, square, ENDECDIS off, off) DS3/STS-1, normal receive pulse (high eq), ENDECDIS DS3/STS-1, normal receive pulse (high ENDECDIS off,
Group Controls Global (GRLOOP) controls remote loopback. When GRLOOP tied high, twelve ports placed remote loopback. normal operations, GRLOOP should tied low.
NOTE:
real-time status alarm signals RLOS TLOS available dedicated output pins regardless BMODE state read/write cycle.
2.2.2
Mode
When BMODE1 tied high BMODE0 tied low, device operates mode. mode, internal registers that control operation each port accessed through SRAM like parallel port. redefinition follows: BDATA[7:0] BADDR[4:0] BWR~ BOE~ BCS~ Eight-bit bidirectional data Five-bit address Write strobe BDATA output enable BDATA chip select
Chapter definition internal registers.
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Functional Description
2.2.3
Serial Mode
M28335 supports Serial Peripheral Interface (SPI) device control configuration. four-wire, slave interface which allows host processor framer with compatible master serial port communicate with device. This interface allows host control query M28335 status writing reading internal registers. 8-bit register written SDIN read from SDOUT clock rate determined SCLK. serial port enabled pulling chip select pin, active (low) during read write cycles. Figure serial peripheral interface port signals. serial interface uses 16-bit process each write read operation. During write read operation, 8-bit control word consisting read/write control 7-bit register address (A[6:0], where A[4:0] used with always zero), transmitted SDIN pin. operation write operation (R/W 8-bit register data (D[7:0]) byte follows address SDIN pin. This data received M28335 stored addressed register. operation read operation (R/W M28335 outputs addressed register contents SDOUT pin. signal input SDIN sampled SCLK falling edge, data output SDOUT changes SCLK rising edge.
Figure 2-2. Host Serial Port Signals
Read Timing
SCLK
Address/Control Byte
Register Data Byte
Write Timing
SCLK
Address/Control Byte
Register Data Byte
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Functional Description
M28335
Transmitter
This section describes detailed operation various blocks M28335 transmitter.
2.3.1
B3ZS/HDB3 Encoder
ENDECDIS E3MODE pins configure encoder mode. When ENDECDIS encoder receiving non-encoded Nonreturn Zero (NRZ) data TNRZ (TPOS) alone, Connect (NC) (TNEG) ignored. Data encoded into representation three-level B3ZS (E3MODE HDB3 (E3MODE signal (conforming coding rules specified Appendix before going pulse shaper form binary signals representing positive negative three-level pulses. When ENDECDIS encoder disabled. encoder passes already-encoded data over TPOS (TNRZ) TNEG (NC) pulse shaper. transmit digital data clocked into chip rising TCLK edge, which must equal symbol rate (line rate). small delay added data provides certain amount negative data hold time.
2.3.2
Pulse Shaper
pulse shaper converts digital (clocked) positive negative pulses into single analog three-level Alternate Mark Inversion (AMI) pulse. pulses Return Zero (RZ) format, meaning that positive negative pulses have duration first half symbol period. rate (E3MODE pulse full-amplitude, square-shaped pulse with very little slope.
Figure 2-3. Pulse Shaper
Mode Pulse Pulse Shaper Pulse
Line Driver
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DS3/STS-1 rates, pulse-shaper block shapes transmit waveform reduces high-frequency energy content. This ensures that transmit pulse template cross-connect block, which follows 0-450 feet transmit-side coaxial cable.
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Functional Description
2.3.3
Line Driver
differential line driver takes filtered transmit waveform, increases proper level, drives into transmit magnetics. external discrete backmatching resistors line matching. driver presented with approximately differential load. Driver gain accounts gain loss back-matching resistors. Figure illustrates Pulse/Power template measurement points various data rates.
Figure 2-4. Pulse Power Measurement Points
Pulse/Power Template STS-1
0-450 COAX (type 734/728)
0-450 COAX (type 734/728)
Pulse/Power Template
0-450 COAX (type 734/728)
0-450 COAX (type 734/728)
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M28335
2.3.3.1
Transmit Pulse Mask Templates
Figure illustrates transmit pulse mask rates.
Figure 2-5. Transmit Pulse Mask Rates
Table 2-3. Transmit Template Specifications Time Axis Range (UI) Upper Curve
-0.85 -0.68 -0.68 0.36 0.36 0.03 0.03 2)(1 0.34)]} 0.08 0.407 -1.84(T 0.36)
Normalized Amplitude Equation
Lower Curve
-0.85 -0.36 -0.36 0.36 0.36 -0.03 -0.03 2)(1 0.18)]} -0.03
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Figure 2-6. Transmit Pulse Mask STS-1 Rates
Transmit Pulse Mask STS-1 Rates
Normalized Pulse Amplitude
-0.2
Normalized Symbol Time
101487_013
Table 2-4. STS-1 Transmit Template Specifications Time Axis Range Upper Curve
-0.85 -0.68 -0.68 0.26 0.26 0.03 0.03 2)(1 0.34)]} 0.61 -2.4(T 0.26)
Normalized Amplitude Equation
Lower Curve
-0.85 -0.38 -0.38 0.36 0.36 -0.03 -0.03 2)(1 0.18)]} -0.03
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Figure 2-7. Transmit Pulse Mask Rate
Volts Normalized 8.65 12.1 14.55
24.5 29.1 Time
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2.3.4
Alarm Indication Signal (AIS) Generator
When TAIS asserted, replaces transmit data TPOS TNEG. type signal (all supported. three-level signal form, this continuously alternating positive negative pulse stream, transmit data were continuous string logical Figure illustrates signal. TAIS same data latency data pins used replace single symbols within data stream. When encoder disabled (ENDECDIS TAIS mode maintains proper phase, based polarity last received. signal follows same path data during remote local loopback.
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Functional Description
Figure 2-8. Signal
POSITIVE PULSE
NEGATIVE PULSE
TLINEP (output voltage)
TLINEN (output voltage)
500020_015
2.3.5
Transmit Monitor Block
transmit monitor inputs (TMONP TMONM) designed monitor line driver outputs (TLINEP TLINEM/N) pulses, assert Loss Signal (TLOS) indicator when output pulse been detected TCLK periods. After TLOS asserted, will deassert until pulse again detected. transmit monitor independent function which TMONP TMONM must externally connected TLINEP TLINEM/N, respectively. special (TMONTST) available testing board-level functionality downstream from TLOS outputs. When TMONTST high asserts TLOS channel outputs. TLOS outputs active high when monitor inputs detect signal.
2.3.6
Jitter Generation (Intrinsic)
M28335 meets jitter generation requirements various rates with large margins, with condition that input transmit clock (TCLK) jitter-free. Data rates jitter generation requirements defined these three documents:
rate-ETSI TBR24, ITU-T 9.823 rate-Bellcore Telecardia GR499, AT&T Accunet TR54014, ITU-T 9.824 STS-1 rate-Bellcore Telecardia GR253
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Functional Description
M28335
2.4.1
Receiver
This section describes detailed operation blocks M28335 receiver.
Receive Sensitivity
receiver recovers data from coaxial cable that attenuated frequency-dependent characteristics cable. addition, receiver compensates flat loss (across frequencies) various electrical components variation transmitted signal power. M28335 recover data that been attenuated maximum feet coax, having characteristics attenuation consistent with ANSI T1.102-1993, Annex Figure C.2. This approximates characteristics AT&T type 734/728 cable; almost same attenuation characteristic achieved one-half length AT&T type cable.
2.4.2
AGC/VGA Block
Variable Gain Amplifier (VGA) receives input signal from coaxial cable. supplies flat gain (independent frequency) make various flat losses transmission channel loss one-half symbol rate that cannot made equalizer. gain controlled feedback loop which senses amplitude equalizer output, acts amplitude servo optimal slicing.
2.4.3
Receive Equalizer
receive equalizer receives differential signal from boosts high frequency content signal reduce intersymbol interference (ISI) point that correct decisions made slicer with minimum jitter recovered data. REQH provided allow lower amounts equalization (shorter equivalent cable lengths) cases where square-shaped pulse (that does meet DS3/ STS-1 standards) transmitted receiver. square-shaped input much larger high-frequency content could have overshoots output high enough cause errors. Setting REQH lowers gain reduces amount overshoot.
2.4.4
Clock Recovery Circuit
clock recovery circuit PLL) extracts embedded clock from sliced data provides retimed data decoder (data mode). Upon startup (after internal reset deasserted), uses reference clock (REFCLK, running symbol rate) phase-frequency detector lock correct data rate (reference mode). During reference mode, data outputs squelched (set kept reference mode until valid input detected.
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Functional Description
2.4.5
Loss Signal (LOS) Detector
Receive Loss Signal (RLOS) digital function that monitors retimed data from clock recovery block. data checked continuous When continuous consecutive occurs, RLOS signal asserted, then count made every block symbols. RLOS signal deasserted when count within block symbols least: B3ZS: Minimum density count (~30.5%) HDB3: Minimum density count (~22.7%) RLOS detector always monitors cable-side inputs. detector affected state remote local looping.
2.4.6
B3ZS/HDB3 Decoder With Bipolar Violation Detector
M28335 device, when ENDECDIS (encoder/decoder enabled), decoder takes output from clock recovery circuit decodes data (HDB3 B3ZS) into single retimed data signal. data signal then sent M28335 RNRZ (RPOS) pin. detected Line Code Violations (LCV) sent over corresponding RLCV (RNEG) pin. RLCV asserted symbol period time violation appears output (RNRZ). following shows data sequence criteria LCV; violations indicated bold text. valid bipolar pulse indicated bipolar violation (non-alternating positive negative) pulse indicated Excessive zeros: (HDB3) (B3ZS). These violations passed data RNRZ pin. Bipolar violation: (i.e., HDB3) (B3ZS HDB3). These violations passed data RNRZ pin. Coding violation: (HDB3) (B3ZS) with even number since last valid substitution (follows coding rule). These violations passed data RNRZ pin. even/odd counter (used count number between will count bipolar violation coding violation valid substitution resets counter. When ENDECDIS decoder disabled, retimed slicer outputs sent over RPOS (RNRZ) RNEG (RLCV) pins. These outputs then decoded Framer other downstream device. LCVs detected this mode operation. decoder configurable either: mode using HDB3 coding (E3MODE DS3/STS-1 mode using B3ZS coding (E3MODE receiver digital data outputs centered rising edge RCLK (see Section 2.10).
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M28335
2.4.7
Data Squelching
counter receiver counts number consecutive symbol periods without valid data pulse. When more counted, receiver assumes lost signal resets itself regain signal. While receiver reacquiring signal, clock recovery block locks reference clock, data squelching achieved forcing data bits data squelching true both dual rail mode. When input signal been properly amplified equalized, clock recovery then switches incoming data.
Jitter Tolerance
M28335 receiver tolerate specified amount high-frequency jitter received signal while providing error-free operation (generally defined 10-9). specifications (illustrated Figure 2-10) jitter tolerance discussed following documents: rate-ITU-T G.823 ETSI TBR24 contain frequency masks input jitter tolerance.
NOTE: meet jitter transfer requirements loop-timed operation, external jitter attenuator required. jitter attenuator lessens jitter from receive clock.
rate-ITU-T G.823 Bellcore GR499 specify jitter tolerance frequency masks Category Category interfaces. STS-1 rate-Bellcore GR253 specifies jitter tolerance.
STS-1 jitter tolerance differs from requirements only Category interfaces.
NOTE:
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Figure 2-9. Minimum Jitter Tolerance Requirement
Rate
Input Jitter Amplitude
Jitter Frequency
STS-1 Rates
STS-1 Category Category
Input Jitter Amplitude
Jitter Frequency
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M28335
2.5.1
Jitter Transfer
receiver must meet certain jitter transfer specifications between input output jitter function frequency. These specifications only intended with jitter attenuator. Because M28335 does contain jitter attenuator, must supplied externally. reference purposes, specifications discussed following documents illustrated Figure 2-10. rate-Assume same DS3. rate-Bellcore GR499, section 7.3.2 figures 7-3, 7-4, 7-5, defines describes jitter transfer. STS-1 rate-Bellcore GR253, section 5.6.2.1, defines describes jitter transfer STS-1 rate.
Figure 2-10. Maximum Jitter Transfer Curve Requirement
Jitter Gain -19.9
STS-1 Category Category Category (Note: slopes dB/decade)
Jitter Frequency
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2.6.1
Additional M28335 Functions
Bias Generator
achieve good isolation between channels, each channel uses independent power ground both transmit receive. Additionally, each channel band voltage reference. Because only external resistor current generation exists, only band voltage used. band from been chosen this task. 12.1 external resistor from RBIAS ground specified have tolerance ±1%. This keeps tighter control power dissipation circuit performance.
NOTE:
Capacitance should kept minimum RBIAS pin.
2.6.2
External Reset
system cannot guarantee valid REFCLK frequency input during power-on reset (POR) cycle, M28335 requires assertion external reset signal (RESET). Valid frequencies REFCLK (44.768 ppm), (34.368 ppm) STS-1 (51.84 ppm).
2.6.3
Power-On Reset (POR)
circuit provided device initialize resettable digital logic analog control lines. circuit uses fixed timer (~1µs) deassert itself soon power supply voltage reaches minimum level When minimum supply voltage reached (see Table 2-6), REFCLK input counted clocks before internal reset deasserted. this time receiver block attempts frequency lock onto valid incoming REFCLK input. After frequency lock achieved, receiver attempts phase lock onto valid RLINE receive signal.
NOTE:
valid REFCLK input present when releases internal reset, receiver block unable lock RLINE receive signal. common some types crystal oscillators oscillate lower fundamental frequency crystal oscillator supply reached minimum operational voltage.
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M28335
2.6.4
Interrupt
Each RLOS TLOS signal goes dedicated edge-detector, whose output stored flip-flop Each interrupt dedicated enable register with which specific interrupt sources activated. interrupt register outputs ORed together generate global interrupt value, which read Global register Global Interrupt signal also enable register Global register, which activates routing global interrupt interrupt pin. Interrupt Status register contents read through parallel serial interface. read interrupt register should clear register, should leave others untouched.
2.6.5
Loopback Multiplexers (MUXes)
loopback MUXes channel M28335 allow local loopback (terminal framer side), remote loopback (cable side), both (the signal follows same path transmit data during loopback). RLOS signal monitors cable inputs irrespective loopback. Remote Loopback (RLOOP) controlled Portn Control register. RLOOP, receive data (retimed after clock recovery decoded) loops back into pulse shaper place transmit data. Additionally, this data sent RPOS, RNEG, RCLK pins. Local Loopback (LLOOP) controlled Portn Control register. LOOP, transmit data loops back immediately from encoder output decoder input place received data. Additionally, this data sent TLINEP TLINEM/N pins.
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Mechanical Specifications
Figure 2-11. M28335 Mechanical Drawing TBGA)-Dimensions
0.10 Corner
0.35 Chamfer Places) VIEW DETAIL BOTTOM VIEW DETAIL
SIDE VIEW DIMENSIONAL REFERENCES MIN. NOM. MAX. 1.25 1.40 1.55 0.40 0.50 0.60 34.80 35.00 35.20 33.00 (BSC.) 34.80 35.00 33.00 (BSC.) 0.63 0.90 0.15 0.25 1.00 TYP. 0.35 0.15
500020_018a
00.30 00.10
REF.
DETAIL
35.20
0.50 0.85
0.75 0.95
DETAIL
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M28335
2.8.1
Electrical Characteristics
Absolute Maximum Ratings
Table 2-5. Absolute Maximum Ratings Symbol
DVDDC/ RVDD/ TVDD/ TVSOL
Parameter
Power supply voltage
-0.3
Unit
Voltage signal Storage temperature Vapor phase soldering temperature min.) Thermal resistance (Still air, soldered) Failures time 89,000 device hours, temperature failures.
-1.0
°C/W °C/W fits
GENERAL NOTE:
Stresses above those listed absolute maximum ratings cause permanent damage device. This stress rating only, functional operation device these other conditions beyond those indicated other sections this document implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
2.8.2
Recommended Operating Conditions
Table lists various operating conditions, power supplies, bias resistor.
Table 2-6. Recommended Operating Conditions Parameter
Power supply voltage voltage(1) Power dissipation External bias resistor
FOOTNOTE:
Conditions
DVDDC, RVDD, TVDD, Total chip RBIAS GND;
3.135 3.135 11.98
3.32 12.1
3.465 12.22
Unit
With logic input, should tied With logic input, should tied
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Parameter
high threshold threshold high threshold threshold ILEAK Input capacitance Load capacitance
GENERAL NOTE:
Characteristics
Conditions
Digital inputs Digital inputs Digital outputs, Digital outputs, digital Digital outputs
Table 2-7. Characteristics
-0.3
Unit
digital inputs V-compliant. These inputs diode protected DVDDIO DVSSIO pins. Additionally, digital inputs contain pull-down resistors. digital outputs also V-compliant. However, these outputs will drive will they accept external pull-ups. output DVDDC (3.3
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Functional Description
M28335
2.10
Characteristics
Table 2-8. Characteristics (Logic Timing) Parameter
Tosym, Tisym RCLK TCLK Clock Duty Cycle DS-3 STS-1 Towidth/Tosym, RCLK Tiwidth/Tisym, TCLK Tiwidth/Tisym, REFCLK TPOS/TNRZ, TNEG, TAIS TPOS/TNRZ, TNEG, TAIS
Conditions
29.10 22.35 19.29
Unit
Todelay Tisetup Tihold
GENERAL NOTE:
description applies DS3, STS-1 clock rates other parameters such pulse width, set-up time, hold time, duty cycle. timing diagram, illustrated Figure 2-12, describes logical relationship between various clock data signals, parameter values. A.C. timings based load.
Figure 2-12. Timing Diagram
Tosym
DATA OUTPUTS
RCLK Towidth Todelay
RPOS/RNRZ, RNEG/RLCV
Tisym
DATA INPUTS
TCLK Tiwidth
Tisetup
Tihold
TPOS/TNRZ, TNEG, TAIS,
Don't Care
Valid Data
Don't Care
500020_020
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Table 2-9. Mode Timing-Read Cycles Parameter
TAZD tdis tpwh tpwl Address valid data valid Address hold after BCS~ BOE~ rising edge BCS~ BOE~ falling edge BDATA drive BDATA hold after BCS~ BOE~ rising edge BCS~ BOE~ high time BCS~ BOE~ time
Description
Figure 2-13. Mode Read Timing
tAZD BADDR[3:0] Address Read Data
tdis
BDATA[7:0]
BWR~ tpwh BCS~ BOE~
500020_026
tpwl
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M28335
Table 2-10. Mode Timing-Write Cycles Parameter
tpwh tpwl
Description
Address setup before BCS~ BWR~ rising edge Address hold after BCS~ BWR~ rising edge Data setup before BCS~ BWR~ rising edge Data hold after BCS~ BWR~ rising edge BCS~ BWR~ high time BCS~ &BWR~ time
Type
Figure 2-14. Mode Write Timing
tAZD BADDR[3:0] Address BDATA[7:0] tpwh BCS~ BWR~ BOE~ tpwl Write Data
(high)
500020_027
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Table 2-11. Serial Mode Timing Symbol
Tcssu PWsch PWscl Tsisu Tsihf Tvsif Tsiz PWcsi Tcsur
Parameter
CS_N set-up time SCLK rising edge Pulse width SCLK high Pulse width SCLK SCLK rising edge set-up time SCLK rising edge hold time SCLK falling edge valid time CS_N inactive three-state Pulse width CS_N inactive SCLK rising edge CS_N hold time
Unit
Figure 2-15. Serial Mode Register Read (see Note below)
PWcsi BCSN Tcssu SCLK Tsihf Tsisu Write PWscl PWsch Tcsur
SDIN
50020_038A
Figure 2-16. Serial Mode Register Write (see Note below)
PWcsi BCSN Tcssu SCLK Tsihf Tsisu Read PWscl PWsch
SDIN
Address
Tvsif
Read Data
Tsiz
50020_037
SDOUT
NOTE:
Serial mode, BDATA1/PORTMODE2/SDOUT configured SDOUT, BDATA0/PORTMODE1/SDIN configured SDIN, BOE~/LMODE0/SCLK configured SCLK.
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2-25
Functional Description
M28335
2-26
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Registers
Address
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 00x9 0x0A 0x0B 0x0C 0x0D 0x1E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18
Address
Name
PC10 PC11 PC12 RMTR1 RMTR2 RMTR3 RALM1 RALM2 TALM1 TALM2 RISR1 RISR2 TISR1 TISR2 RIER1
Table 3-1. Register Address Description
Global Control Register Port1 Control Register Port2 Control Register Port3 Control Register Port4 Control Register Port5 Control Register Port6 Control Register Port7 Control Register Port8 Control Register Port9 Control Register Port10 Control Register Port11 Control Register Port12 Control Register RLOS Max/Threshold Register RLOS Max/Threshold Register RLOS Max/Threshold Register RLOS Alarm Register RLOS Alarm Register TLOS Alarm Register TLOS Alarm Register RLOS Interrupt Status Register RLOS Interrupt Status Register TLOS Interrupt Status Register TLOS Interrupt Status Register RLOS Interrupt Enable Register
Default
0x00 0x00 0x00 0x00
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Registers
M28335
Table 3-1. Register Address Address
0x19 0x1A 0x1B 0x1C 0x1D
Name
RIER2 TIER1 TIER2 RDR1 RDR2
Description
RLOS Interrupt Enable Register TLOS Interrupt Enable Register TLOS Interrupt Enable Register RLOS Data Squelch Disable Register RLOS Data Squelch Disable Register
Default
0x00 0x00 0x00 0x00 0x00
Global Register
0x0-Global Control Register (GC)
Name Default
BINTR
BINTR
INTR_TST
TMONTST
INTEN
RESET
Interrupt Status alarm interrupt pending more alarm interrupt pending
NOTE: BINTR different from hardware BINT~ because BINT~ masked INTEN bit.
INTR_TST
Interrupt Test Control Normal operation (RLOS TLOS signals used interrupt sources) Interrupt test operations (DATA2-DATA7 signals used interrupt sources)
NOTE: BINTR different from hardware BINT~ because BINT~ masked INTEN bit.
TMONTST
Monitor Test Normal operation TLOS Asserts TLOS outputs; this used test board-level functionality downstream from TLOS outputs
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M28335
Registers
Port Registers
0x1-0xC-Portn Control Register (PCn)
Name Default
ENDECDIS
ENCDECDIS
RLOOP
LLOOP
REQH
Encoder/Decoder Disable Device accepts data TNRZ (TPOS) outputs decoded single-ended data RNRZ (RPOS) Device accepts bipolar AMI/B3ZS/HDB3 data TPOS/TNEG outputs receive bipolar data RPOS/RNEG Line Build feet Line Build disabled feet Line Build enabled Port Power-down Transmitter receiver this port disabled. This setting will also cause interrupt this port masked. alarm condition (RLOS TLOS) from powered-down port will cause interrupt occur. power-down (PD~ transition high low) will generate interrupt. Normal operation Remote Loopback Normal operation Remote Loopback enabled this port Local Loop Back Normal operation Local Loopback enabled this port Receive Equalizer High Receive Equalizer forced gain. Used correctly receive square pulses. Normal receive equalizer setting. Used normal operation. This effect mode selected Mode DS3/STS-1 mode mode Transmit Output Enable Transmit output disabled Transmit output enabled
RLOOP
LLOOP
REQH
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Registers
M28335
Interrupt Status Registers
0x14-RLOS Interrupt Status Register (RISR1)
Name
RISn
RIS8
RIS7
RIS6
RIS5
RIS4
RIS3
RIS2
RIS1
Receive Loss Signal (RLOS) Interrupt status. RLOS interrupt pending RLOS interrupt pending
0x15-RLOS Interrupt Status Register (RISR2)
Name
RISn
RIS12
RIS11
RIS10
RIS9
RLOS Interrupt status. RLOS interrupt pending RLOS interrupt pending
0x16-TLOS Interrupt Status Register (TISR1)
Name
TISn
TIS8
TIS7
TIS6
TIS5
TIS4
TIS3
TIS2
TIS1
Transmit Loss Signal (TLOS) Interrupt status. TLOS interrupt pending TLOS interrupt pending
0x17-TLOS Interrupt Status Register (TISR2)
Name
TISn
TIS12
TIS11
TIS10
TIS9
TLOS Interrupt status. TLOS interrupt pending TLOS interrupt pending
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M28335
Registers
Interrupt Enable Registers
0x18-RLOS Interrupt Enable Register (RIER1)
Name
RIEn
RIE8
RIE7
RIE6
RIE5
RIE4
RIE3
RIE2
RIE1
RLOS Interrupt enable. RLOS interrupt disabled RLOS interrupt enabled
0x19-RLOS Interrupt Enable Register (RIER2)
Name
RIEn
RIE12
RIE11
RIE10
RIE9
RLOS Interrupt enable. RLOS interrupt disabled RLOS interrupt enabled
0x1A-TLOS Interrupt Enable Register (TIER1)
Name
TIEn
TIE8
TIE7
TIE6
TIE5
TIE4
TIE3
TIE2
TIE1
TLOS Interrupt enable. TLOS interrupt disabled TLOS interrupt enabled
0x1B-TLOS Interrupt Enable Register (TIER2)
Name
TIEn
TIE12
TIE11
TIE10
TIE9
TLOS Interrupt enable. TLOS interrupt disabled TLOS interrupt enabled
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Registers
M28335
RLOS Threshold Control Registers
0x0D-RMTR1 (RLOS Threshold Register
Name
RMn&RTn
RLOS Maximum RLOS Threshold. Table RLOS threshold control bits.
0x0E-RMTR2 (RLOS Threshold Register
Name
RMn&RTn
RLOS Maximum RLOS Threshold. Table RLOS threshold control bits.
0x0F-RMTR3 (RLOS Threshold Register
Name
RMn&RTn
RM12
RT12
RM11
RT11
RM10
RT10
RLOS Maximum RLOS Threshold. Table RLOS threshold control bits.
Table 3-2. RLOS Threshold Control Bits
Action
RLOS Cleared RLOS Declared
(mV)
(TBD)
Typical (mV)
(TBD) (TBD) (TBD) (TBD)
(mV)
(TBD)
RLOS Cleared RLOS Declared
RLOS Cleared RLOS Declared
Reserved
GENERAL NOTE: Hysteresis
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M28335
Registers
RLOS Data Squelch Disable Registers
0x1C-RDR1 (RLOS Disable Register
Name
RLOS disable RLOS auto data squelch enabled RLOS data squelch disabled
0x1D-RDR2 (RLOS Disable Register
Name
RD12
RD11
RD10
RLOS disable RLOS auto data squelch enabled RLOS data squelch disabled
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Registers
M28335
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Applications
M28335 used variety applications.
Line Interface Example
Figure illustrates example line being terminated M28335. data clock extracted passed framer chip further data manipulation user interface. important employ high-frequency design techniques printed board layout.
Figure 4-1. Line Interface Example
M28335
TPOS TNEG TCLK TMONP TLINEP TLINEN TMONM 31.6 37.4 0.01µF Type 728, 734, 31.6 Type 728, 734,
Framer
Channel
RPOS RNEG RCLK RLINEP RLINEN
37.4
Only Channel Shown
General Note: transformers part number T3001 from Pulse Technology. Recommended Vendors, Section 3.1.5. TMONP TMONM denoted dotted lines.
500020_025
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M28335
Interface Example CX28365 Mode
M28335 interfaced CX28365 T3/E3 Framer Cell Delineator without glue logic illustrated Figure 4-2. M28335 configured mode provide more flexible control. line Framer/ Delineator OutPort2 configured provide "Chip-Select" M28335. line InPort1 Framer/Delineator configured interrupt input receive interrupt from M28335. BADD BDATA M28335 located processor address data respectively. TLOS RLOS status accessed through M28335's internal registers. TLOS RLOS hardware status from M28335 used drive LEDs provide realtime display status lines, they used further status processing.
Figure 4-2. Interface CX28365 Mode
M28335 M28335 T3/E3/STS-1 T3/E3/STS-1
BDATA[7:0]
Processor Data
CX28365 M28365 T3/E3 Framer T3/E3 Framer Cell Delineator Cell Delineator
MData[7:0]
Processor Address
BADD[4:0]
Processor Control
MAddr[12:0]
BWR~ BOE~
MWR~ MOE~
BCS~ BINTR~
OutPort2[0] InPort1[0]
BMODE1 BMODE0
Note: BMODE0 internal pulldown. left disconnected grounded.
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M28335
Applications
Interface Example CX28365 Hardware Mode
M28335 interfaced CX28365 T3/E3 Framer Cell Delineator hardware mode illustrated Figure 4-3. OutPort1 Framer/ Delineator configured output control twelve PORTMODE lines M28335. Three OutPort2 lines Framer/Delineator configured output handle global remote loop back chip-wide mode controls. InPort1 InPort2 configured input monitor RLOS TLOS from M28335.
Figure 4-3. Interface CX28365 Hardware Mode
M28335 CX28335 T3/E3/STS-1 T3/E3/STS-1
PORTMODE1 PORTMODE2 PORTMODE3 PORTMODE4 PORTMODE5 PORTMODE6 PORTMODE7 PORTMODE8 PORTMODE9 PORTMODE10 PORTMODE11 PORTMODE12 LMODE0 LMODE1 GRLOOP
CX28365 CX28365 T3/E3 Framer T3/E3 Framer Cell Delineator Cell Delineator
OutPort1[0] OutPort1[1] OutPort1[2] OutPort1[3] OutPort1[4] OutPort1[5] OutPort1[6] OutPort1[7] OutPort1[8] OutPort1[9] OutPort1[10] OutPort1[11] OutPort2[0] OutPort2[1] OutPort2[2] InPort1[11:0] InPort2[11:0]
BMODE0 BMODE1
RLOS[11:0] TLOS[11:0]
Note: BMODE0 internal pulldown. left disconnected grounded.
500020_035
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Applications
M28335
Serial Mode Interface Example
M28335 interfaced microprocessor microcontroller that supports Serial Peripheral Interface (SPI) shown Figure 4-4. microprocessor/ microcontroller working master. generates SPICLK that shifts data from M28335 SDOUT Master Slave (SPIMISO) shifts data M28335 SDIN through Master Out, Slave (SPIMOSI) pin. microprocessor/microcontroller also provides chip-select function receives interrupt from M28335.
Figure 4-4. Serial Mode Interface Example
M28335 M28335 T3/E3/STS-1 T3/E3/STS-1
Microprocessor/ Microprocessor/ Controller Controller
SCLK SDIN SDOUT BCS~ BINTR~
SPICLK SPIMOSI SPIMISO CHIP_SELECT INTERRUPT
BMODE1 BMODE0
500020_034
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M28335
Applications
Design Considerations M28335
M28335 device LIUs operating frequencies 52.84 MHz. highspeed nature device calls careful design using this device. Some design considerations outlined below.
4.5.1
Power Supply Ground Plane
unified power plane with properly placed capacitors correct size will mitigate most power rail-related voltage transients. properly placed bulk capacitor, where power enters board, with noise-bypassing capacitors power pins integrated circuits should adequate. noise-bypassing capacitors must able supply switching current. Ferrite beads used with power rails filter high-frequency noise. every design, noise frequencies levels different. Therefore, whether beads necessary not, effective frequency where they should operate, difficult determine. good idea provision ferrite beads boards. board trace from M28335 power supply noise-bypassing capacitor should minimized. Additionally, ground connections from ground plane M28335 ground pins noise-bypassing capacitor ground pins should minimized. unified ground plane best minimize ground impedance. Most ground noise produced return currents power supply transients during switching. This effect minimized reducing ground plane impedance.
4.5.2
4.5.2.1
Component Placement
VBIAS Resistor
important keep VBAIS quiet, noise coupled this affects internal references. VBIAS resistor should placed close possible VBIAS digital signals should routed near resistor. Additionally, would wise guard pin, resistor, traces with ground vias.
4.5.2.2
Decoupling
recommended that decoupled with 0.01 capacitor. capacitor should placed close the.01 capacitor should placed close capacitor.
4.5.2.3
Termination Resistors Capacitor
impedance matching termination resistors capacitor should placed close RLINE pins possible.
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M28335
4.5.3
Impedance Matching
critical that traces around transformers matching resistors kept minimum length and, following cases, trace impedance matched with ±10% tolerance:
impedance from connector transformer impedance from transformer matching resistors
4.5.4
Other Passive Parts
reference design uses Pulse T3001 extended temperature range transformer coupling connector device. ferrite beads used decouple receive- transmit-VDD pins analog input pins type 2508056017Y0 from Fair-Rite Products Corporation. recommended that tantulum capacitor used where power enters board.
4.5.5
IBIS Models
IBIS (Input/Output Buffer Interface Specification) models M28335 available from Mindspeed's site (www.Mindspeed.com).
4.5.6
Recommended Vendors
Product: Transformers Product: Ferrite Beads Fair-Rite Products Corp. P.O. Commercial Wallkill, 12589 914-895-2055 www.Fair-Rite.com
America Address:
Telo: Fax: Northern Asia
Pulse Corporate Office 12220 World Trade Drive Diego, 92128 858-674-8100 858-674-8262 Pulse 3F-4, Sec. Hsin Road Hsi-Chih Tapei Hsien, Taiwan R.O.C. 886-2-26980228 886-2-26980948 Pulse Huxley Road Surrey Research Park Guildford, Surrey United Kingdom 44-1483-401700 44-1483-401701
Telo: site:
Telo: Northern Europe
Product: Crystals Crystek Corp. 12730 Commonwealth Drive Fort Myers, 33913 800-237-3061 941561-1025 sales@crystek.com www.crystek.com
Telo: Fax:
Telo: Fax: E-mail: site:
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Appendix Applicable Standards
applicable standards documents follows:
ANSI T1.102-1993 (DS3 STS-1 standard) ANSI T1.404a-1996 (DS3 metallic interface) Recommendation G.703 (DS3 standard) Recommendation G.823 G.824 (jitter wander) Bellcore GR499, Issue 12/89 (formerly TR-TSY-000499) (DS3 STS-1 requirements) Bellcore GR253, Issue 12/91 (formerly TA-NWT-000253) (STS-1 requirements jitter) Bellcore TR-TSY-000191, Issue 5/86 (AIS LOS) ETSI TBR24 TBR25 terminal equipment interface) ETSI standard) AT&T Technical Reference TR54014, 1992 (Accunet Interface Specification DS-3 jitter only)
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Applicable Standards
M28335
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www.mindspeed.com General Information: U.S. Canada: (800) 854-8099 International: (949) 483-6996 Headquarters Newport Beach 4311 Jamboree P.O. Newport Beach, 92658

500020D December 2001 Ordering Information Model Number M283

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