700MHZ, JITTER LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER FEATUR

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700MHZ, JITTER LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER FEATUR

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ICS8430-11
700MHZ, JITTER LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
FEATURES
Dual differential 3.3V LVPECL outputs Selectable crystal oscillator interface LVCMOS TEST_CLK utput frequency 700MHz Crystal input frequency range: 14MHz 25MHz range: 200MHz 700MHz Parallel serial interface programming counter output dividers period jitter: 2.6ps (typical) Cycle-to-cycle jitter: 17ps (typical) 3.3V supply voltage 70°C ambient operating temperature Industrial temperature information available upon request
GENERAL DESCRIPTION
ICS8430-11 general purpose, dual output Crystal-to-3.3V Differential LVPECL High Frequency HiPerClockSSynthesizer member HiPerClockSfamily High Performance Clock Solutions from ICS. ICS8430-11 selectable TEST_CLK crystal inputs. operates frequency range 200MHz 700MHz. With output configured divide frequency output frequency steps small 2MHz achieved using 16MHz crystal reference clock. Output frequencies 700MHz programmed using serial parallel interfaces configuration logic. jitter frequency range ICS8430-11 make ideal clock generator most clock tree applications.
BLOCK DIAGRAM
VCO_SEL
ASSIGNMENT
VCO_SEL nP_LOAD XTAL2
XTAL_SEL TEST_CLK XTAL1 XTAL2
XTAL1 TEST_CLK XTAL_SEL VCCA S_LOAD S_DATA S_CLOCK
ICS8430-11
PHASE DETECTOR S_LOAD S_DATA S_CLOCK nP_LOAD M0:M8 N0:N2 CONFIGURATION INTERFACE LOGIC
FOUT0 nFOUT0 FOUT1 nFOUT1
TEST FOUT1 nFOUT1 VCCO FOUT0 nFOUT0
TEST
32-Lead LQFP 1.4mm package body Package View
Preliminary Information presented herein represents product prototyping pre-production. noted characteristics based initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves right change circuitry specifications without notice.
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700MHZ, JITTER LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
NOTE: functional description that follows describes operation using 16MHz crystal. Valid loop divider values different crystal input frequencies defined Input Frequency Characteristics, Table NOTE
ICS8430-11 features fully integrated therefore requires external components setting loop bandwidth. parallel-resonant, fundamental crystal used input on-chip oscillator. output oscillator divided prior phase detector. With 16MHz crystal, this provides 1MHz reference frequency. operates over range 200MHz 700MHz. output divider also applied phase detector. phase detector divider force output frequency times reference frequency adjusting control voltage. Note that some values (either high low), will achieve lock. output scaled divider prior being sent each LVPECL output buffers. divider provides output duty cycle. programmable features ICS8430-11 support input modes, programmable divider output divider. input operational modes parallel serial. Figure shows timing diagram each mode. parallel mode, nP_LOAD input initially LOW. data inputs through through passed directly divider output divider. LOW-to-HIGH transition nP_LOAD input, data latched divider remains loaded until next transition nP_LOAD until serial event occurs. result, bits hardwired divider output divider specific default state that will automatically occur during power-up. TEST output when operating parallel input mode. relationship between frequency, crystal frequency divider defined follows: fxtal fVCO value required values through shown Table Programmable Frequency Function Table. Valid values which will achieve lock 16MHz reference defined 350. frequency defined follows: fout fVCO fxtal Serial operation occurs when nP_LOAD HIGH S_LOAD LOW. shift register loaded sampling S_DATA bits with rising edge S_CLOCK. contents shift register loaded into divider output divider when S_LOAD transitions from LOW-to-HIGH. divide output divide values latched HIGH-to-LOW transition S_LOAD. S_LOAD held HIGH, data S_DATA input passed directly divider output divider each rising edge S_CLOCK. serial mode used program bits test bits internal registers determine state TEST output follows: TEST Output S_Data clocked into register Output divider CMOS Fout
S_DATA S_CLOCK S_LOAD
M0:M8, N0:N2
nP_LOAD
Time
FIGURE PARALLEL SERIAL LOAD OPERATIONS
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Type Input Input Input Input Power Output Power Output Power Output Input Pulldown Description
TABLE DESCRIPTIONS
Number Name TEST FOUT1, nFOUT1 VCCO FOUT0, nFOUT0
Pulldown divider inputs. Data latched LOW-to-HIGH transition nP_LOAD input. LVCMOS LVTTL interface levels. Pullup Pulldown Determines output divider value defined Table Function Table. LVCMOS LVTTL interface levels. Pullup Negative supply pins. Test output which ACTIVE serial mode operation. Output driven parallel mode. LVCMOS interface levels. Positive power supply pin. Differential output synthesizer. 3.3V LVPECL interface levels. Output supply pin. Differential output synthesizer. 3.3V LVPECL interface levels.
Master reset. Forces outputs LOW, does affect loaded values. LVCMOS LVTTL interface levels. Clocks serial data present S_DATA input into shift register S_CLOCK Input Pulldown rising edge S_CLOCK. Shift register serial input. Data sampled rising edge S_DATA Input Pulldown S_CLOCK. Controls transition data from shift register into dividers. S_LOAD Input Pulldown LVCMOS LVTTL interface levels. VCCA Power Analog supply pin. Selects between ystal test inputs reference source. XTAL_SEL Input Pullup LVCMOS LVTTL interface levels. Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW. TEST_CLK Input Pulldown Test clock input. LVCMOS LVTTL interface levels. XTAL1, XTAL2 Input ystal oscillator inputs. Parallel load input. Determines when data present M8:M0 nP_LOAD Input Pulldown loaded into divider, when data present N2:N0 sets output divider value. LVCMOS LVTTL interface levels. Determines whether synthesizer bypass mode. VCO_SEL Input Pullup LVCMOS LVTTL interface levels. NOTE: Pullup Pulldown refer internal input resistors. Table Characteristics, typical values.
TABLE CHARACTERISTICS
Symbol RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical Maximum Units
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TABLE PARALLEL
SERIAL MODES FUNCTION TABLE
Inputs Conditions S_CLOCK S_DATA Data Data Data Data Reset. Forces outputs LOW. Data inputs passed directly divider output divider. TEST output forced LOW. Data latched into input registers remains loaded until next transition until serial event occurs. Serial input mode. Shift register loaded with data S_DATA each rising edge S_CLOCK. Contents shift register passed divider output divider. divider output divider values latched. Parallel serial input affect shift registers. S_DATA passed directly divider clocked.
nP_LOAD
Data Data
Data Data
S_LOAD
NOTE: HIGH Don't care Rising edge transition Falling edge transition
TABLE PROGRAMMABLE FREQUENCY FUNCTION TABLE (NOTE
Frequency (MHz) NOTE These divide 16MHz. Divide
values resulting
frequencies correspond ystal TEST_CLK
input frequency
TABLE PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs
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Divider Value
FOUT0, nFOUT0 Output Frequency (MHz) Minimum Maximum 12.5 87.5 43.75 87.5
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700MHZ, JITTER LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
4.6V -0.5V 0.5V -0.5V VCCO 0.5V 47.9°C/W lfpm) -65°C 150°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCCx Inputs, Outputs, Package Thermal Impedance, Storage Temperature, TSTG
Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
TABLE POWER SUPPLY CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol VCCA VCCO ICCA Parameter Positive Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical Maximum 3.465 3.465 3.465 Units
TABLE LVCMOS CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol Input High Voltage Parameter TEST_CLK VCO_SEL, S_LOAD, S_DATA, S_CLOCK, nP_LOAD, M0:M8, N0:N2, XTAL_SEL TEST_CLK VCO_SEL, S_LOAD, S_DATA, S_CLOCK, nP_LOAD, M0:M8, N0:N2, XTAL_SEL M0-M7, S_CLOCK, S_DATA, S_LOAD, TEST_CLK, nP_LOAD XTAL_SEL, VCO_SEL M0-M7, S_CLOCK, S_DATA, S_LOAD, TEST_CLK, nP_LOAD XTAL_SEL, VCO_SEL Test Conditions Minimum -0.3 -0.3 Typical Maximum Units
Input Voltage
Input High Current
3.465V 3.465V 3.465V, 3.465V,
Input Current
-150
Output TEST; NOTE High Voltage Output TEST; NOTE Voltage NOTE Outputs terminated with VCCO/2.
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Test Conditions Minimum Typical Maximum 0.85 Units
TABLE LVPECL CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol Parameter Output High Voltage; NOTE Output Voltage; NOTE
VSWING Peak-to-Peak Output Voltage Swing NOTE Outputs terminated with VCCO "Parameter Measurement Information" section, "3.3V Output Load Test Circuit" figure.
TABLE INPUT FREQUENCY CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol Parameter TEST_CLK; NOTE Input Frequency XTAL1, XTAL2; NOTE Test Conditions Minimum Typical Maximum Units
S_CLOCK NOTE input crystal reference frequency range, value must operate within 200MHz 700MHz range. Using minimum input frequency 14MHz, valid values 400. Using maximum frequency 25MHz, valid values 224.
TABLE CRYSTAL CHARACTERISTICS
Parameter Mode Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Test Conditions Minimum Typical Maximum Units Fundamental
TABLE CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol FMAX Parameter Output Frequency Cycle-to-Cycle Jitter NOTE Period Jitter, RMS; NOTE Output Skew; NOTE Output Rise Time Output Fall Time nP_LOAD Setup Time S_DATA S_CLOCK S_CLOCK S_LOAD nP_LOAD Hold Time Output Duty Cycle S_DATA S_CLOCK S_CLOCK S_LOAD Test Conditions Minimum Typical Maximum Units
tjit(cc) tjit(per) tsk(o)
Lock Time tLOCK Parameter Measurement Information section. NOTE Jitter performance using XTAL inputs. NOTE Defined skew between outputs same supply voltage with equal load conditions. Measured output differential cross points. NOTE This parameter defined accordance with JEDEC Standard
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700MHZ, JITTER LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
VCCA VCCO
SCOPE
LVPECL
VCC, VCCA VCCO
-1.3V 0.135V
3.3V OUTPUT LOAD TEST CIRCUIT
nFOUTx
FOUTx
nFOUTy FOUTy
tsk(o)
OUTPUT SKEW
SWING
Clock Inputs Outputs
INPUT
OUTPUT RISE
FALL TIME
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700MHZ, JITTER LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
nFOUTx TEST, FOUTx
Pulse Width
PERIOD
PERIOD
tPERIOD
Vref
contains 68.26% measurements contains 95.4% measurements contains 99.73% measurements contains 99.99366% measurements contains (100-1.973x10-7)% measurements
Histogram
Reference Point
(Trigger Edge)
Mean Period
(First edge after trigger)
Period Jitter
nFOUTx
FOUTx
tcycle
jit(cc) tcycle -tcycle
1000 Cycles
Cycle-to-Cycle Jitter
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tcycle
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700MHZ, JITTER LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER APPLICATIONS
POWER SUPPLY FILTERING TECHNIQUES
high speed analog circuitry, power supply pins vulnerable random noise. ICS8430-11 provides separate power supplies isolate high switching noise from outputs internal PLL. VCC, VCCA, VCCO should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, power supply isolation required. Figure illustrates resistor along with 10µF .01µF bypass capacitor should connected each VCCA pin.
3.3V .01µF .01µF
FIGURE POWER SUPPLY FILTERING
CRYSTAL INPUT OSCILLATOR INTERFACE
ICS8430-11 features internal oscillator that uses external quartz crystal source reference frequency. 16MHz crystal divided before being sent phase detector provides reference frequency. oscillator series resonant, multi-vibrator type design. This design provides better stability eliminates need large chip capacitors. Though series resonant crystal preferred, parallel resonant crystal used. parallel resonant mode crystal used series resonant circuit will exhibit frequency oscillation hundred lower than specified. hundred translates inaccuracy. general computing applications this level inaccuracy irrelevant. better accuracy required, external capacitor added parallel resonant crystal series Figure shows interface with crystal. Figures show various crystal parameters which recommended only guidelines. Figure shows interface capacitor with parallel resonant crystal. Figure shows capacitor value needed optimum perforFIGURE Recommended tuning capacitance various parallel resonant crystals.
Series Capacitor, (pF) 24.000 Crystal Frequency (MHz) 15.000 16.667 19.440 20.000 14.318
mance over various parallel resonant crystals. Figure shows recommended tuning capacitance various parallel resonant crystals.
ICS8430-11
XTAL2
(Pin LQFP)
XTAL1
FIGURE CRYSTAL INTERFACE
FIGURE Recommended tuning capacitance various parallel resonant crystals.
-100
Frequency Accuracy (ppm)
Optional
(Pin LQFP)
19.44MHz
Series Capacitor, (pF)
16MHz 15.00MHz
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TERMINATION LVPECL OUTPUTS
clock layout topology shown below typical termination LVPECL outputs. different layouts mentioned recommended only guidelines. FOUT nFOUT impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors current path ground) current sources must used functionality. These outputs designed
drive transmission lines. Matched impedance techniques should used maximize operating frequency minimize signal distortion. There simple termination schemes. Figures show different layouts which recommended only guidelines. Other suitable clock layouts exist would recommended that board designers simulate guarantee compatibility across printed circuit clock component process variations.
3.3V
FOUT
FOUT
(VOH
FIGURE LVPECL OUTPUT TERMINATION
schematic ICS8430-11 layout example used this layout guideline shown Figure ICS8430-11 recommended board layout this example shown Figure This layout example used general guideline. layout actual system will depend selected component types, density components, density traces, stacking P.C. board.
0.01u REF_IN XTAL_SEL S_LOAD S_DATA S_CLOCK
TEST FOUT1 nFOUT1 VCCO FOUT0 nFOUT0
VCO_SEL nP_LOAD XTAL2
FOUT FOUTN
8430-01
TEST
0.1u
FIGURE SCHEMATIC
8430DY-11
0.1u
FIGURE LVPECL OUTPUT TERMINATION
LAYOUT GUIDELINE
XTAL1 REF_IN nXTAL_SEL VCCA S_LOAD S_DATA S_CLOCK
Termination
Termination (Not shown layout)
INTL2
RECOMMENDED LAYOUT
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traces with transmission lines FOUT nFOUT should have equal delay adjacent each other. Avoid sharp angles clock trace. Sharp angle turns cause characteristic impedance change transmission lines. Keep clock trace same layer. Whenever possible, avoid vias clock traces. trace affect trace characteristic impedance hence degrade signal quality. prevent cross talk, avoid routing other signal traces parallel with clock traces. running parallel traces unavoidable, allow more space between clock trace other signal trace. Make sure other signal trace routed between clock trace pair. matching termination resistors should located close receiver input pins possible. Other termination schemes also used shown this example.
following component footprints used this layout example: resistors capacitors size 0603.
POWER
GROUNDING
Place decoupling capacitors close possible power pins. space allows, placing decoupling capacitor component side preferred. This reduce unwanted inductance between decoupling capacitor power generated via. Maximize size power (ground) decoupling capacitor. Maximize number vias between power (ground) pads. This reduce inductance between power (ground) plane component power (ground) pins. VCCA shares same power supply with VCC, insert filter C11, between. Place this filter close VCCA possible.
CLOCK TRACES
TERMINATION
component placements, locations orientations should arranged achieve best clock signal quality. Poor clock signal quality degrade system performance cause system failure. synchronous high-speed digital system, clock signal less tolerable poor signal quality than other signals. ringing rising falling edge excessive ring back cause system failure. trace shape trace delay might restricted available space board component location. While routing traces, clock signal traces should routed first should locked prior routing other signal traces.
CRYSTAL
crystal should located close possible pins (XTAL1) (XTAL2). trace length between should kept minimum avoid unwanted parasitic inductance capacitance. Other signal traces should routed near crystal traces.
VCCA Close input pins receiver TL1N
TL1N
TL1, traces equal length
FIGURE BOARD LAYOUT
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700MHZ, JITTER LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS
This section provides information power dissipation junction temperature ICS8430-11. Equations example calculations also provided.
Power Dissipation. total power dissipation ICS8430-11 core power plus power dissipated load(s). following power dissipation 3.3V 3.465V, which gives worst case results. NOTE: Please refer Section details calculating power dissipated load.
Power (core)MAX VCC_MAX IEE_MAX 3.465V 120mA 416mW Power (outputs)MAX 30.2mW/Loaded Output pair outputs loaded, total power 30.2mW 60.4mW
Total Power_MAX (3.465V, with outputs switching) 416mW 60.4mW 476.4mW
Junction Temperature. Junction temperature, temperature junction bond wire bond directly affects reliability device. maximum recommended junction temperature HiPerClockSdevices 125°C.
equation follows: Pd_total Junction Temperature Junction-to-Ambient Thermal Resistance Pd_total Total Device Power Dissipation (example calculation section above) Ambient Temperature order calculate junction temperature, appropriate junction-to-ambient thermal resistance must used Assuming moderate flow linear feet minute multi-layer board, appropriate value 42.1°C/W Table below. Therefore, ambient temperature 70°C with outputs switching 70°C 0.476W 42.1°C/W 90°C. This well below limit 125°C This calculation only example. will obviously vary depending number loaded outputs, supply voltage, flow, type board (single layer multi-layer).
TABLE THERMAL RESISTANCE
32-PIN LQFP, FORCED CONVECTION
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W
55.9°C/W 42.1°C/W
50.1°C/W 39.4°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
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Calculations Equations.
purpose this section derive power dissipated into load. LVPECL output driver circuit termination shown Figure
VCCO
VOUT VCCO
FIGURE LVPECL DRIVER CIRCUIT
TERMINATION
calculate worst case power dissipation into load, following equations which assume load, termination voltage
logic high, VOUT
CCO_MAX
OH_MAX
CCO_MAX
1.0V
OH_MAX
1.0V 1.7V
logic low, VOUT
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
1.7V
Pd_H power dissipation when output drives high. Pd_L power dissipation when output drives low. Pd_H 2V))/R
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
[(2V
CCO_MAX
OH_MAX
))/R
CCO_MAX
OH_MAX
[(2V 1V)/50] 20.0mW
Pd_L
OL_MAX
CCO_MAX
2V))/R
CCO_MAX
OL_MAX
[(2V
CCO_MAX
OL_MAX
))/R
CCO_MAX
OL_MAX
[(2V 1.7V)/50] 1.7V 10.2mW Total Power Dissipation output pair Pd_H Pd_L 30.2mW
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700MHZ, JITTER LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE JAVS. FLOW TABLE
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W
55.9°C/W 42.1°C/W
50.1°C/W 39.4°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
TRANSISTOR COUNT
transistor count ICS8430-11 4534
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PACKAGE OUTLINE SUFFIX
TABLE PACKAGE DIMENSIONS
JEDEC VARIATION DIMENSIONS MILLIMETERS SYMBOL
Reference Document: JEDEC Publication MS-026
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MINIMUM
NOMINAL
MAXIMUM
1.60 0.05 1.35 0.30 0.09 9.00 BASIC 7.00 BASIC 5.60 9.00 BASIC 7.00 BASIC 5.60 0.80 BASIC 0.45 0.60 0.75 0.10 1.40 0.37 0.15 1.45 0.45 0.20
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ICS8430-11
700MHZ, JITTER LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Marking ICS8430DY-11 ICS8430DY-11 Package Lead LQFP Lead LQFP Tape Reel Count tray 1000 Temperature 70°C 70°C
TABLE ORDERING INFORMATION
Part/Order Number ICS8430DY-11 ICS8430DY-11T
While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial applications. other applications such those requiring extended temperature range, high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 8430DY-11
REV. JANUARY 2002

700MHZ, JITTER LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER FEATUR

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