700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

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700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

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ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
FEATURES
Dual differential 3.3V LVPECL output Selectable crystal oscillator interface LVCMOS TEST_CLK TEST_CLK accept following input levels: LVCMOS LVTTL Maximum output frequency 700MHz Maximum crystal TEST_CLK input frequency 25MHz range: 200MHz 700MHz Parallel serial interface programming counter output dividers period jitter: TBDps (typical) Cycle-to-cycle jitter: 30ps (typical) 3.3V supply voltage 70°C ambient operating temperature
GENERAL DESCRIPTION
ICS8432-51 general purpose, dual output Crystal-to-3.3V Differential LVPECL High Frequency HiPerClockSSynthesizer member HiPerClockSfamily High Performance Clocks Solutions from ICS. ICS8432-51 selectable TEST_CLK crystal inputs. TEST_CLK input accepts LVCMOS LVTTL input levels translates them 3.3V LVPECL levels. operates frequency range 200MHz 700MHz. frequency programmed steps equal value input reference crystal frequency. output frequency programmed using serial parallel interfaces configuration logic. phase noise characteristics ICS8432-51 makes ideal clock source Gigabit Ethernet, Fiber Channel Infiniband applications.
BLOCK DIAGRAM
VCO_SEL
ASSIGNMENT
VCO_SEL nP_LOAD XTAL2
XTAL_SEL TEST_CLK XTAL1 XTAL2
TEST FOUT1 nFOUT1 VCCO FOUT0 nFOUT0
XTAL1 TEST_CLK XTAL_SEL VCCA S_LOAD S_DATA S_CLOCK
PHASE DETECTOR
FOUT0 nFOUT0 FOUT1 nFOUT1
ICS8432-51
S_LOAD S_DATA S_CLOCK nP_LOAD M0:M8 N0:N1
CONFIGURATION INTERFACE LOGIC
TEST
32-Lead LQFP 1.4mm package body Package View
Preliminary Information presented herein represents product prototyping pre-production. noted characteristics based initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves right change circuitry specifications without notice.
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700MHZ, CYRSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
NOTE: functional description that follows describes operation using 25MHz crystal. Valid loop divider values different crystal input frequencies defined Input Frequency Characteristics, Table NOTE
ICS8432-51 features fully integrated therefore requires external components setting loop bandwidth. fundamental crystal used input on-chip oscillator. output oscillator into phase detector. 25MHz crystal provides 25MHz phase detector reference frequency. operates over range 200MHz 700MHz. output loop divider also applied phase detector. phase detector loop filter divider force output frequency times reference frequency adjusting control voltage. Note that some values (either high low) will achieve lock. output scaled divider prior being sent each LVPECL output buffers. divider provides output duty cycle. programmable features ICS8432-51 support input modes programmable loop divider output divider. input operational modes parallel serial. Figure shows timing diagram each mode. parallel mode nP_LOAD input initially LOW. data inputs through passed directly ripple counter. LOW-to-HIGH transition nP_LOAD input data latched ripple counter remains loaded until next transition nP_LOAD until serial event occurs. result bits hardwired ripple counter specific default state that will automatically occur during power-up. TEST output when operating parallel input mode. relationship between frequency, crystal frequency loop divider defined follows: fVCO fxtal count required values through shown Table Programmable Frequency Function. Valid values which will achieve lock 25MHz reference defined frequency defined follows: FOUT fVCO fxtal Serial operation occurs when nP_LOAD HIGH S_LOAD LOW. shift register loaded sampling S_DATA bits with rising edge S_CLOCK. contents shift register loaded into ripple counter when S_LOAD transitions from LOW-to-HIGH. ripple counter divide values latched HIGH-to-LOW transition S_LOAD. S_LOAD held HIGH data S_DATA input passed directly ripple counter each rising edge S_CLOCK. serial mode used program bits test bits internal registers determine state TEST output follows: TEST Output S_Data Output divider CMOS Fout
S_DATA S_CLOCK S_LOAD
*NULL
M0:M8, N0:N1 nP_LOAD
Time
FIGURE PARALLEL SERIAL LOAD OPERATIONS
*NOTE: NULL timing slot must observed.
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700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Type Input Input Input Unused Power Output Power Output Power Output Input Input Input Input Power Input Input Input Input Input Pullup Pulldown Pulldown Pulldown Pulldown Pullup counter/divider inputs. Data latched LOW-to-HIGH transistion Pulldown nP_LOAD input. LVCMOS LVTTL interface levels. Pulldown Determines output divider value defined Table Function table. LVCMOS LVTTL interface levels. connect. Negative supply pins. Connect ground. Test output which ACTIVE serial mode operation. Output driven parallel mode. LVCMOS interface levels. Positive supply pin. Differential output synthesizer. 3.3V LVPECL interface levels. Output supply pin. Connect 3.3V. Differential output synthesizer. 3.3V LVPECL interface levels. Forces outputs LOW, does effect loaded values. LVCMOS LVTTL interface levels. Clocks serial data present S_DATA input into shift register rising edge S_CLK. Shift register serial input. Data sampled rising edge S_CLK. Controls transition data from shift register into ripple counter. LVCMOS LVTTL interface levels. Analog supply pin. Connect 3.3V. Selects between ystal test inputs reference source. LVCMOS LVTTL interface levels. Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW. ystal oscillator inputs. Parallel load input. Determines when data present M8:M0 Pulldown loaded into ripple counter, when data present N1:N0 sets output divide value. LVCMOS LVTTL interface levels. Determines whether synthesizer bypass mode. Pullup LVCMOS LVTTL interface levels. Description
TABLE DESCRIPTIONS
Number Name TEST FOUT1, nFOUT1 VCCO FOUT0, nFOUT0 S_CLOCK S_DATA S_LOAD VCCA XTAL_SEL TEST_CLK XTAL1, XTAL2 nP_LOAD VCO_SEL
Pulldown Test clock input. LVCMOS LVTTL interface levels.
NOTE: Pullup Pulldown refers internal input resistors. Table Characteristics, typical values.
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700MHZ, CYRSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Test Conditions Minimum Typical Maximum Units
TABLE CHARACTERISTICS
Symbol RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor
TABLE PARALLEL
nP_LOAD
SERIAL MODE FUNCTION TABLE
Inputs Conditions S_CLOCK S_DATA Reset. counters reset. Data inputs passed directly ripple counter output divider. TEST output forced LOW. Data latched into input registers remains loaded until next transition until serial event occurs. Serial input mode. Shift register loaded with data S_DATA each rising edge S_CLOCK. Contents shift register passed ripple counter output divider. Ripple counter output divide values latched. Parallel serial input affect shift registers. Data S_LOAD
Data
Data
Data
Data Data Data
TABLE PROGRAMMABLE FREQUENCY FUNCTION TABLE
Frequency (MHz) Count
NOTE These count values resulting frequency correspond ystal test clock input frequency 25MHz.
TABLE PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs
8432AY-51
Divider Value
Output Frequency (MHz) Minimum Maximum 87.5
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700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
4.6V -0.5V -0.5V VCCO 0.5V 47.9°C/W lfpm) -65°C 150°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Inputs, Outputs, VCCO Package Thermal Impedance, Storage Temperature, TSTG
Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
TABLE POWER SUPPLY CHARACTERISTICS, VCCA VCCO 3.3V±5%,
Symbol VCCA VCCO Parameter Positive Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Test Conditions Minimum 3.135 3.135 3.135
70°C
Maximum 3.465 3.465 3.465 Units
Typical
TABLE LVCMOS LVTTL CHARACTERISTICS, VCCA VCCO 3.3V±5%,
Symbol Parameter Input High Voltage Input Voltage Input High Current Test Conditions input pins, except XTAL1 XTAL2 input pins, except XTAL1 XTAL2 M0-M4, M6-M8, S_CLOCK, TEST_CLK, S_DATA, S_LOAD, nP_LOAD XTAL_SEL, VCO_SEL M0-M4, M6-M8, S_CLOCK, TEST_CLK, S_DATA, S_LOAD, nP_LOAD XTAL_SEL, VCO_SEL Output High Voltage Output Voltage TEST TEST Minimum -0.3 *VCCx 3.465V VCCx 3.465V VCCx 3.465V, VCCx 3.465V, VCCx 3.135V, -36mA VCCx 3.135V, 36mA
70°C
Maximum Units
Typical
Input Current
-150
*NOTE VCCx denotes VCC, VCCA, VCCO.
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TABLE LVPECL CHARACTERISTICS, VCCA VCCO 3.3V±5%,
Symbol VSWING Parameter Output High Voltage; NOTE Output Voltage; NOTE Peak-to-Peak Output Voltage Swing Test Conditions
70°C
Typical Maximum VCCO VCCO -1.6 0.85 Units
Minimum VCCO VCCO
NOTE Outputs terminated with VCCO
TABLE INPUT FREQUENCY CHARACTERISTICS, VCCA VCCO 3.3V±5%,
Symbol Parameter TEST_CLK; NOTE Maximum Input Frequency XTAL1, XTAL2; NOTE Test Conditions
70°C
Typical Maximum Units
Minimum
S_CLOCK NOTE input ystal TEST_CLK frequency range value must operate within 200MHz 700MHz range. Using minimum input frequency 12MHz valid values Using maximum frequency 25MHz valid values
TABLE CRYSTAL CHARACTERISTICS
Parameter Mode Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Series Inductance Operating Temperature Range
Test Conditions
Minimum
Typical Maximum
Units
Fundamental
TABLE CHARACTERISTICS, VCCA VCCO 3.3V±5%,
Symbol FOUT Parameter Maximum Output Frequency Cycle-to-Cycle Jitter, RMS; NOTE Period Jitter, RMS; NOTE Output Skew; NOTE Output Rise Time Output Fall Time nP_LOAD Setup Time S_DATA S_CLOCK S_CLOCK S_LOAD nP_LOAD Hold Time Output Duty Cycle S_DATA S_CLOCK S_CLOCK S_LOAD
70°C
Minimum Typical Maximum Units
Test Conditions
tjit(cc) tjit(per) tsk(o)
50MHz 50MHz
Lock Time tLOCK parameters measured 500MHz unless noted otherwise. NOTE Jitter performance using Xtal inputs. NOTE Defined skew between outputs same supply voltage with equal load conditions. Measured output differential cross points. NOTE This parameter defined accordance with JEDEC Standard
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700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
VCC, VCCA, VCCO
SCOPE
LVPECL
VCC, VCCA, VCCO 2.0V
-1.3V 0.135V
FIGURE 3.3V OUTPUT LOAD TEST CIRCUIT
nFOUTx
FOUTx nFOUTy
FOUTy
tsk(o)
FIGURE OUTPUT SKEW
SWING
Clock Inputs Outputs
FIGURE INPUT
OUTPUT RISE
FALL TIME
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nFOUTx TEST, FOUTx
Pulse Width
PERIOD
PERIOD
FIGURE tPERIOD
IDEAL OUTPUT
Vref
ACTUAL OUTPUT
tjit(per) tcycle
nFOUTx
FOUTx
tcycle
jit(cc) tcycle -tcycle
FIGURE Cycle-to-Cycle Jitter
8432AY-51
Vref
cycle
where nominal output frequency tcycle cycle within sample measured controlled edges
FIGURE Period Jitter
tcycle
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700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER APPLICATIONS
STORAGE AREA NETWORKS
variety technologies used interconnection elements within SAN. tables below lists common frequencies used well settings ICS8432-51 generate appropriate frequency.
Table Common SANs Applications Frequencies
Interconnect Technology Gigabit Ethernet Fibre Channel Infiniband Clock Rate 1.25 1.0625 2.1250 Reference Freq. SERDES (MHz) 125, 250, 156.25 106.25, 53.125, 132.81 125, Crystal Frequency (MHz) 19.53 16.6, 26.563
Table Configuration Details SANs Applications
Interconnect Technology Crystal Frequency (MHz) Gigabit Ethernet 19.53 Fiber Channel Fiber Channel Infiniband 16.6 106.25 132.81 ICS8432-01 Output Frequency SERDES (MHz) 156.25 53.125 ICS8432-51 Settings
POWER SUPPLY FILTERING TECHNIQUES
high speed analog circuitry, power supply pins vulnerable random noise. ICS8432-51 provides separate power supplies isolate high switching noise from outputs internal PLL. VCC, VCCA, VCCO should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, better power supply isolation required. Figure illustrates along with 10µF .01µF bypass capacitor should connected each power supply pin.
8432AY-51
3.3V .01µF .01µF
FIGURE POWER SUPPLY FILTERING REV.
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ICS8432-51
700MHZ, CYRSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
TERMINATION LVPECL OUTPUTS
drive transmission lines. Matched impedance techniques should used maximize operating frequency minimize signal distortion. There simple termination schemes. Figures show different layouts which recommended only guidelines. Other suitable clock layouts exist would recommended that board designers simulate guarantee compatibility across printed circuit clock component process variations.
3.3V
clock layout topology shown below typical termination LVPECL outputs. different layouts mentioned recommended only guidelines. FOUT nFOUT impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors current path ground) current sources must used functionality. These outputs designed
FOUT
FOUT
(VOH
FIGURE LVPECL OUTPUT TERMINATION
schematic ICS8432-51 layout example used this layout guideline shown Figure ICS8432-51 recommended board layout this example shown Figure This layout example used general guideline. layout actual system will depend selected component types, density components, density traces, stacking P.C. board.
0.01u REF_IN XTAL_SEL S_LOAD S_DATA S_CLOCK
TEST FOUT1 nFOUT1 VCCO FOUT0 nFOUT0
VCO_SEL nP_LOAD XTAL2
FOUT FOUTN
8432-01
TEST
0.1u
FIGURE RECOMMENDED SCHEMATIC LAYOUT
8432AY-51
0.1u
FIGURE LVPECL OUTPUT TERMINATION
LAYOUT GUIDELINE
XTAL1 REF_IN nXTAL_SEL VCCA S_LOAD S_DATA S_CLOCK
Termination
Termination (Not shown layout)
INTL2
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following component footprints used this layout example: resistors capacitors size 0603.
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
traces should routed first should locked prior routing other signals traces. traces with transmission lines FOUT nFOUT should have equal delay adjacent each other. Avoid sharp angles clock trace. Sharp angle turns cause characteristic impedance change transmission lines. Keep clock trace same layer. Whenever possible, avoid vias clock traces. trace affect trace characteristic impedance hence degrade signal quality. prevent cross talk, avoid routing other signal traces parallel with clock traces. running parallel traces unavoidable, allow more space between clock trace other signal trace. Make sure other signal trace routed between clock trace pair. matching termination resistors should located close receiver input pins possible. Other termination scheme also used shown this example.
POWER
GROUNDING
Place decoupling capacitors close possible power pins. space allows, placing decoupling capacitor component side preferred. This reduce unwanted inductance between decoupling capacitor power generated via. Maximize size power (ground) decoupling capacitor. Maximize number vias between power (ground) pads. This reduce inductance between power (ground) plane component power (ground) pins. VCCA shares same power supply with VCC, insert filter C11, between. Place this filter close VCCA possible.
CLOCK TRACES
TERMINATION
component placements, locations orientations should arranged achieve best clock signal quality. Poor clock signal quality degrade system performance cause system failure. synchronous high-speed digital system, clock signal less tolerable poor signal quality than other signals. ringing rising falling edge excessive ring back cause system failure. trace shape trace delay might restricted available space board component location. While routing traces, clock signal
CRYSTAL
crystal should located close possible pins (XTAL1) (XTAL2). trace length between should kept minimum avoid unwanted parasitic inductance capacitance. Other signal traces should routed near crystal traces.
VCCA Close input pins receiver TL1N
TL1N
TL1, traces equal length
FIGURE BOARD LAYOUT
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700MHZ, CYRSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS
This section provides information power dissipation junction temperature ICS8432-51. Equations example calculations also provided.
Power Dissipation. total power dissipation ICS8432-51 core power plus power dissipated load(s). following power dissipation 3.3V 3.465V, which gives worst case results. NOTE: Please refer Section details calculating power dissipated load.
Power (core)MAX VCC_MAX IEE_MAX 3.465V 110mA 381.2mW Power (outputs)MAX 30.2mW/Loaded Output pair outputs loaded, total power 30.2mW 60.4mW
Total Power_MAX (3.465V, with outputs switching) 381.2mW 60.4mW 441.6mW
Junction Temperature. Junction temperature, temperature junction bond wire bond directly affects reliability device. maximum recommended junction temperature HiPerClockSdevices 125°C.
equation follows: Pd_total Junction Temperature junction-to-ambient thermal resistance Pd_total Total device power dissipation (example calculation section above) Ambient Temperature order calculate junction temperature, appropriate junction-to-ambient thermal resistance must used Assuming moderate flow linear feet minute multi-layer board, appropriate value 42.1°C/W Table below. Therefore, ambient temperature 70°C with outputs switching 70°C 0.441W 42.1°C/W 88.6°C. This well below limit 125°C This calculation only example. will obviously vary depending number loaded outputs, supply voltage, flow, type board (single layer multi-layer).
Table Thermal Resistance 32-pin LQFP, Forced Convection
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W
55.9°C/W 42.1°C/W
50.1°C/W 39.4°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
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Calculations Equations.
purpose this section derive power dissipated into load. LVPECL output driver circuit termination shown Figure
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
VCCO
VOUT VCCO
FIGURE LVPECL DRIVER CIRCUIT
TERMINATION
calculate worst case power dissipation into load, following equations which assume load, termination voltage
Pd_H power dissipation when output drives high. Pd_L power dissipation when output drives low.
Pd_H Pd_L
OH_MAX
CCO_MAX
2V))/R
CCO_MAX
OH_MAX
OL_MAX
CCO_MAX
2V))/R
CCO_MAX
OL_MAX
logic high, VOUT Using
CCO_MAX
OH_MAX
CCO_MAX
1.0V
OH_MAX
3.465, this results
2.465V
logic low, VOUT Using
CCO_MAX
OL_MAX
CCO_MAX
1.7V
OL_MAX
3.465, this results
1.765V
Pd_H =[(2.465V (3.465V 2V))/50] (3.465V 2.465V) 20mW Pd_L =[(1.765V (3.465V 2V))/50] (3.465V 1.765V) 10.2mW Total Power Dissipation output pair Pd_H Pd_L 30.2mW
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700MHZ, CYRSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE JAVS. FLOW TABLE
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W
55.9°C/W 42.1°C/W
50.1°C/W 39.4°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
TRANSISTOR COUNT
transistor count ICS8432-51 3703
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700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE SUFFIX
TABLE PACKAGE DIMENSIONS
JEDEC VARIATION DIMENSIONS MILLIMETERS SYMBOL 0.45 -0.05 1.35 0.30 0.09 MINIMUM NOMINAL -1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 -0.75 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication MS-026
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700MHZ, CYRSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Marking ICS8432AY-51 ICS8432AY-51 Package Lead LQFP Lead LQFP Tape Reel Count tray 1000 Temperature 70°C 70°C
TABLE ORDERING INFORMATION
Part/Order Number ICS8432AY-51 ICS8432AY-51T
While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial applications. other applications such those requiring extended temperature range, high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 8432AY-51
REV. AUGUST 2001

700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

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