MK2049-34 Phase-Locked Loop (PLL) based clock synthesizer that accepts

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MK2049-34 Phase-Locked Loop (PLL) based clock synthesizer that accepts

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MK2049-34 Communications Clock
MK2049-34 Phase-Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With clock input reference, MK2049-34 generates ISDN, xDSL, other communications frequencies. This allows generation clocks frequency-locked phase-locked backplane clock, simplifying clock synchronization communications systems. MK2049-34 also accept input clock provide same output loop timing. outputs frequency locked together input. This part also jitter-attenuated Buffer capability. this mode, MK2049-34 ideal filtering jitter from video clocks other clocks with high jitter. ICS/MicroClock customize these devices many other different frequencies. Contact your ICS/MicroClock representative more details.
Packaged SOIC operation Fixed phase relationship selections Meets TR62411, ETS300 011, GR-1244 specification MTIE, Pull-in/Hold-in Range, Phase Transients, Jitter Generation Stratum Accepts multiple inputs: backplane clock, Loop Timing frequencies, 10-36 Locks ±100 (External mode) Buffer Mode allows jitter attenuation 10-36 input x1/x0.5 x2/x4 outputs Exact internal ratios enable zero error Output clock rates include ISDN, xDSL, submultiples MK2049-01, -02, more selections
Block Diagram
FS3:0
Clock Synthesis, Control, Jitter Attenuation Circuitry Output Buffer Output Buffer
ICLK Reference Crystal Crystal Oscillator
External/ Loop Timing
CLK/2
Output Buffer
(External Mode only)
FCAP
CAP1
CAP2
2049-34
Revision 091801
Integrated Circuit Systems, Inc. Race Street Jose 95126 www.icst.com
MK2049-34 Communications Clock
Assignment
FCAP CLK/2 CAP2 CAP1 ICLK
(300 mil) SOIC
Descriptions
Number Name Type Description FCAP CLK/2 ICLK CAP1 CAP2 Frequency Select Determines input/outputs tables page Crystal connection. Connect crystal shown tables page Connect +3.3V. Filter Capacitor. Connect 1000 ceramic capacitor ground. Connect +3.3V. Connect ground. Clock output determined status FS3:0 tables page Clock output determined status FS3:0 tables page Always CLK. Recovered clock output. Frequency Select Determines input/outputs tables page Frequency Select Determines input/outputs tables page Input clock connection. Connect backplane clock. Connect ground. Connect +3.3V. Connect ground. Connect 10-200k resistor ground. Contact 408-297-1201 recommended value your app. Frequency Select Determines input/outputs tables page Crystal connection. Connect crystal shown tables page
Connect loop filter ceramic capacitors resistor between this CAP2. Connect loop filter ceramic capacitors resistor between this CAP1.
Type:
crystal connections, Input, output, power supply connection, loop filter connections
2049-34
Revision 091801
Integrated Circuit Systems, Inc. Race Street Jose 95126 www.icst.com
MK2049-34 Communications Clock
Electrical Specifications
Parameter Conditions Minimum ABSOLUTE MAXIMUM RATINGS (Note Supply Voltage, Referenced Inputs Clock Outputs -0.5 Ambient Operating Temperature MK2049-34SI Soldering Temperature seconds Storage Temperature CHARACTERISTICS (VDD unless noted) Operating Voltage, 3.15 Input High Voltage, Input Voltage, Output High Voltage, VOH, CMOS level IOH=-4 VDD-0.4 Output High Voltage, IOH=-8 Output Voltage IOL=8 Operating Supply Current, Load, VDD=3.3V Short Circuit Current Each output Input Capacitance, FS3:0 CHARACTERISTICS (VDD unless noted) Input Frequency, External Mode, Note ICLK Input Clock Pulse Width Propagation Delay ICLK Output-Output Skew CLK/2 Output Clock Rise Time Output Clock Fall Time Output Clock Duty Cycle, High Time VDD/2, except Actual mean frequency error versus target clock selection Typical Maximum VDD+0.5 3.45 Units
8.000
Notes: Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage device. Prolonged exposure levels above operating limits below Absolute Maximums affect device reliability. loop timing modes buffer modes, tables page required input clock frequencies.
2049-34
Revision 091801
Integrated Circuit Systems, Inc. Race Street Jose 95126 www.icst.com
MK2049-34 Communications Clock
MK2049-34 Output Decoding Table External Mode (MHz)
ICLK CLK/2 1.544 2.048 22.368 17.184 19.44 16.384 17.664 18.688 7.68 10.752 10.24 38.88 3.088 4.096 44.736 34.368 38.88 32.768 35.328 37.376 15.36 21.504 20.48 77.76 Crystal 12.352 12.288 11.184 11.456 9.72 8.192 17.664 9.344 15.36 10.752 10.24 9.72
MK2049-34 Output Decoding Table Loop Timing Mode (MHz)
ICLK 1.544 2.048 CLK/2 1.544 2.048 3.088 4.096 Crystal 12.352 12.288
MK2049-34 Output Decoding Table Buffer Mode (MHz)
ICLK CLK/2 ICLK/2 2*ICLK ICLK 4*ICLK Crystal ICLK/2 ICLK
connect directly ground, connect directly VDD. Crystal connected pins clock input applied
2049-34
Revision 091801
Integrated Circuit Systems, Inc. Race Street Jose 95126 www.icst.com
MK2049-34 Communications Clock
OPERATING MODES
MK2049-34 three operating modes: External, Loop Timing, Buffer. Although each mode uses input clock generate various output clocks, there important differences their input crystal requirements. External Mode MK2049-34 accepts external clock will produce number common communication clock frequencies. input clock does need have duty cycle; "high" "on" pulse narrow acceptable. MK2049-34, rising edges CLK/2 both aligned with rising edge ICLK; refer Figure more details. Loop Timing Mode This mode used remove jitter from standard high-frequency communication clocks. inputs, CLK/2 output will same input frequency, with twice input frequency. Buffer Mode Unlike other modes that accept only single specified input frequency, Buffer Mode will accept wider range input clocks. input jitter attenuated, outputs CLK/2 also provide option getting input frequency. example, this mode used remove jitter from clock, generating low-jitter 13.5 outputs.
INPUT OUTPUT SYNCHRONIZATION
shown tables page MK2049-34 offers Zero Delay feature selections. There internal feedback path between ICLK output clocks, providing fixed phase relationship between input output, requirement many communications systems. rising edge ICLK will aligned with rising edges CLK/2. used this illustration, same true selections Loop Timing Buffer modes.)
ICLK kHz)
(MHz)
CLK/2(MHz)
Figure MK2049-34 Input Output Clock Waveforms
2049-34
Revision 091801
Integrated Circuit Systems, Inc. Race Street Jose 95126 www.icst.com
MK2049-34 Communications Clock
Measuring Zero Delay MK2049
MK2049-34 produces low-jitter output clocks. addition, this part very bandwidth-on order Hertz. Since most input clocks will have high jitter, this make measuring input-to-output skew (zero delay feature) very difficult. MK2049 designed reject input jitter; when input output clocks both displayed oscilloscope, they appear locked because scope trigger point constantly changing with input jitter. fact, input output clocks probably locked, MK2049 will have zero delay average position input clock. order this clearly, jitter input clock necessary. Most frequency sources SUITABLE this since they have high jitter frequencies. modes, output clocks frequency-locked input. output will remain specified output
Frequency Locking Input
modes, output clocks frequency-locked input. output will remain specified output frequency long combined variation input frequency crystal does exceed ppm. example, crystal vary (initial accuracy temperature aging), then input frequency vary still have output clock remain frequency-locked.
2049-34
Revision 091801
Integrated Circuit Systems, Inc. Race Street Jose 95126 www.icst.com
MK2049-34 Communications Clock
BOARD LAYOUT
proper board layout critical successful MK2049. particular, CAP1 CAP2 pins very sensitive noise leakage (CAP2 most sensitive). Traces must short possible capacitors resistor must mounted next device shown below. capacitor shown between pins between pins power supply decoupling capacitors. high frequency output clocks pins should have series termination connected close pin. Additional improvements will come from keeping components same side board, minimizing vias through other signal layers, routing other signals away from MK2049. also refer MAN05 additional suggestions layout crystal section. crystal traces should include pads small capacitors from ground; these used adjust stray capacitance board match crystal load capacitance. typical telecom reference frequency accurate much less than ppm, MK2049 lock properly even board capacitance adjusted with these fixed capacitors. However, MicroClock recommends that adjustment capacitors included minimize effects variation individual crystals, temperature, aging. value these capacitors (typically determined once given board layout, using procedure described section titled "Determining Crystal Frequency Adjustment Capacitors".
Optional; text
resist. resist.
Cutout ground power plane. Route traces away from this area.
resist. resist.
=connect =connect
Figure Typical MK2049-34 Layout
2049-34
Revision 091801
Integrated Circuit Systems, Inc. Race Street Jose 95126 www.icst.com
MK2049-34 Communications Clock
EXTERNAL COMPONENT SELECTION MK2049-34 requires minimum number external components proper operation. Decoupling capacitors 0.01µF must connected between pins close chip (especially pins 17), series terminating resistors should used clock outputs with traces longer than inch (assuming traces). selection additional external components described following sections.
Loop Filter Components
external loop filter should connected between CAP1 CAP2 shown Figure below, close chip possible. High quality ceramic capacitors recommended. type polarized electrolytic capacitor. Ceramic capacitors should have dielectric. Another alternative Panasonic polymer dielectric series; their part number ECHU1C104JB5. Avoid high-K dielectrics like X7R; these other ceramics which have piezolectric properties allow mechanical vibration system increase output jitter because mechanical energy converted directly voltage noise input.
CAP2 CAP1 Figure Loop Filter Component Values (Typical component values shown. Contact MicroClock applications department (408)297-1201 recommended values your application)
Crystal Operation
MK2049 operates phase locking input signal VCXO which consists special recommended crystal integrated VCXO oscillator circuit MK2049. achieve best performance reliability, layout guidelines shown previous page must closely followed. frequency oscillation quartz crystal determined load capacitors connected MK2049 variable load capacitors on-chip which "pull", change frequency crystal. External stray capacitance must kept minimum ensure maximum pullability crystal. achieve this, layout should short traces between MK2049 crystal. VCXO operate correctly, crystal properly specified matched MK2049-34 must used. more information, including list recommended crystals, refer application note MAN05.
2049-34
Revision 091801
Integrated Circuit Systems, Inc. Race Street Jose 95126 www.icst.com
MK2049-34 Communications Clock
EXTERNAL COMPONENT SELECTION (continued)
Determining Crystal Frequency Adjustment Capacitors
determine crystal adjustment capacitor values, will need board your final layout, frequency counter capable less than resolution accuracy, power supplies, some samples crystals which plan production, along with measured initial accuracy each crystal specified load capacitance, determine value crystal capacitors: Connect MK2049 Connect MK2049 second power supply. Adjust voltage Measure record frequency CLK/2 output Adjust voltage Measure record frequency same output. calculate centering error:
Centering error
(f3.3V ftarget) 0.0V target) errorxtal ftarget
actual initial accuracy ppm) crystal being measured.
Where ftarget 44.736000 MHz, example, errorxtal
centering error less than ppm, adjustment needed. centering error more than negative, board much stray capacitance will need redone with layout reduce stray capacitance. (The crystal re-specified lower load capacitance instead. Contact details.) centering error more than positive, identical fixed centering capacitors from each crystal ground. value each these caps given External Capacitor 2*(centering error)/(trim sensitivity) Trim sensitivity parameter which supplied your crystal vendor. know value, assume ppm/pF. After changes, repeat measurement verify that remaining error acceptably (less than ppm). applications department perform this procedure your board. Call 408-295-9800, will arrange send board (stuffed unstuffed) your crystals. will calculate value capacitors needed.
2049-34
Revision 091801
Integrated Circuit Systems, Inc. Race Street Jose 95126 www.icst.com
MK2049-34 Communications Clock
Package Outline Package Dimensions (For current dimensional specifications, JEDEC Publication 95.)
SOIC
Inches Symbol -0.0040 0.013 0.007 0.496 0.291 0.394 0.01 0.016 0.104 -0.020 0.013 0.512 0.299 0.419 0.029 0.050 Millimeters -0.10 0.33 0.18 12.60 7.40 10.01 0.25 0.41 2.65 -0.51 0.33 13.00 7.60 10.64 0.74 1.27
INDEX AREA
.050
1.27
Ordering Information
Part/Order Number MK2049-34SI MK2049-34SITR Marking MK2049-34SI MK2049-34SI Package SOIC Tape Reel Temperature
While information presented herein been checked both accuracy reliability, Integrated Circuit Systems (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial applications. other applications such those requiring extended temperature range, high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments.
2049-34
Revision 091801
Integrated Circuit Systems, Inc. Race Street Jose 95126 www.icst.com

MK2049-34 Phase-Locked Loop (PLL) based clock synthesizer that accepts

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