MK2049 Phase-Locked Loop (PLL) based clock synthesizer, which accepts
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MK2049-01 Communications Clock
MK2049 Phase-Locked Loop (PLL) based clock synthesizer, which accepts clock input reference generates frequencies. device also accept input clock provide same output loop timing. outputs frequency locked together input. This allows generation locked clocks backplane clock, simplifying clock distribution communications systems. customize this device many other different frequencies. Contact your representative more details. fixed input-output phase relationship, refer MK2049-02, -03, -3x. MK2049-3x devices.
Packaged SOIC Meets TR62411, ETS300 011, GR-1244 specification MTIE, Pull-in/Hold-in Range, Phase Transients, Jitter Generation Stratum Accepts multiple inputs: backplane clock Loop Timing frequencies Locks ±100 (External mode) Exact internal ratios eliminate need external dividers Zero synthesis error output clocks. Output clock rates include OC3÷8 operation Offered Commercial Industrial temperature versions
Block Diagram
Clock Synthesis, Control, Jitter Attenuation Circuitry Output Buffer CLK1
FS3:0
ICLK
External/ Loop Timing
Output Buffer
CLK2
Reference Crystal
Crystal Oscillator CAP1 CAP2
Output Buffer
2049-01
Revision 091801
Integrated Circuit Systems, Inc. Race Street Jose 95126 (408)295-9800tel
MK2049-01 Communications Clock
Assignment
CLK2 CLK1 CAP2 CAP1 ICLK
Output Decoding Table External Mode (MHz)
Input CLK1 CLK2 Crystal
1.544 2.048 22.368 17.184 19.44
3.088 4.096 44.736 34.368 38.88
12.288 12.288 12.288 12.288 12.96
Output Decoding Table Loop Timing Mode (MHz)
Input CLK1 CLK2 Crystal
(300 mil) SOIC
1.544 2.048 44.736 34.368
1.544 2.048 22.368 17.184
3.088 4.096 44.736 34.368
12.288 12.288 12.288 12.288
Descriptions
Number Name CLK2 CLK1 ICLK CAP1 CAP2 Type Description
connect directly ground, connect directly VDD. Crystal applied pins clock input applied
Frequency Select Determines input/outputs tables above. Crystal conection. Connect 12.288 12.96 crystal. Crystal conection. Connect 12.288 12.96 crystal. Connect +5V. Connect +5V. Connect +5V. Connect ground. Clock output determined status FS3:0 tables above. Clock output determined status FS3:0 tables above. CLK2 divided Recovered clock output. External mode only. Frequency Select Determines input/outputs tables above. Frequency Select Determines input/outputs tables above. Input clock connection. Connect backplane Loop Timing clock. Connect ground. Connect +5V. Connect 0.030 ceramic capacitor resistor series between this CAP2. Connect ground. Connect 0.030 ceramic capacitor resistor series between this CAP1. Connect ground. Frequency Select Determines input/outputs tables above.
Type: Input, output, power supply connection, loop filter connection
2049-01
Revision 091801
Integrated Circuit Systems, Inc. Race Street Jose 95126 (408)295-9800tel
MK2049-01 Communications Clock
Electrical Specifications
Parameter Conditions Minimum Typical Maximum ABSOLUTE MAXIMUM RATINGS (Note Supply Voltage, Referenced Inputs Clock Outputs -0.5 VDD+0.5 Ambient Operating Temperature MK2049-01SI only Soldering Temperature seconds Storage Temperature CHARACTERISTICS (VDD unless noted) Operating Voltage, 4.75 5.25 Input High Voltage, Input Voltage, Output High Voltage IOH=-4mA VDD-0.4 Output High Voltage IOH=-25mA Output Voltage IOL=25mA Operating Supply Current, Load, VDD=5.0V Short Circuit Current Each output ±100 Input Capacitance, FS3:0 CHARACTERISTICS (VDD unless noted) Input Frequency, External Mode, Note ICLK 8.0000 Input Crystal Frequency 12.2880 Input Crystal Frequency Selection 0111 12.9600 Output Clock Rise Time 2.0V Output Clock Fall Time 0.8V Output Clock Duty Cycle, High Time VDD/2 Actual mean frequency error versus target clock selection Units
Notes: Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage device. Prolonged exposure levels above operating limits below Absolute Maximums affect device reliability. table page input frequencies required loop timing mode.
2049-01
Revision 091801
Integrated Circuit Systems, Inc. Race Street Jose 95126 (408)295-9800tel
MK2049-01 Communications Clock
OPERATING MODES
MK2049-01 operating modes: External Loop Timing. Although both modes input clock generate various output clocks, there important differences their input requirements. External Mode MK2049-01 accepts external clock will produce number common communication clock frequencies. input clock does need have duty cycle; "high" "on" pulse narrow acceptable. Loop Timing Mode This mode used remove jitter from standard high-frequency communication clocks. inputs, CLK1 output will same input frequency, with CLK2 twice input frequency. inputs, CLK1 will input frequency CLK2 will same input frequency.
FREQUENCY LOCKING INPUT both modes, output clocks frequency-locked input. output will remain specified output frequency long combined variation input frequency crystal does exceed ppm. example, crystal vary (initial accuracy temperature aging), then input frequency vary still have output clock remain frequency-locked.
INPUT OUTPUT SYNCHRONIZATION rising edges CLK1 CLK2 have fixed phase alignment with rising edge ICLK. Each time device powered-up, phase relationship could change. Refer other MK2049 versions (e.g., MK2049-02, -03, -34) input-output phase alignment important your application.
2049-01
Revision 091801
Integrated Circuit Systems, Inc. Race Street Jose 95126 (408)295-9800tel
MK2049-01 Communications Clock
LAYOUT EXTERNAL COMPONENTS
MK2049-01 requires minimum number external components proper operation. Decoupling capacitors 0.01µF must connected between pins close chip (especially pins 17), series terminating resistors should used clock outputs with traces longer than inch (assuming traces). loop filter components should connected close chip possible. Refer next section more information. Board Layout proper board layout critical successful MK2049. particular, CAP1 CAP2 pins very sensitive noise leakage (CAP2 most sensitive). Traces must short possible capacitors resistor must mounted next device shown below. capacitor shown between pins between pins power supply decoupling capacitors. high frequency output clocks pins should have series termination connected close pin. Additional improvements will come from keeping components same side board, minimizing vias through other signal layers, routing other signals away from MK2049. also refer MAN05 additional suggestions layout crystal section. crystal traces should include pads small capacitors from ground; these used adjust stray capacitance board match crystal load capacitance. typical telecom reference frequency accurate much less than ppm, MK2049 lock properly even board capacitance adjusted with these fixed capacitors. However, MicroClock recommends that adjustment capacitors included minimize effects variation individual crystals, temperature, aging. value these capacitors (typically determined once given board layout, using procedure described later this section, titled "Determining Crystal Frequency Adjustment Capacitors".
Optional; text
resist. resist.
Cutout ground power plane. Route traces away from this area.
resist.
=connect =connect
Figure MK2049-01 Layout Example
2049-01
Revision 091801
Integrated Circuit Systems, Inc. Race Street Jose 95126 (408)295-9800tel
MK2049-01 Communications Clock
LAYOUT EXTERNAL COMPONENTS (continued)
Loop Filter Components external loop filter should connected between CAP1 CAP2 shown Figure below, close chip possible. sure follow recommendations capacitor types described page
CAP2 CAP1 0.030
Figure Loop Filter component values most configurations Typical component values shown. Contact applications department (408)297-1201 recommended values your application.
Crystal Operation MK2049 operates phase locking input signal VCXO which consists special recommended crystal integrated VCXO oscillator circuit MK2049. achieve best performance reliability, layout guidelines shown previous page must closely followed. frequency oscillation quartz crystal determined load capacitors connected MK2049 variable load capacitors on-chip which "pull", change frequency crystal. External stray capacitance must kept minimum ensure maximum pullability crystal. achieve this, layout should short traces between MK2049 crystal. VCXO operate correctly, crystal properly specified matched MK2049-01 must used. more information, including list recommended crystals, refer application note MAN05.
2049-01
Revision 091801
Integrated Circuit Systems, Inc. Race Street Jose 95126 (408)295-9800tel
MK2049-01 Communications Clock
LAYOUT EXTERNAL COMPONENTS (continued)
Determining Crystal Frequency Adjustment Capacitors determine crystal adjustment capacitor values, will need board your final layout, frequency counter capable less than resolution accuracy, power supplies, some samples crystals which plan production, along with measured initial accuracy each crystal specified load capacitance, determine value crystal capacitors: Connect MK2049 Connect MK2049 second power supply. Adjust voltage Measure record frequency CLK1 CLK2 output Adjust voltage Measure record frequency same output. calculate centering error:
Centering error
3.0V target) 0.0V target) target
error xtal
Where ftarget 44.736000 MHz, example, errorxtal
actual initial accuracy ppm) crystal being measured.
centering error less than ppm, adjustment needed. centering error more than negative, board much stray capacitance will need redone with layout reduce stray capacitance. (The crystal re-specified lower load capacitance instead. Contact MicroClock details.) centering error more than positive, identical fixed centering capacitors from each crystal ground. value each these caps given External Capacitor 2*(centering error)/(trim sensitivity) Trim sensitivity parameter which supplied your crystal vendor. know value, assume ppm/pF. After changes, repeat measurement verify that remaining error acceptably (less than ppm). MicroClock Applications department perform this procedure your board. Call 408-295-9800, will arrange send board (stuffed unstuffed) your crystals. will calculate value capacitors needed.
2049-01
Revision 091801
Integrated Circuit Systems, Inc. Race Street Jose 95126 (408)295-9800tel
MK2049-01 Communications Clock
Input Jitter Modulation Frequency (Hz) 1000 2000 4000 8000 10000 16000 32000 64000 Input Jitter Magnitude (UIp-p) 7.75 3.98 1.74 Measured Jitter Output (UIp-p) Output Jitter Jitter Magnitude Attenuation (UIp-p) (dB) 1.07 19.41 0.56 25.04 0.36 28.87 0.147 36.65 0.037 48.64 0.016 55.92 0.01 60.00 0.01 60.00 0.01 60.00 0.01 60.00 0.01 57.79 0.01 52.00 0.01 44.81
Table Jitter results (1.544 MHz) reference frequency, measured HP3785B output filter).
Input Jitter Modulation Frequency (Hz) 1000 2000 4000 8000 10000 16000 32000 64000 128000 192000 256000
Input Jitter Magnitude (UIp-p) 10.5 10.5 10.5 10.5 10.5 10.5 10.5 10.5 10.5 10.5 10.5 10.5 10.5
Measured Jitter Output (UIp-p) Output Jitter Jitter Magnitude Attenuation (UIp-p) (dB) 0.071 43.4 0.07 43.52 0.144 37.26 0.12 38.84 0.08 42.36 0.07 43.52 0.066 44.03 0.065 44.17 0.06 44.86 0.06 44.86 0.058 45.16 0.06 44.86 0.062 44.58
Table Jitter results (44.736 MHz) reference frequency, measured HP3785B -1.1 output filter).
2049-01
Revision 091801
Integrated Circuit Systems, Inc. Race Street Jose 95126 (408)295-9800tel
MK2049-01 Communications Clock
Input Jitter Modulation Frequency (Hz) 1000 2000 5000 10000 15000 25000 50000 75000 Measured Jitter Output (UIp-p) Output Jitter Jitter Magnitude Attenuation (UIp-p) (dB) 0.018 38.42 0.014 40.60 0.01 43.52 0.01 43.52 0.007 46.62 0.006 47.96 0.006 47.96 0.006 41.58 0.006 35.56 0.006 32.04 0.006 30.46 0.006 30.46 0.006 30.46
Input Jitter Magnitude (UIp-p) 0.72 0.36 0.24 0.20 0.20 0.20
Table Jitter results (2.048 MHz) reference frequency, measured HP3785A (100 -800 output filter).
Input Jitter Modulation Frequency (Hz) 1000 2000 5000 10000 15000 25000 50000 75000 100000
Input Jitter Magnitude (UIp-p) 0.72 0.36 0.24
Measured Jitter Output (UIp-p) Output Jitter Jitter Magnitude Attenuation (UIp-p) (dB) 0.113 22.46 0.094 24.06 0.077 25.79 0.069 26.74 0.07 26.62 0.068 20.5 0.007 34.22 0.007 30.7 0.007 29.12 0.007 29.12 0.007 29.12 0.007 29.12
Table Jitter results (34.368 MHz) reference frequency, measured HP3785A (100 output filter).
2049-01
Revision 091801
Integrated Circuit Systems, Inc. Race Street Jose 95126 (408)295-9800tel
MK2049-01 Communications Clock
Package Outline Package Dimensions (For current dimensional specifications, JEDEC Publication 95.)
SOIC
Inches Symbol -0.0040 0.013 0.007 0.496 0.291 0.394 0.01 0.016 0.104 -0.020 0.013 0.512 0.299 0.419 0.029 0.050 Millimeters -0.10 0.33 0.18 12.60 7.40 10.01 0.25 0.41 2.65 -0.51 0.33 13.00 7.60 10.64 0.74 1.27
INDEX AREA
.050
1.27
Ordering Information
Part/Order Number MK2049-01S MK2049-01STR MK2049-01SI MK2049-01SITR Marking MK2049-01S MK2049-01S MK2049-01SI MK2049-01SI Package SOIC Tape Reel SOIC Tape Reel Temperature
While information presented herein been checked both accuracy reliability, assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial applications. other applications such those requiring extended temperature range, high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments.
2049-01
Revision 091801
Integrated Circuit Systems, Inc. Race Street Jose 95126 (408)295-9800tel
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