Phase Noise Clock Generator MK1581-01 provides synchronization ti

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Phase Noise Clock Generator MK1581-01 provides synchronization ti

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MK1581-01
Phase Noise Clock Generator
MK1581-01 provides synchronization timing control based network access multitrunk telecommunication systems. device accepts frame clock input uses on-chip VCXO produce synchronized phase noise clock output. This monolithic combined with external inexpensive quartz crystal, used replace more costly hybrid VCXO retiming module. Through selection external loop filter components values, device tailored meet system's clock jitter attenuation requirements. Low-pass jitter attenuation characteristics range possible.
Features
Generates (1.544 MHz) (2.048 MHz)
output clock from 8kHz frame clock input Configurable jitter attenuation characteristics, excellent Stratum source de-jitter circuit VCXO-based clock generation ensures very jitter phase noise generation Output clock phase frequency locked input reference clock +115ppm minimum crystal frequency pullability range, using recommended crystal Industrial temperature range power CMOS technology TSSOP package Single 3.3V power supply
Block Diagram
ullable xtal
Phase etector
z_IN
ivider
eedb ivid
CHGP
1581-01
Revision 091901
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 295-9800 www.icst.com
Preliminary
MK1581-01 Phase Noise Clock Generator
Assignment
CHGP 8kHz_IN ISET
Output Clock Selection Table
Input Clock Output Clock (MHz) 1.544 2.048 Crystal Used (MHz) 24.704 24.576
4.40 body, 0.65 pitch TSSOP
Descriptions
Number
Name
CHGP ISET 8kHz_IN
Type
Power Power Power Input Power Power Power Output Power Power Output Input Input
Power Supply. Connect +3.3V. Power Supply. Connect +3.3V. Power Supply. Connect +3.3V. VCXO Control Voltage Input. Connect this CHGP external loop filter shown this data sheet. Connect ground Connect ground Connect ground Charge Pump Output. Connect this external loop filter VIN. Charge pump current setting node, connection setting resistor. Connect ground. Connect ground. Clock Output Output Frequency Selection. Determines output frequency table above. Internal pull-up. reference clock input. Crystal Output. Connect this specified crystal. Crystal Input. Connect this specified crystal.
1581-01
Revision 091901
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 295-9800 www.icst.com
Preliminary
MK1581-01 Phase Noise Clock Generator
Functional MK1581-01 clock generator that generates reference clock directly from internal VCXO circuit that works conjunction with external quartz crystal. VCXO output frequency phase controlled internal (Phase Locked Loop) circuit, enabling device perform clock regeneration from input reference clock. Most typical clock devices internal (Voltage Controlled Oscillator) output clock generation. using VCXO with external crystal, MK1581-01 able generate jitter, phase-noise output clock. bandwidth capability circuit serves provide input clock jitter attenuation enables stable operation with frequency input reference clock. internal VCXO circuit requires external pullable crystal operation. External loop filter components enable configuration with loop bandwidth.
capacitance. MK1581-01 incorporates variable load capacitors on-chip which "pull", change, frequency crystal. crystals specified with MK1581-01 designed have zero frequency error when total on-chip stray capacitance 14pF. achieve this, layout should short traces between MK1581-01 crystal. complete description recommended crystal parameters shown below. Recommended Crystal Parameters: Operating Temperature Range Commercial Applications Industrial Applications Initial Accuracy 25°C Temperature Stability Aging Load Capacitance Shunt Capacitance, C0/C1 Ratio Equivalent Series Resistance 70°C 85°C
Application Information
Output Frequency Configuration
MK1581-01 configured generate either 1.544 clock 2.048 clock from 8kHz input clock. Please refer Output Clock Selection Table Page Input according this table, external crystal frequency. Please refer Quartz Crystal section this page regarding external crystal requirements. obtain list qualified crystal devices that meet these requirements, please contact MicroClock applications department.
Loop Filter Components
phased-locked loop (PLL) control system that keeps frequency phase locked with input reference clock. Like control systems, analog circuits loop filter establish operating stability. MK1581-01 uses external loop filter components following reasons: Larger loop filter capacitor values used, allowing lower loop bandwidth. This enables lower input clock reference frequencies also input clock jitter attenuation capabilities. Larger loop filter capacitors also allow higher loop damping factors when less passband peaking desired. loop filter values user selected optimize loop response characteristics given application. Referencing External Component Schematic this page, external loop filter made components RSET establishes charge pump current therefore influences loop filter characteristics.
Quartz Crystal
important that correct type quartz crystal used with MK1581-01. Failure result reduced frequency pullability range, inability loop lock, excessive output phase jitter. MK1581-01 operates phase-locking VCXO circuit input signal selected ICLK input. VCXO consists external crystal integrated VCXO oscillator circuit. achieve best performance reliability, crystal device with recommended parameters (shown below) must used, layout guidelines discussed Layout Recommendations section must followed. frequency oscillation quartz crystal determined external load
1581-01
Revision 091901
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 295-9800 www.icst.com
Preliminary
MK1581-01 Phase Noise Clock Generator
External Component Schematic
on't efer tiona tion)
z_IN
CHGP
Recommended Loop Filter Values Output Frequency Selection
Crystal Output Freq Multiplier 1.544 2.048 3088 3072 RSET Loop Bandwidth
(-3dB point)
Damping Factor
1581-01
Revision 091901
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 295-9800 www.icst.com
Preliminary
MK1581-01 Phase Noise Clock Generator
"normalized" loop bandwidth calculated follows: "normalized" bandwidth (NBW) equation above does take into account effects damping factor second pole. approximately equal actual -3dB bandwidth loop when damping factor about very small. most applications, about actual -3dB bandwidth. However, does provide useful approximation filter performance. loop damping factor calculated follows: Damping Factor Where: Value resistor loop filter (Ohms) Charge pump current (amps) (refer Charge Pump Current Table, below) Crystal multiplier shown above table Value capacitor loop filter (Farads) general rule, following relationship should maintained between components loop filter:
Special considerations must made choosing loop components loop capacitors should low-leakage type avoid leakage-induced phase noise. this reason, type polarized electrolytic capacitors. Microphonics (mechanical board vibration) also induce output phase noise, especially when loop bandwidth less than 1kHz. this reason, ceramic capacitors should have dielectric. Avoid high-K dielectrics like X7R. These some other ceramics have piezoelectric properties that convert mechanical vibration into voltage noise that interferes with VCXO operation. larger loop capacitor values such film types made Panasonic, metal poly types made Murata Cornell Dubilier recommended. questions changes regarding loop filter characteristics, please contact your sales area FAE, MicroClock Applications.
Series Termination Resistor
Clock output traces over inch should series termination. series terminate trace commonly used trace impedance), place resistor series with clock line, close clock output possible. nominal impedance clock output (The optional series termination resistor shown External Component Schematic.)
Decoupling Capacitors
with high performance mixed-signal MK1581-01 must isolated from system power supply noise perform optimally. Decoupling capacitors 0.01µF must connected between each ground plane. further guard against interfering system supply noise, MK1581-01 should common connection power plane shown diagram next page. ferrite bead bulk capacitor help reduce lower frequency noise supply that lead output clock phase modulation.
Charge Pump Current Table
RSET Charge Pump Current (ICP)
1581-01
Revision 091901
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 295-9800 www.icst.com
Preliminary
MK1581-01 Phase Noise Clock Generator
Recommended Power Supply Connection Optimal Device Performance
onnection 3.3V lane Ferrite
should trace ground via. Distance ferrite bead bulk decoupling from device less critical. loop filter components must also placed close CHGP pins. should closest device. Coupling noise from other system signal traces should minimized keeping traces short away from active signal traces. vias should avoided. external crystal should mounted just next device with short traces. traces should routed next each other with minimum spaces, instead they should separated away from other traces. minimize series termination resistor, needed, should placed close clock output. optimum layout with components same side board, minimizing vias through other signal layers (the ferrite bead bulk decoupling capacitor mounted back). Other signal traces should routed away from MK1581-01. This includes signal traces just underneath device, layers adjacent ground plane layer used device. Applications Note MAN05 also referenced additional suggestions layout crystal section.
ecoupling apacitor (such Tantalum
0.01 ecoupling apacitors
Crystal Load Capacitors
device crystal connections should include pads small capacitors from ground from ground, shown External Component Schematic. These capacitors used adjust stray capacitance board match nominally required crystal load capacitance. Because load capacitance only increased this trimming process, important keep stray capacitance minimum using very short traces (and via's) been crystal device. most cases load capacitors will required. They should stuffed prototype evaluation board indiscriminate these trim capacitors will typically cause more crystal centering error than their absence. need load capacitors later determined, values will fall within range. need for, value these trim capacitors only determined prototype evaluation. Please refer Optimization Crystal Load Capacitors section more information.
Optimization Crystal Load Capacitors
concept behind optional crystal load capacitors introduced previously this data sheet (see Crystal Load Capacitor section Page determine need value these capacitors, will need your final layout, frequency counter capable less than resolution accuracy, power supplies, some samples crystals which plan production, along with measured initial accuracy each crystal specified crystal load capacitance, determine value crystal capacitors: Connect 3.3V. Connect second power supply. Adjust voltage Measure record frequency output.
Layout Recommendations
optimum device performance lowest output phase noise, following guidelines should observed. Please also refer Recommended Layout drawing Page Each 0.01µF decoupling capacitor should mounted component side board close possible. via's should used between decoupling capacitor pin. trace should kept short possible,
1581-01
Revision 091901
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 295-9800 www.icst.com
Preliminary
MK1581-01 Phase Noise Clock Generator
Adjust voltage 3.3V. Measure record frequency same output. calculate centering error:
3.0V Error error xtal
much stray capacitance will need redone with layout reduce stray capacitance. Alternately, crystal re-specified higher lower load capacitance. Contact MicroClock details. centering error more than positive, identical fixed centering capacitors from each crystal ground. value each these caps given External Capacitor (centering error)/(trim sensitivity) Trim sensitivity parameter which supplied your crystal vendor. know value, assume ppm/pF. After changes, repeat measurement verify that remaining error acceptably (less than ±15ppm).
Where: ftarget nominal crystal frequency errorxtal =actual initial accuracy ppm) crystal being measured centering error less than ppm, adjustment needed most applications. centering error more than negative,
Recommended Layout
inim output clock jitter, device connections should bulk decoupling device (see text).
inim output clock jitter, ground plane ithin this entire area. route other traces from this area.
Legend:
round onnection
1581-01
Revision 091901
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 295-9800 www.icst.com
Preliminary
MK1581-01 Phase Noise Clock Generator
Absolute Maximum Ratings
Stresses above ratings listed below cause permanent damage MK1581-01. These ratings, which standard values commercially rated parts, stress ratings only. Functional operation device these other conditions above those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect product reliability. Electrical parameters guaranteed only over recommended operating temperature range.
Item
Supply Voltage, Inputs Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature
Rating
-0.5V VDD+0.5V +85°C +150°C 175°C 260°C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature Power Supply Voltage (measured respect GND)
Min.
+3.15
Typ.
+3.3
Max.
+3.45
Units
Electrical Characteristics
Unless stated otherwise, 3.3V ±5%, Ambient Temperature +85°C
Parameter
Operating Voltage Supply Current Input High Voltage, Input Voltage, Input High Voltage, 8kHz_IN Input Voltage, 8kHz_IN Input High Current Input Current Input Capacitance, except Output High Voltage (CMOS Level) Output High Voltage Output Voltage
Symbol
Conditions
Clock outputs unloaded, 3.3V
Min.
3.15
Typ.
Max.
3.45
VDD/2-1
Units
VDD/2+1
VDD-0.4
1581-01
Revision 091901
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 295-9800 www.icst.com
Preliminary
MK1581-01 Phase Noise Clock Generator
Parameter
Short Circuit Current VIN, VCXO Control Voltage Nominal Output Impedance
Symbol
ZOUT
Conditions
Min.
Typ.
Max.
Units
Electrical Characteristics
Unless stated otherwise, 3.3V ±5%, Ambient Temperature +85°
Parameter
VCXO Crystal Pull Range VCXO Crystal Nominal Frequency Input Jitter Tolerance Input pulse width Output Frequency Error Output Duty Cycle high time) Output Rise Time Output Fall Time Skew, Input Output Clock Cycle Jitter (short term jitter)
Symbol
FOUT
Conditions
Using Recommended Crystal
Min.
-115 24.704
Typ.
Max.
+115 24.576
Units
reference input clock period ICLK error Measured VDD/2, CL=15pF 2.0V, CL=15pF 0.8V, CL=15pF Note Peak Peak
Note Minimum high time input clock. Note input output clock skew controlled predictable will change between power cycles. Because dependent phase relationship between output feedback divider states following power input output clock skew will remain stable during given power cycle. controlled input output skew desired this output clock frequency please refer MK2049 MK2069 products.
1581-01
Revision 091901
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 295-9800 www.icst.com
Preliminary
MK1581-01 Phase Noise Clock Generator
Package Outline Package Dimensions TSSOP, 4.40 Body, 0.65 Pitch)
Package dimensions kept current with JEDEC Publication MO-153
Millimeters Symbol Inches
AREA
-1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 -0.10
-0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.193 0.201 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 -0.004
Ordering Information
Part Order Number
MK1581-01GI MK1581-01GITR
Marking
MK1581-01GI MK1581-01GI
Shipping packaging
Tubes Tape Reel
Package
TSSOP TSSOP
Temperature
+85° +85°
While information presented herein been checked both accuracy reliability, Integrated Circuit Systems (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial applications. other applications such those requiring extended temperature range, high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments.
1581-01
Revision 091901
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 295-9800 www.icst.com

Phase Noise Clock Generator MK1581-01 provides synchronization ti

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