700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER F

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700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER F

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ICS8432-111
700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
FEATURES
Dual differential 3.3V LVPECL outputs Selectable differential CLK, nCLK pair LVCMOS TEST_CLK CLK, nCLK pair accept following differential input levels: LVPECL, LVHSTL, LVDS, SSTL, HCSL TEST_CLK accept following input types: LVCMOS LVTTL Maximum FOUT frequency 700MHz Maximum FOUT/2 frequency 350MHz 14MHz 25MHz differential input TEST_CLK input frequency range: 200MHz 700MHz Parallel serial interface programming counter frequency multiplier dividers period jitter: Cycle-to-cycle jitter: 25ps (maximum) 3.3V supply voltage 70°C ambient operating temperature
GENERAL DESCRIPTION
ICS8432-111 general purpose, dual output Differential-to-3.3V LVPECL High Frequency HiPerClockSSynthesizer member HiPerClockSfamily High Performance Clocks Solutions from ICS. ICS8432-111 selectable differential CLK, nCLK pair LVCMOS TEST_CLK. TEST_CLK input accepts LVCMOS LVTTL input levels translates them 3.3V LVPECL levels. CLK, nCLK pair accept most standard differential input levels.The operates frequency range 200MHz 700MHz. frequency programmed steps equal value input differential single ended reference frequency. Output frequencies 700MHz FOUT 350MHz FOUT/2 programmed using serial parallel interfaces configuration logic. phase noise characteristics multiple frequency outputs ICS8432-111 makes ideal clock source Fiber Channel Infiniband applications.
BLOCK DIAGRAM
VCO_SEL CLK_SEL TEST_CLK nCLK
ASSIGNMENT
VCO_SEL nP_LOAD nCLK
TEST FOUT/2 nFOUT/2 VCCO FOUT nFOUT
TEST_CLK CLK_SEL VCCA S_LOAD S_DATA S_CLOCK
ICS8432-111
PHASE DETECTOR S_LOAD S_DATA S_CLOCK nP_LOAD M0:M8 N0:N1
FOUT nFOUT FOUT/2 nFOUT/2
CONFIGURATION INTERFACE LOGIC
TEST
32-Lead LQFP 1.4mm package body Package View
Preliminary Information presented herein represents product prototyping pre-production. noted characteristics based initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves right change circuitry specifications without notice.
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700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
NOTE: functional description that follows describes operation using 25MHz clock input. Valid loop divider values different input frequencies defined Input Frequency Characteristics, Table NOTE
ICS8432-111 features fully integrated therefore requires external components setting loop bandwidth. differential clock input used input ICS8432-111. This input into phase detector. 25MHz clock input provides 25MHz phase detector reference frequency. operates over range 200MHz 700MHz. output loop divider also applied phase detector. phase detector loop filter divider force output frequency times reference frequency adjusting control voltage. Note that some values (either high low), will achieve lock. output scaled divider prior being sent each LVPECL output buffers. divider provides output duty cycle. programmable features ICS8432-111 support input modes programmable loop divider output divider. input operational modes parallel serial. Figure1 shows timing diagram each mode. parallel mode nP_LOAD input initially LOW. data inputs through passed directly ripple counter. LOW-to-HIGH transition nP_LOAD input, data latched ripple counter remains loaded until next transition nP_LOAD until serial event occurs. result, bits hardwired ripple counter specific default state that will automatically occur during power-up. TEST output when operating parallel input mode. relationship between frequency, input frequency loop divider defined follows: fVCO count required values through shown Table Programmable Frequency Function. Valid values which will achieve lock defined frequency defined follows: fOUT fVCO Serial operation occurs when nP_LOAD HIGH S_LOAD LOW. shift register loaded sampling S_DATA bits with rising edge S_CLOCK. contents shift register loaded into ripple counter when S_LOAD transitions from LOW-to-HIGH. ripple counter divide values latched HIGH-to-LOW transition S_LOAD. S_LOAD held HIGH, data S_DATA input passed directly ripple counter each rising edge S_CLOCK. serial mode used program bits test bits internal registers determine state TEST output follows: TEST Output S_Data Output divider CMOS Fout/2
S_DATA S_CLOCK
NULL
S_LOAD M0:M8, N0:N1
nP_LOAD
Time
FIGURE PARALLEL SERIAL LOAD OPERATIONS
*NOTE:
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NULL timing slot must observed.
REV. DECEMBER 2001
ICS8432-111
700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Type Input Input Input Unused Power Output Power Output Power Output Input Input Input Input Power Input Input Input Input Input Input Pullup Pulldown Pullup Pulldown Pulldown Pulldown Pulldown Pullup counter/divider inputs. Data latched LOW-to-HIGH transistion Pulldown nP_LOAD input. LVCMOS LVTTL interface levels. Pulldown Determines output divider value defined Table Function Table. LVCMOS LVTTL interface levels. connect. Negative supply pins. Connect ground. Test output which ACTIVE serial mode operation. Output driven parallel mode. LVCMOS interface levels. Positive supply pin. Half frequency differential output synthesizer. 3.3V LVPECL interface levels. Output supply pin. Connect 3.3V. Differential output synthesizer. 3.3V LVPECL interface levels. Master reset. Forces outputs LOW, does effect loaded values. LVCMOS LVTTL interface levels. Clocks serial data present S_DATA input into shift register rising edge S_CLOCK. Shift register serial input. Data sampled rising edge S_CLOCK. Controls transition data from shift register into ripple counter. LVCMOS LVTTL interface levels. Analog supply pin. Connect 3.3V. Selects between differential clock input test input reference source. LVCMOS LVTTL interface levels. Selects CLK, nCLK inputs when HIGH. Selects TEST_CLK when LOW. Test clock input. LVCMOS LVTTL interface levels. Description
TABLE DESCRIPTIONS
Number Name TEST FOUT/2, nFOUT/2 VCCO FOUT, nFOUT S_CLOCK S_DATA S_LOAD VCCA CLK_SEL TEST_CLK nCLK nP_LOAD VCO_SEL
Pulldown Non-inver ting differential clock input. Inver ting differential clock input. Parallel load input. Determines when data present M8:M0 Pulldown loaded into ripple counter, when data present N1:N0 sets output divider value. LVCMOS LVTTL interface levels. Determines whether synthesizer bypass mode. Pullup LVCMOS LVTTL interface levels.
NOTE: Pullup Pulldown refers internal input resistors. Table Characteristics, typical values.
TABLE CHARACTERISTICS
Symbol RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical Maximum Units
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700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE PARALLEL
SERIAL MODE FUNCTION TABLE
Inputs Conditions S_CLOCK S_DATA Data Data Data Data Reset. counters reset. Data inputs passed directly ripple counter output divider. TEST output forced LOW. Data latched into input registers remains loaded until next transition until serial event occurs. Serial input mode. Shift register loaded with data S_DATA each rising edge S_CLOCK. Contents shift register passed ripple counter output divider. Ripple counter output divider values latched. Parallel serial input affect shift registers. S_DATA passed directly ripple counter clocked.
nP_LOAD
Data Data
Data Data
S_LOAD
NOTE: HIGH Don't care Rising edge transition Falling edge transition
TABLE PROGRAMMABLE FREQUENCY FUNCTION TABLE
Frequency (MHz) Count
NOTE These count values resulting frequencies correspond differential input TEST_CLK input frequency 25MHz.
TABLE PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs
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Output Frequency (MHz) Divider Value Minimum FOUT Maximum 87.5 Minimum 62.5 31.25 15.625 FOUT/2 Maximum 87.5 43.75
REV. DECEMBER 2001
ICS8432-111
700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
4.6V -0.5V 0.5V -0.5V 0.5V 47.9°C/W lfpm) -65°C 150°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCCx Inputs, Outputs, Package Thermal Impedance, Storage Temperature, TSTG
Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these condition conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
TABLE POWER SUPPLY CHARACTERISTICS, VCCA VCCO 3.3V±5%,
Symbol VCCA VCCO ICCA Parameter Positive Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135
70°C
Maximum 3.465 3.465 3.465 Units
Typical
TABLE LVCMOS LVTTL CHARACTERISTICS, VCCA VCCO 3.3V±5%,
Symbol Parameter Input High Voltage VCO_SEL, CLK_SEL, S_LOAD, S_DATA, S_CLOCK, nP_LOAD, N0:N1, M0:M8, TEST_CLK Input Voltage VCO_SEL, CLK_SEL, S_LOAD, S_DATA, S_CLOCK, nP_LOAD, N0:N1, M0:M8, TEST_CLK M0-M4, M6-M8, S_CLOCK, S_DATA, S_LOAD, TEST_CLK, nP_LOAD, CLK_SEL, VCO_SEL M0-M4, M6-M8, S_CLOCK, S_DATA, S_LOAD, TEST_CLK, nP_LOAD, CLK_SEL, VCO_SEL Output High Voltage Output Voltage TEST; NOTE TEST; NOTE *VCCx 3.465V *VCCx 3.465V *VCCx 3.465V, *VCCx 3.465V, Test Conditions Minimum -0.3
70°C
Maximum Units
Typical
Input High Current
Input Current
-150
NOTE Outputs terminated with VCCO/2. page Figure 3.3V Output Load Test Circuit. *NOTE: VCCx denotes VCC, VCCA, VCCO.
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700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE DIFFERENTIAL CHARACTERISTICS, VCCA VCCO 3.3V±5%,
Symbol Parameter Input High Current Input Current nCLK nCLK Test Conditions *VCCx 3.465V *VCCx 3.465V *VCCx 3.465V, *VCCx 3.465V, -150 Minimum
70°C
Maximum Units 0.85
Typical
Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VCMR NOTE NOTE Common mode voltage defined VIH. NOTE single ended applications, maximum input voltage CLK, nCLK 0.3V. NOTE: *VCCx denotes VCC, VCCA, VCCO.
TABLE LVPECL CHARACTERISTICS, VCCA VCCO 3.3V±5%,
Symbol VSWING Parameter Output High Voltage; NOTE Output Voltage; NOTE Peak-to-Peak Output Voltage Swing Test Conditions
70°C
Typical Maximum VCCO VCCO 0.85 Units
Minimum VCCO VCCO
NOTE Outputs terminated with VCCO
TABLE INPUT FREQUENCY CHARACTERISTICS, VCCA VCCO 3.3V±5%,
Symbol Parameter TEST_CLK; NOTE Input Frequency CLK, nCLK; NOTE Test Conditions
70°C
Typical Maximum Units
Minimum
S_CLOCK NOTE input frequency range, value must operate within 200MHz 700MHz range. Using minimum input frequency 12MHz, valid values Using maximum frequency 25MHz, valid values
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ICS8432-111
700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE CHARACTERISTICS, VCCA VCCO 3.3V±5%,
Symbol FOUT Parameter Output Frequency Cycle-to-Cycle Jitter NOTE Period Jitter, RMS; NOTE Output Skew; NOTE Output Rise Time Output Fall Time nP_LOAD Setup Time S_DATA S_CLOCK S_CLOCK S_LOAD nP_LOAD Hold Time Output Duty Cycle S_DATA S_CLOCK S_CLOCK S_LOAD
70°C
Minimum Typical Maximum Units
Test Conditions
tjit(cc) tjit(per) tsk(o)
50MHz 50MHz
Lock Time tLOCK parameters measured 500MHz unless noted otherwise. NOTE Defined skew between outputs same supply voltage with equal load conditions. Measured output differential cross points. NOTE This parameter defined accordance with JEDEC Standard
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ICS8432-111
700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
VCC, VCCA, VCCO
SCOPE
LVPECL
VCC, VCCA, VCCO 2.0V
-1.3V 0.135V
FIGURE 3.3V OUTPUT LOAD TEST CIRCUIT
nFOUTx FOUTx
nFOUTy FOUTy
tsk(o)
FIGURE OUTPUT SKEW
SWING
Clock Inputs Outputs
FIGURE INPUT
OUTPUT RISE
FALL TIME
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ICS8432-111
700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
nFOUT, FOUT/2 TEST, FOUT, FOUT/2
Pulse Width
PERIOD
PERIOD
FIGURE tPERIOD
IDEAL OUTPUT
ACTUAL OUTPUT
jit(per) tcycle
nFOUT, FOUT/2
FOUT, FOUT/2
tcycle
jit(cc) tcycle -tcycle
1000 Cycles
FIGURE Cycle-to-Cycle Jitter
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tcycle
where nominal output frequency tcycle cycle within sample measured controlled edges
FIGURE Period Jitter
tcycle
REV. DECEMBER 2001
ICS8432-111
700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION
WIRING DIFFERENTIAL INPUT ACCEPT SINGLE ENDED LEVELS
Figure shows differential input wired accept single ended levels. reference voltage V_REF VCC/2 generated bias resistors This bias circuit should located close possible input pin. ratio might need adjusted position V_REF center input voltage swing. example, input clock swing only 2.5V 3.3V, V_REF should 1.25V R2/R1 0.609.
CLK_IN V_REF
0.1uF
FIGURE SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
POWER SUPPLY FILTERING TECHNIQUES
high speed analog circuitry, power supply pins vulnerable random noise. ICS8432-111 provides separate power supplies isolate high switching noise from outputs internal PLL. VCC, VCCA, VCCO should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, power supply isolation required. Figure illustrates resistor along with 10µF .01µF bypass capacitor should connected each VCCA pin.
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3.3V .01µF VCCA .01µF
FIGURE POWER SUPPLY FILTERING
REV. DECEMBER 2001
ICS8432-111
700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TERMINATION LVPECL OUTPUTS
clock layout topology shown below typical termination LVPECL outputs. different layouts mentioned recommended only guidelines. FOUT nFOUT impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors current path ground) current sources must used functionality. These outputs designed
drive transmission lines. Matched impedance techniques should used maximize operating frequency minimize signal distortion. There simple termination schemes. Figures show different layouts which recommended only guidelines. Other suitable clock layouts exist would recommended that board designers simulate guarantee compatibility across printed circuit clock component process variations.
3.3V
FOUT
FOUT
(VOH
FIGURE 10A. LVPECL OUTPUT TERMINATION
schematic ICS8432-111 layout example used this layout guideline shown Figure 11A. ICS8432-111 recommended board layout this example shown Figure 11B. This layout example used general guideline. layout actual system will depend selected component types, density components, density traces, stacking P.C. board.
FIGURE 11A. SCHEMATIC
8432CY-111
FIGURE 10B. LVPECL OUTPUT TERMINATION
LAYOUT GUIDELINE
RECOMMENDED LAYOUT
REV. DECEMBER 2001
ICS8432-111
700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
trace delay might restricted available space board component location. While routing traces, clock signal traces should routed first should locked prior routing other signals traces. differential output traces should have same length. Avoid sharp angles clock trace. Sharp angle turns cause characteristic impedance change transmission lines. Keep clock traces same layer. Whenever possible, avoid placing vias clock traces. Placement vias traces affect trace characteristic impedance hence degrade signal integrity. prevent cross talk, avoid routing other signal traces parallel with clock traces. running parallel traces unavoidable, allow spearation least three trace widths between differential clock trace other signal trace. Make sure other signal traces routed between clock trace pair. matching termination resistors should located close receiver input pins possible.
following component footprints used this layout example: resistors capacitors size 0603.
POWER
GROUNDING
Place decoupling capacitors close possible power pins. space allows, placement decoupling capacitor component side preferred. This reduce unwanted inductance between decoupling capacitor power caused via. Maximize power ground sizes number vias capacitors. This reduce inductance between power ground planes component power ground pins. filter consisting C11, should placed close VCCA possible.
CLOCK TRACES
TERMINATION
Poor signal integrity degrade system performance cause system failure. synchronous high-speed digital systems, clock signal less tolerant poor signal integrity than other signals. ringing rising falling edge excessive ring back cause system failure. shape trace
FIGURE 11B. BOARD LAYOUT ICS8432-111
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REV. DECEMBER 2001
ICS8432-111
700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS
This section provides information power dissipation junction temperature ICS8432-111. Equations example calculations also provided.
Power Dissipation. total power dissipation ICS8432-111 core power plus power dissipated load(s). following power dissipation 3.3V 3.465V, which gives worst case results. NOTE: Please refer Section details calculating power dissipated load.
Power (core)MAX VCC_MAX IEE_MAX 3.465V 110mA 381.2mW Power (outputs)MAX 30.2mW/Loaded Output pair outputs loaded, total power 30.2mW 60.4mW
Total Power_MAX (3.465V, with outputs switching) 381.2mW 60.4mW 441.6mW
Junction Temperature. Junction temperature, temperature junction bond wire bond directly affects reliability device. maximum recommended junction temperature HiPerClockSdevices 125°C.
equation follows: Pd_total Junction Temperature junction-to-ambient thermal resistance Pd_total Total device power dissipation (example calculation section above) Ambient Temperature order calculate junction temperature, appropriate junction-to-ambient thermal resistance must used Assuming moderate flow linear feet minute multi-layer board, appropriate value 42.1°C/W Table below. Therefore, ambient temperature 70°C with outputs switching 70°C 0.441W 42.1°C/W 88.6°C. This well below limit 125°C This calculation only example. will obviously vary depending number loaded outputs, supply voltage, flow, type board (single layer multi-layer).
Table Thermal Resistance 32-pin LQFP, Forced Convection
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W
55.9°C/W 42.1°C/W
50.1°C/W 39.4°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
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Calculations Equations.
purpose this section derive power dissipated into load. LVPECL output driver circuit termination shown Figure
ICS8432-111
700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
VCCO
VOUT VCCO
FIGURE LVPECL DRIVER CIRCUIT
TERMINATION
calculate worst case power dissipation into load, following equations which assume load, termination voltage
Pd_H power dissipation when output drives high. Pd_L power dissipation when output drives low.
Pd_H [(VOH_MAX (VCCO_MAX 2V))/R (VCCO_MAX VOH_MAX)
Pd_L
OL_MAX
CCO_MAX
2V))/R
CCO_MAX
OL_MAX
logic high, VOUT
OH_MAX
CCO_MAX
1.0V
Using VCCO_MAX 3.465, this results VOH_MAX 2.465V logic low, VOUT Using
CCO_MAX
OL_MAX
CCO_MAX
1.7V
OL_MAX
3.465, this results
1.765V
Pd_H =[(2.465V (3.465V 2V))/50] (3.465V 2.465V) 20mW Pd_L =[(1.765V (3.465V 2V))/50] (3.465V 1.765V) 10.2mW Total Power Dissipation output pair Pd_H Pd_L 30.2mW
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ICS8432-111
700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE JAVS. FLOW TABLE
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W
55.9°C/W 42.1°C/W
50.1°C/W 39.4°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
TRANSISTOR COUNT
transistor count ICS8432-111 3765
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ICS8432-111
700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE SUFFIX
TABLE PACKAGE DIMENSIONS
JEDEC VARIATION DIMENSIONS MILLIMETERS SYMBOL 0.45 -0.05 1.35 0.30 0.09 MINIMUM NOMINAL -1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 -0.75 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication MS-026
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REV. DECEMBER 2001
ICS8432-111
700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Marking ICS8432CY-111 ICS8432CY-111 Package Lead LQFP Lead LQFP Tape Reel Count tray 1000 Temperature 70°C 70°C
TABLE ORDERING INFORMATION
Part/Order Number ICS8432CY-111 ICS8432CY-111T
While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial applications. other applications such those requiring extended temperature range, high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 8432CY-111
REV. DECEMBER 2001

700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER F

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