VCXO-Based Universal Clock Translator MK2069-04 VCXO (Voltage Con
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MK2069-04
VCXO-Based Universal Clock Translator
MK2069-04 VCXO (Voltage Controlled Crystal Oscillator) based clock generator that features (Phase-Locked Loop) input reference divider feedback divider that have wide numeric range selectable user. This enables complex multiplication ratio that used translation between clock frequency standards. on-chip VCXO produces stable, jitter output clock using phase detector frequency down lower. This means MK2069-04 translate between clock frequencies that have common denominator, such frame clock common with telecom standards. MK2069-04 also provides jitter attenuation input clock accept input frequency well. device optimized user configurability providing access major divider functions. power-up programming needed configuration selected. External VCXO loop filter components provide additional level user configurability. MK2069-04 includes lock detector (LD) output that serves clock status monitor. clear (CLR) input enables rapid synchronization phase newly selected input clock.
Features
Input clock frequency <1kHz 170MHz Output clock frequency 500kHz 160MHz Clock translation examples:
(1.544MHz) to/from (2.048MHz) (44.736MHz) to/from (34.368MHz) OC-3 (155.52MHz) to/from (1.544 MHz) CCIR-601 (27MHz) to/from SMPTE 274M (74.125MHz)
Jitter attenuation input clock provided VCXO
circuit. Jitter transfer characteristics user configured through external loop filter component selection. jitter phase noise generation. lock status output Clear function allows seamless synchronizing altered input clock phase provides frequency translation VCXO output (VCLK) higher alternate output frequency (TCLK). Device will free-run absence input clock based VCXO frequency. TSSOP package Single 3.3V power supply tolerant clock input
Block Diagram
ullable xtal 11:0
hase ctor
VCXO
ivider
ivid
ivider 1,2,12,16
ivider
VCXO
ivider 4096
ivid Translator
only
etec
11:0
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MK2069-04 VCXO-Based Universal Clock Translator
Assignment
GNDT GNDV GNDP RCLK
Input Selection Tables
VCXO Reference Pre-Divider Selection Table
Pre-Divider Ratio
VCXO Reference Divider Selection Table
RV11:0 0.00 0.01 1.11 Divider Ratio 4097 Notes
2069-04
Divide Value Address
VCXO Feedback Divider Selection
FV11:0 Divider Ratio Notes addresses 4094, 0.00 Divide Value 0.01 Address 1.10 4096 1.11
VCXO Scaling Divider Selection Table
Divider Ratio
Translator Feedback Divider Selection
Divider Ratio
Translator Scaling Divider Selection Table
Divider Ratio
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MK2069-04 VCXO-Based Universal Clock Translator
Descriptions
Number
Name
RV10 RV11 VDDT GNDT VDDV GNDV ISET FV10 FV11 ICLK RCLK GNDP
Type
Input Input Input Input Input Input Input Input Input Input Input Power Ground Power Ground Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Ground Power Ground
Reference Divider input, VCXO PLL, internal pull-up. Reference Divider input, VCXO PLL, internal pull-up. Reference Divider input, VCXO PLL, internal pull-up. Reference Divider input, VCXO PLL, internal pull-up. Feedback Divider input, Translator PLL, internal pull-up. Feedback Divider input, Translator PLL, internal pull-up. Feedback Divider input, Translator PLL, internal pull-up. Reference Divider VCXO PLL, internal pull-up. Reference Divider VCXO PLL, internal pull-up. Reference Divider VCXO PLL, internal pull-up. Scaling Divider selection bit, Translator PLL, internal pull-up. Power Supply connection translator PLL. Ground connection translator PLL. Crystal oscillator input. Connect this external quartz crystal. Power Supply connection VCXO PLL. Crystal oscillator output. Connect this external quartz crystal. Ground connection VCXO PLL. Loop filter connection, reference node. Refer loop filter circuit page Loop filter connection, active node. Refer loop filter circuit page Charge pump current setting pin. Refer loop filter circuit page Feedback Divider input, VCXO PLL, internal pull-up. Feedback Divider 1input, VCXO PLL, internal pull-up. Feedback Divider input, VCXO PLL, internal pull-up. Feedback Divider input, VCXO PLL, internal pull-up. Feedback Divider input, VCXO PLL, internal pull-up. Feedback Divider input, VCXO PLL, internal pull-up. Feedback Divider input, VCXO PLL, internal pull-up. Feedback Divider input, VCXO PLL, internal pull-up. Feedback Divider input, VCXO PLL, internal pull-up. Feedback Divider input, VCXO PLL, internal pull-up. Feedback Divider input, VCXO PLL, internal pull-up. Feedback Divider input, VCXO PLL, internal pull-up. Reference Divider VCXO PLL, internal pull-up. Reference Divider VCXO PLL, internal pull-up. Reference clock input, tolerant input Clear input, allows VCXO free-run when low, internal pull-up. Lock detector threshold setting circuit connection. Refer circuit page Ground connection internal digital circuitry. Lock detector threshold setting circuit connection. Refer circuit page VCXO phase detector Reference Clock output. Ground connection output drivers (VCLK, TCLK, RCLK, LDR).
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MK2069-04 VCXO-Based Universal Clock Translator
Number
Name
VCLK VDDP TCLK
Type
Output Power Output Output Power Input Input Input Input Input Input Input Input Input Input Clock output from VCXO
Power Supply output drivers (VCLK, TCLK, RCLK, LDR). Clock output from Translator Lock detector output. Power Supply connection internal digital circuitry. Output enable RCLK. RCLK tri-stated when low, internal pull-up. Output enable VCLK. VCLK tri-stated when low, internal pull-up. Output enable TCLK. TCLK tri-stated when low, internal pull-up. Output enable tri-stated when low, internal pull-up. Reference Divider input, VCXO PLL, internal pull-up. Reference Divider input, VCXO PLL, internal pull-up. Reference Divider input, VCXO PLL, internal pull-up. Scaler Divider input, VCXO PLL, internal pull-up. Scaler Divider input, VCXO PLL, internal pull-up. Scaler Divider input, VCXO PLL, internal pull-up.
Functional MK2069-04 (Phase Locked Loop) based clock generator that generates output clocks synchronized input reference clock. contains cascaded PLL's with user selectable divider ratios. first VCXO-based uses external pullable crystal part normal "VCO" (voltage controlled oscillator) function PLL. VCXO assures phase noise clock source even when loop bandwidth implemented. loop bandwidth needed when input reference frequency phase detector low, when jitter attenuation input reference desired. second used translate multiply frequency VCXO which maximum output frequency MHz. This second PLL, Translator PLL, uses on-chip circuit that provide output clock MHz. Translator uses high loop bandwidth (typically greater than MHz) assure stability clock output generated VCO. requires stable, high frequency input reference which provided VCXO. divide values divider blocks within both PLLs device configuration. This enables system designer define following:
Input clock frequency VCXO crystal frequency VCLK output frequency RCLK output frequency, which also phase detector frequency VCXO PLL. TCLK output frequency
unused clock logic outputs tri-stated reduce interference (jitter, phase noise) other clock outputs. Outputs also tri-stated system testing purposes. External components used configure VCXO loop response. This serves maximize loop stability achieve desired input clock jitter attenuation characteristics.
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MK2069-04 VCXO-Based Universal Clock Translator
Application Information
MK2069-04 mixed analog digital integrated circuit that sensitive (printed circuit board) layout external component selection. Used properly, device will provide same high performance expected from canned VCXO-based hybrid timing device, lower cost. help avoid unexpected problems, guidance provided sections below should followed.
clock outputs device remain frequency locked input, which required normal operation.
Setting TCLK Output Frequency
clock frequency TCLK determined f(TCLK) Divider f(VCLK) Where: Divider frequency range TCLK operational range internal circuit output divider selections: f(TCLK) f(VC0) Divider
Setting VCLK Output Frequency
frequency VCLK output determined following relationship: Divider f(VCLK) f(ICLK) Divider Divider Where: Divider 4096 Divider Divider 4097 Because divider inherently higher speed operation than divider, divider should when this factor included divisor combination. VCLK output frequency range allowable frequency range external VCXO crystal internal VCXO divider selections: f(VCLK) VCXO Divider
Where: f(VCO) Divider 2,4,8 higher frequency will generally produce lower phase noise therefore preferred.
MK2069-04 Loop Response JItter Attenuation Characteristics
MK2069-04 will reduce transfer phase jitter existing input reference clock output clock. This operation known jitter attenuation. low-pass frequency response VCXO loop mechanism that provides input jitter attenuation. Clock jitter, more accurately called phase jitter, overall instability clock period which measured time domain using oscilloscope, instance. Jitter comprised phase noise which represented frequency domain. phase noise input reference clock attenuated according VCXO low-pass frequency response curve. response curve, thus jitter attenuation characteristics, established through selection external MK2069-04 passive components other device setting explained following section.
Where: F(VCXO) F(External Crystal) Divider 1,2,4,6,8,10,12 higher crystal frequency will generally produce lower phase noise therefore preferred. crystal frequency between 13.5 recommended. Because VCLK generated external crystal, tracking range VCLK given configuration limited pullable range crystal. This guaranteed +/-115 minimum. This tracking range also applies input clock
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MK2069-04 VCXO-Based Universal Clock Translator
Setting VCXO Loop Response.
VCXO loop response determined both fixed device characteristics variables user. This includes values RSET shown External VCXO Components figure this page. VCXO loop bandwidth approximated
NBW(VCO PLL) Divider Divider
External VCXO Components
efer rystal ning Load apacitors" ectio
Where: Value resistor loop filter Ohms Charge pump current amps (see table page VCXO Gain Hz/V (see table page Divider 1,2,12 Divider 4096 above equation calculates "normalized" loop bandwidth (denoted "NBW") which approximately equal bandwidth. does take into account effects damping factor second pole imposed does, however, provide useful approximation filter performance. prevent jitter VCLK modulation VCXO phase detector frequency, following general rule should observed: NBW(VCO PLL)
ptional Crystal Tunin acitors
2069
XTAL
f(Phase Detector)
loop damping factor determined
DF(VCLK) Divider Divider
Where: Value capacitor loop filter Farads
general, loop damping factor should greater ensure output stability. higher damping factor will create less peaking passband will further assure output stability with presence system power supply noise. damping factor will ensure passband peak less then 0.2dB which required network clock wander transfer compliance. higher damping factor also increase output clock jitter when there excess digital noise system application, reduced ability respond therefore compensate phase noise ingress.
Notes setting value
another general rule, following relationship should maintained between components loop filter:
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MK2069-04 VCXO-Based Universal Clock Translator
establishes second pole VCXO loop filter. higher damping factors calculate value based value that would used damping factor This will minimize baseband peaking loop instability that lead output jitter. also dampens VCXO input voltage modulation charge pump correction pulses. value that will result increased output phase noise phase detector frequency this. extreme cases where input jitter high, charge pump current high, small, VCXO input voltage supply ground rail resulting non-linear loop response. best value filter response software available from (please refer
following section). should increased value until just starts affecting passband peak.
Loop Filter Response Software
PC-based program available that simulates VCXO loop response characteristics. This used instead above bandwidth damping factor equations. user enters external loop filter component values other listed device characteristics. program generates frequency response graph, which translates jitter attenuation characteristics. Normalized bandwidth (NBW) damping factor values also calculated. obtain this free software please contact applications department ICS, MicroClock Division, (408) 297-1201. This program will placed site near future.
Graph Charge Pump Current Value RSET (external resistor)
1E-3
ICP, Amps
100E-6
10E-6 100E+3
1E+6
RSET, ohms
Recommended Range Operation
10E+6
Charge Pump Current, Example Settings from Above Graph
RSET Charge Pump Current (ICP)
Notes Setting Charge Pump Current
recommended range charge pump current Below loop filter charge leakage, capacitor leakage, become problem. This loop filter leakage cause locking problems, output clock cycle slips, frequency phase noise. seen loop bandwidth damping factor equations using filter response software available from ICS, increasing charge pump current (ICP) increases both bandwidth damping factor.
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MK2069-04 VCXO-Based Universal Clock Translator
VCXO Gain (KO) XTAL Frequency
6000
Notes Setting RPV, Divider Values VCXO
shown loop bandwidth damping factor equations page using filter response software available from ICS, increasing decreases both bandwidth damping factor. Many applications require that these cases, decrease loop bandwidth increase value which accompanied increase value and/or maintain same frequency multiplication ratio. However, phase detector frequency, FPD, also needs considered. equal input frequency divided value should typically least loop bandwidth prevent loop modulation (phase noise) phase detector frequency. phase detector jitter tolerance limit (use 0.4UI) input phase noise frequency aliasing should considerations well.
5000
4000
3000
2000
1000
rystal Frequ
Example Loop Filter Component Value
Phase Detector Frequency 19.44 Xtal Freq (MHz) 19.44 19.44 22.368 19.44 VCLK (MHz) 19.44 19.44 RSET Loop Loop Damp. (-3dB) 0.85 Passband Peaking 0.15dB 1.2dB 0.12dB 1.8dB Note
2430
2430
22.368 2796 19.44
Notes: This filter configuration assures passband ripple compliant with Bellcore GR-1244-CORE satisfy wander transfer requirements (<0.2 ripple required) network node. used following system synchronizer such MT9045 provide clock jitter attenuation while maintaining Stratum compliance. 155.52 TCLK output generated with VCXO configuration will OC-3 OC-12 timing jitter compliant. This reduced cost size variant above filter, decreased size useful when GR-1244-CORE compliance needed. This configuration used generate clock 44.768 TCLK output. This configuration GR-1244-CORE compliant when used following system synchronizer. Lowering phase detector frequency, increasing value and/or dividers divider, will lower loop bandwidth and/or decrease size same damping factor.
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Loop Filter Capacitor Type
Loop filter capacitors should film type. This includes polymer film type made Panasonic, metal poly types made MuRata Cornell Dublier. Panasonic ECP-U ECH-U series capacitors typically used MK20xx demo boards found work well. These devices available from Digi-Key. Other acceptable capacitor types include those with dielectric. Avoid high-K dielectrics like (these acceptable decoupling capacitors, however). loop capacitors must have high dielectric resistance avoid leakage-induced phase noise. this reason, type polarized electrolytic capacitors. Microphonics (mechanical board vibration) will also induce output phase noise, especially when loop bandwidth less than 1kHz. High-K dielectrics like have piezoelectric properties that convert mechanical vibration into voltage noise that interferes with VCXO operation. additional questions, please contact your Sales contact MicroClock applications (408) 297-1201.
correction pulses provided loop filter. During this time, VCXO frequency held constant residual charge voltage loop filter, regardless input clock condition. However, VCXO frequency will drift over time, eventually minimum pull range crystal, leak-off loop filter charge. This means that provide holdover function, only very short duration, typically milliseconds. Upon bringing high, Divider reset begins counting upon with first positive edge input clock, charge pump re-activated. resetting Divider, memory previous input clock phase removed from feedback divider, eliminating generation extra VCLK clock cycles that would occur loop re-lock under normal means. Lock time also reduced, generation clock wander. using this fashion VCLK will align input clock phase with only VCLK cycle slips resulting. When used, number VCLK cycle slips high Divider value. TCLK always locked VCLK regardless state input.
Lock Detection
MK2069-04 includes lock detection feature that indicates lock status VCLK relative selected input reference clock. When phase lock achieved (such following power-up), output goes high. When phase lock lost (such when input clock stops, drifts beyond pullable range crystal, suddenly shifts phase), output goes low. definition "locked" condition determined user. high when VCXO phase detector error below user-defined threshold. This threshold external components shown Lock Detection Circuit Diagram, below. help guard against false lock indications, will high only when phase error below threshold consecutive phase detector cycles. will when phase error above threshold only phase detector cycle. lock detector threshold (phase error) determined following relationship: Threshold)
Input Phase Compensation Circuit
VCXO includes special input clock phase compensation circuit. used when changing phase input clock, which might occur when selecting reference input through external clock multiplexer. phase compensation circuit allows VCXO quickly lock input clock phase without producing extra clock cycles clock wander, assuming clock same frequency. Input controls phase compensation circuit. must remain high normal operation. When used conjunction with external multiplexer (MUX), should brought prior reselection, then returned high after reselection. This prevents VCXO from attempting lock input clock phase associated with input clock. When high, VCXO operates normally. When low, VCXO charge pump output inactivated which means that charge pump
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MK2069-04 VCXO-Based Universal Clock Translator
Where:
avoid excessive noise leakage) avoid excessive error stray capacitance, which much including LDC) Lock Detector Application example: desired maximum allowable loop phase error generated 19.44MHz clock 100UI which Solution: (0.001 (8.5 Under ideal conditions, where VCXO phaselocked low-jitter reference input, loop phase error typically maintained within nanoseconds.
Power Supply Considerations
with integrated clock device, MK2069-04 special power supply requirements:
feed from system power supply must
filtered noise that cause output clock jitter. Power supply noise sources include system switching power supply other system components. noise interfere with device components such phase detector.
Each must decoupled individually
prevent power supply noise generated device circuit block from interfering with another circuit block.
Clock noise from device pins must onto
power plane system problems result. This above requirements served circuit illustrated Recommended Power Supply Connection (next page). main features this circuit follows:
Lock Detection Circuit Diagram
etection ircuit
tput Lock ualific ation ounter
RESET
Only connection made power
plane.
capacitors ferrite chip ferrite bead)
Error tput
common device supply form lowpass `pi' filter that remove noise from power supply well clock noise back toward supply. bulk capacitor should tantalum type, minimum. other capacitors should ceramic type.
power supply traces individual pins
should common supply filter reduce interaction between device circuit blocks.
Inpu hresh
decoupling capacitors pins should
ceramic type should close possible. There should via's between decoupling capacitor supply pin.
lock detection circuit used, output remain unconnected, however input should tied high low. designed accommodate components output will used, remain unstuffed replaced with resistor kohm).
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MK2069-04 VCXO-Based Universal Clock Translator
Recommended Power Supply Connection
capacitance 14pF. achieve this, layout should short traces between MK2069-04 crystal.
onnection 3.3V Plane
0.01
Recommended Crystal Parameters:
0.01
0.01
0.01
Operating Temperature Range Commercial Applications 70°C Industrial Applications 85°C Initial Accuracy 25°C Temperature Stability Aging Load Capacitance (Note Shunt Capacitance, C0/C1 Ratio Equivalent Series Resistance modes spurs (Note (3xfreq)+/-100ppm Note crystal frequencies between 12MHz 27MHz nominal crystal load capacitance specification should 14pF. Below 12MHz nominal crystal load capacitance should 16pF. Note Crystals used production should screened overtone modes spurs over range crystal frequency) 100ppm, when measured nominal parallel resonant frequency. Failure cause locking problems small percentage production systems certain input frequencies. Please refer application note MAN05 further information. Contact list crystals approved with MK2069-04.
Series Termination Resistor
Output clock traces over inch should series termination maintain clock signal integrity reduce EMI. series terminate trace, which commonly used trace impedance, place resistor series with clock line close clock output possible. nominal impedance clock output
Quartz Crystal
MK2069-04 operates phase-locking VCXO circuit input signal selected ICLK input. VCXO consists external crystal integrated VCXO oscillator circuit. achieve best performance reliability, crystal device with recommended parameters (shown below) must used, layout guidelines discussed following section shown must followed. frequency oscillation quartz crystal determined load capacitors connected MK2069-04 incorporates variable load capacitors on-chip which "pull" change frequency crystal. crystals specified with MK2069-04 designed have zero frequency error when total on-chip stray
Crystal Tuning Load Capacitors
crystal traces should include pads small capacitors from ground, shown External VCXO Components diagram page These capacitors optional later used center total load capacitor adjustment range imposed crystal. load adjustment range includes stray capacitance that varies with board layout. Because typical telecom reference frequency accurate less than ppm, MK2069-04 operate properly without these adjustment capacitors. However, recommends that these capacitors included minimize effects
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variation individual crystals, including those induced temperature aging. value these capacitors (typically determined once given board layout, using procedure described section titled "Optimization Crystal Load Capacitors".
Because each input selection includes internal pull-up device, those inputs requiring logic high state ("1") left unconnected. pins requiring logic state ("0") grounded.
Optional Crystal Shielding
crystal connection traces pins sensitive noise pickup. applications that especially sensitive noise, such SONET G-Bit ethernet transceivers, some following crystal shielding techniques should considered. This especially important when MK2069-04 placed near high speed logic signal traces. following techniques illustrated Recommended Layout drawing. metal layer underneath crystal section should ground layer. Remove other layers that above. This ground layer will help shield crystal circuit from other system noise sources. alternative, layers underneath crystal removed, however this recommended there adjacent PCBs that induce noise into unshielded crystal circuit. channel ground plane around crystal area shown. This will eliminate high frequency ground currents that couple into crystal circuit. through-hole optional third lead offered crystal manufacturer (case ground). requirement this third lead made prototype evaluation. crystal less sensitive system noise interference when case grounded. ground trace around crystal circuit shield from other active traces component layer. external crystal particularly sensitive other system clock sources that near crystal frequency since will lock interfering clock source. crystal should keep away from these clock sources. Applications Note MAN05 also referenced additional suggestions layout crystal section.
Layout Recommendations
optimum device performance lowest output phase noise, following guidelines should observed. Please refer Recommended Layout drawing following page. Each 0.01µF decoupling capacitor (CD) should mounted component side board close possible. via's should used between decoupling capacitor pin. trace should kept short possible, should trace ground via. Distance ferrite chip bulk decoupling from device less critical. loop filter components must also placed close CHGP pins. should closest device. Coupling noise from other system signal traces should minimized keeping traces short away from active signal traces. vias should avoided. external crystal should mounted close device possible, component side board. This will keep crystal traces short which will minimize parasitic load capacitance crystal well noise pickup. crystal traces should spaced away from each other should minimum trace width. There should signal traces near crystal traces. Also refer Optional Crystal Shielding section that follows. minimize series termination resistor, needed, should placed close clock output. components should same side board, minimizing vias through other signal layers (the ferrite bead bulk decoupling capacitor mounted back). Other signal traces should routed away from MK2069-04. This includes signal traces traces just underneath device, layers adjacent ground plane layer used device.
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MK2069-04 VCXO-Based Universal Clock Translator
Recommended Layout Diagram
PPLY EVIC PPLY PLAN
LEAD IELD LAYER PLAN
K2069
1206
Components identified function (top line) typical package type (bottom line) which vary. Legend: Ground plane Power Plane suppression cap, typical value (ceramic) Ferrite chip Bulk decoupling capacitor chip power supply, minimum (tantalum) Bulk bypass chip power supply, typical value 1000 (ceramic) Decoupling capacitor (ceramic) Optional load capacitor crystal tuning stuff) External loop capacitor (film type) External loop capacitor (film type) External loop resistor Resistor RSET used determine charge pump current Series termination resistor clock output, typical value RLD* External resistor lock detector circuit CLD* External capacitor lock detector circuit *Note: output used, omitted. text page
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Optimization Crystal Load Capacitors
concept behind crystal load capacitors introduced page determine need value these capacitors, will need board your final layout, frequency counter capable less than resolution accuracy, power supplies, some samples crystals which plan production, along with measured initial accuracy each crystal specified crystal load capacitance, determine value crystal capacitors: Connect MK2069-04 3.3V. Connect second power supply. Adjust voltage Measure record frequency output. Adjust voltage 3.3V. Measure record frequency same output. calculate centering error:
3.0V Error errorxtal
measurement verify that remaining error acceptably (less than ±15ppm).
Circuit Troubleshooting
TCLK VCLK does lock ICLK
First check VCLK ICLK. best display trigger scope with RCLK, especially non-integer VCXO multiplication ratio used. VCLK locked ICLK: 1.1) Ensure proper ICLK input selected. 1.2) Check RPV, Divider settings 1.3) Ensure ICLK within lock range (within about nominal input frequency, limited pull range external crystal). doubt, tweak ICLK frequency down VCLK locks. 1.4) Ensure ICLK jitter excessive. ICLK jitter excessive device lock. Also item below. 1.5) Clean PCB. VCXO loop filter very sensitive board leakage, especially when VCXO phase detector frequency kHz. organic solder flux used (most common today) scrub board with detergent water then blow bake dry. Inorganic solder flux (Rosen core) requires solvent. also section below.
Where: ftarget nominal crystal frequency errorxtal =actual initial accuracy ppm) crystal being measured centering error less than ppm, adjustment needed. centering error more than negative, board much stray capacitance will need redone with layout reduce stray capacitance. (The crystal re-specified higher load capacitance instead. Contact MicroClock details.) centering error more than positive, identical fixed centering capacitors from each crystal ground. value each these caps given External Capacitor (centering error)/(trim sensitivity) Trim sensitivity parameter which supplied your crystal vendor. know value, assume ppm/pF. After changes, repeat
There Excessive Jitter VCLK TCLK
2.1) problem unstable input reference clock. unstable ICLK will appear jitter when ICLK used oscilloscope trigger source. this condition, VCLK TCLK appear unstable since jitter from ICLK (the trigger source) been removed trigger circuit scope. 2.2) instability caused VCXO loop filter leakage. Refer item above. 2.3) VCLK TCLK jitter also caused poor power supply decoupling. Ensure bulk decoupling capacitor place. 2.4) Ensure that VCXO loop bandwidth sufficiently low. should least 1/20th phase detector frequency.
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MK2069-04 VCXO-Based Universal Clock Translator
2.5) Ensure that VCXO loop damping sufficient. should least 0.7, preferably higher. 2.6) Ensure that pole VCXO loop filter sufficiently. general, should equal C1/20. high, passband peaking will occur loop instability occur. low, excessive VCXO modulation charge correction pulses occur.
3.3) biggest cause input output skew VCXO loop filter leakage. Skew best observed comparing ICLK RCLK. When leakage present rising edge RCLK should rising edge ICLK about µsec. Loop filter leakage greatly increase this time cause loop lock. Refer item 1.5, above. 3.4) Another view loop filter leakage observe pin. RCLK scope trigger. will produce negative pulse equal length charge pump pulse. 3.5) Filter leakage also caused improper loop capacitors. Refer section titled `Loop Filter Capacitor Type' page
There Excessive Input Output Skew
3.1) TCLK should track VCLK. rising edge TCLK should within nanoseconds VCLK. 3.1) VCLK should track RCLK. rising edge VCLK should within 5-10 nsec RCLK (VCLK leads).
Absolute Maximum Ratings
Stresses above ratings listed below cause permanent damage MK2069-04. These ratings, which standard values industrial rated parts, stress ratings only. Functional operation device these other conditions above those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect product reliability. Electrical parameters guaranteed only over recommended operating temperature range.
Item
Supply Voltage, Inputs Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature
Rating
-0.5V VDD+0.5V +85°C +150°C 175°C 260°C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature Power Supply Voltage (measured respect GND)
Min.
+3.15
Typ.
+3.3
Max.
+3.45
Units
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MK2069-04 VCXO-Based Universal Clock Translator
Electrical Characteristics
Unless stated otherwise, 3.3V ±5%, Ambient Temperature +85°C
Parameter
Operating Voltage Supply Current
Symbol
Conditions
clock outputs loaded with VCLK 19.44 MHz, TCLK 155.52
Min.
3.15
Typ.
Max.
3.45
Units
Input High Voltage, RPV1:0, RV11:0, FV11:0, SV1:0, FT2:0, ST1:0 Input Voltage, RPV1:0, RV11:0, FV11:0, SV1:0, FT2:0, ST1:0 Input Pull-Up Resistor (Note Input High Voltage, Input High Voltage, ICLK (Note Input Voltage, ICLK, Input High Current (Note Input Current (Note Input Capacitance, except Output High Voltage (CMOS Level) Output High Voltage Output Voltage Output Short Circuit Current, TCLK Output Short Circuit Current, VCLK, RCLK VIN, VCXO Control Voltage
-0.4
VDD-0.4
VDD/2+1 VDD/2+1
VDD/2-1
-0.4
Note logic select inputs (RPV1:0, RV11:0, FV11:0, SV1:0, FT2:0, ST1:0, CLR) have internal pull-up resistor. Note ICLK safely brought prior application VDD, providing utility hot-plug line card applications.
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MK2069-04 VCXO-Based Universal Clock Translator
Electrical Characteristics
Unless stated otherwise, 3.3V ±5%, Ambient Temperature +85°
Parameter
Crystal Frequency Range (Note VCXO Crystal Pull Range VCXO Crystal Free-Run Frequency (Note Input Clock Frequency when Divider (Note Input Clock Frequency when Divider (Note Input Clock Pulse Width VCXO Phase Detector Frequency (Note VCXO Phase Detector Jitter Tolerance Translator Frequency Clock Period Jitter, VCLK Clock Period Jitter, TCLK Timing Jitter, Filtered 500Hz-1.3MHz (OC-3) Timing Jitter, Filtered 65kHz-5MHz (OC-3) Timing Jitter, Filtered 1kHz-5MHz (OC-12) Timing Jitter, Filtered 250kHz-5MHz (OC-12) Output Duty Cycle high time), VCLK when Divider Output Duty Cycle high time), VCLK when Divider TCLK
Symbol
fXTAL tOJf
Conditions
Using recommended crystal Using recommended crystal Input reference
Min.
13.5 ±115 -300 0.008 0.002
Typ.
Max. Units
nsec
±150 -150
Positive Negative Pulse
0.001
phase detector period Peak-to-peak Peak-to-peak Derived from phase noise characteristics, peak-to-peak sigma Derived from phase noise characteristics, peak-to-peak sigma Derived from phase noise characteristics, peak-to-peak sigma Derived from phase noise characteristics, peak-to-peak sigma Measured VDD/2, CL=15pF Measured VDD/2, CL=15pF
tOJf
tOJf
tOJf
2069-04 Integrated Circuit Systems, Inc.
Race Street, Jose, 95126
Revision 111901 (408) 295-9800
www.icst.com
MK2069-04 VCXO-Based Universal Clock Translator
Parameter
Output High Time, RCLK (Note Output Rise Time, VCLK RCLK Output Fall Time, VCLK RCLK Output Rise Time, TCLK Output Fall Time, TCLK Skew, ICLK VCLK (Note Skew, ICLK RCLK (Note Skew, ICLK TCLK (Note Nominal Output Impedance
Symbol
Conditions
Measured VDD/2, CL=15pF 2.0V, CL=15pF 0.8V, CL=15pF 2.0V, CL=15pF 0.8V, CL=15pF Rising edges, CL=15pF Rising edges, CL=15pF Rising edges, CL=15pF
Min.
Typ.
VCLK Period 0.75 0.75
Max. Units
Note This recommended crystal operating range. crystal used, although this result increased output phase noise. Note VCXO crystal will pulled minimum frequency when there input clock (CLR attempt lock Note minimum practical phase detector frequency kHz. Through proper loop filter design lower input frequencies possible. Input frequencies 400Hz have been tested. Note higher input clock frequency used when divider Note output RCLK positive pulse with duration equal VCLK high time, half VCLK period. Note Referenced ICLK, skews VCLK, RCLK TCLK increase together when leakage present external VCXO loop filter.
2069-04 Integrated Circuit Systems, Inc.
Race Street, Jose, 95126
Revision 111901 (408) 295-9800
www.icst.com
MK2069-04 VCXO-Based Universal Clock Translator
Package Outline Package Dimensions
TSSOP 6.10 (240 mil) body, 0.50 mil) pitch Package dimensions kept current with JEDEC Publication
Millimeters Symbol
Inches
AREA
-1.20 0.05 0.15 0.80 1.05 0.17 0.27 0.09 0.20 13.90 14.10 8.10 BASIC 6.00 6.20 0.50 Basic 0.45 0.75 -0.10
-0.047 0.002 0.006 0.032 0.041 0.007 0.011 0.0035 0.008 0.547 0.555 0.319 BASIC 0.236 0.244 0.020 Basic 0.018 0.030 -0.004
Ordering Information
Part Order Number
MK2069-04GI MK2069-04GITR
Marking
MK2069-04GI MK2069-04GI
Shipping packaging
Tubes Tape Reel
Package
TSSOP TSSOP
Temperature
+85° +85°
While information presented herein been checked both accuracy reliability, Integrated Circuit Systems (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial applications. other applications such those requiring extended temperature range, high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments.
2069-04 Integrated Circuit Systems, Inc.
Race Street, Jose, 95126
Revision 111901 (408) 295-9800
www.icst.com
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