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ADM6509 10/100 Base-TX INTEGRATED 9-PORT SWITCH CONTROLLER Overview
ADM6509 single chip nine ports switch device. device contains eight 10/100BASE-T/TX transceivers, nine Media Access Controllers (MACs), non-blocking switching fabric, packet buffer. This allows simple system cost solution design switch product. There eight based full duplex 10BASE-T/100BASE-TX transceivers. auto-negotiation function determines selection either 10BASE-T 100BASE-TX mode. 10BASE-T transceiver operates primarily over unshielded twisted pair (UTP) cable while 100BASE-TX, Fast Ethernet, operates primarily over cable. device fully complies with IEEE 802.3u specification that determines requisite registers, coding waveforms ensure proper transmitter receiver operation. device contains nine internal 802.3 compliant MAC. Each 10/100BaseT/TX capable. Each full half duplex capable. full duplex mode, 802.3x PAUSE frame based flow control supported. half duplex mode, flow control provided with backpressure. This method will generate carrier signal when receive buffer full. Each supports maximum frame sizes either 1522 1536 bytes. ports provide address learning recognition maximum frame rates. address table supports addresses internally. Addresses added table after receiving error free packet. Broadcast multicast frames forwarded non-receiving ports. ADM6509 implemented .25u CMOS technology. This technology provides lower power device. featured PQFP package.
Features
1.Eight-port 10/100BaseT/TX port 2.Non-blocking nine-port switching controller with controller, switching engine, packet buffer which offer cost simple solution. 3.System clock input 25MHz Crystal Oscillator 4.Store-and- forward operation support. 5.Full line speed capability 14880 packet/sec 148810 packet/sec 100M, with blocking. 6.Broadcast storming prevention 7.Support groups port-based VLAN 8.Full-duplex (IEEE802.3x) three-way half-duplex flow control (Back pressure) 9.Data buffer SSRAM embedded 10.CoS support: Port-based, VLAN tag, TCP/IP TOS/DS, custom defined 11.Intelligently back-pressure flow control turned on/off port with priority frames 12.Buffer management included 13.93C46 EEPROM interface 14.Per port LEDs provided 15.Buffer full faulty provided 16.Bridging functions such Local address filtering direct mapping hashing schemes better address coverage Aging function included with configurable aging time Embedded entries address table 17.Low power CMOS technology with 3.3V tolerance 18.160-pins Plastic Quad Flat Package
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ADM6509 Specification
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Block Diagram
N-WAY Monitor
EEPROM Configuration
Data Buffer
Link Table
Address Table
Control Switch Fabric
From port port
TMAC RMAC TMAC RMAC
TMAC RMAC From port port
10/100
10/100
From port port
Example System Diagram
Crystal
ADM6509 9-port switch
EEPROM (Option)
Transformer
Transformer
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ADMtek Incorporated
VSSA VSST VSST VSSA VSSA VSST VSST VSSA
Diagram
ADM6509 Specification
August 2001
ADM6509
Industrial Road, SBIP, Hsin-Chu
VSSA VSST VSST VSSA VSSA VSST VSST VSSA
Version 1.01
www.admtek.com.tw
(03)578-8879 (03)578-8871
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ADM6509 Specification
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Descriptions
Name Media Connections
{0-7}, {0-7} {0-7} {0-7} L-2,3,14,15,17,18,29,30 R-90,91,102,103,105,106,117,118 L-6,7,10,11,21,22,25,26 R-94,95,97,98,109,110,113,114 Receive Pair. Differential data received this pin. Transmit Pair. Differential data transmitted this pin.
Type
Descriptions
Clock
XTAL25i XTAL25o crystal, external clock input crystal
Management port. ports floated need.
MDIO Clock input MDIO. runs 1MHz frequency clock port auto-negotiation result monitoring.
Bi-directional serial used write read form registers device. Carrier Sense Collision Transmit Enable Transmit Data
Interface
RXDV RXD[0] RXD[1] RXD[2] RXD[3] Transmit Clock Receive Clock Receive Data Valid Receive Data
EEPROM Interface (Option). pins floated configuration need.
EESK EECS EEDI EEDO Clock Input serial EEPROM Chip Select serial EEPROM Data Input serial EEPROM Data Output serial EEPROM
Display
ADMtek Incorporated August 2001
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ADM6509 Specification 155,154,153 152,151,150 148,147,146 144,143,141 140,138,137 135,134,133 131,130,129 128,127,126
www.admtek.com.tw Status Indicators shown below: Name Mode0 (default) Mode1 LEDM[0-1] LED0[0-2]-LED7[0-2] Link/activity (Steady/Flash) Speed (Steady) Duplex/Col(Steady/Flash) Link/Activity (Steady/Flash) Speed (Steady) Duplex Link/Activity (Steady/Flash) the10M mode Link/Activity (Steady/Flash) 100M mode Duplex/Col (Steady/Flash) Link/Activity (Steady/Flash) Speed (Steady) (Flash)
Mode2
Mode3
Note: mean need pull-up resistor.
Configuration Pins
LEDM[0-1] Test Pins QFLED PORT_PRI[0. 32,33 42,43,44,46,47,48,49,50,51 self test Reserved 54,56 83,85,86 Status Ports Configuration Pins (Internal pull down) Back Pressure Mode. pull down, back pressure (Default internal pull-up, disable) Full Duplex Flow Control, pull down, pause frame flow control (Default: internal pull disable)
Bias
REF_RES Reference Voltage. Connected VSSA 12.1K resistor. Reset. Active When toggled, chip recalls configuration data from EEPROM. (Floated, ignore function) Positive Power Digital Core,2.5V Positive Power I/O, 3.3V Positive Power Analog circuitry, 2.5V Positive Power Analog circuitry, 3.3V
Miscellaneous
RESET RECALL
Power
VDDL VDDH VDDAL VDDAH 40,55,71,81,124,132,149 4,13,19,28,92,101,107,116 1,16,31,89,104,119
ADMtek Incorporated August 2001
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ADM6509 Specification 34,36,38,41,52,60,65,79,82,88, 122,123,125,139,145,157,159
www.admtek.com.tw Digital circuit, core
VSSA 5,12,20,27,93,100,108 Analog circuitry Note: Power pins, VDDX VSSX required connected proper operation device.
Function Description
7.1.1 Overview ADM6509 embedded ports Ethernet (physical layer) device. capable operating either 10Mbps 100Mbps. associated with Physical Layer model. performs functions between Medium dependent interface) internal switch. According IEEE 802.3u, contains (physical coding sublayer), PMA( physical medium attachment), PMD( physical medium attachment), optional AutoNegotiation functions. This data converted form specified IEEE 802.3 transmission cable. Conversely, capable receiving signals from cable converting these signals into digital data sent sublayer. 100BASE-TX mode, ADM6509 takes data from MACs performs physical layer 4B/5B encoding, scrambling, parallel serial conversion, NRZI conversion NRZI MLT-3 conversion transmission over cable. receive path uses adaptive equalizer take MLT-3 signals from cable, performs clock recovery, perform MLT-3 NRZI conversion, NRZI conversion, de-scrambling data, 4B/5B decoding, performs data alignment, stores data elasticity buffer then converts nibble data that applied theMACs. Auto-Negotiation, carrier sense, collision detection implemented device logic. Similarly, 10BASE-T mode, Manchester encoding decoding used with level transmitted received data cable. 7.1.2 Link Detect 10Base-T 100Base-TX different means signaling link integrity. link detect function uses counter count number edges receive signal over given period. When enough edges counted three consecutive periods, link detect established. number edges will determine whether link 10Base-T 100Base-TX. 7.1.3 Auto-Negotiation Auto-Negotiation(AN) mechanism defined IEEE 802.3u implemented. When function enabled, mode operation will automatically chosen advertising abilities comparing them with those received from link partner. Each transceiver port advertise 100Base-Tx full duplex, 100Base-T half duplex, 10Base-T full half duplex. Each transceiver will negotiate independently with link partner choose highest level operation available link. enable/disable/force EEPROM. 7.1.4 Digital Adaptive Equalizer 100Base-TX transmission through transmission media causes signal distortion characterized wideband loss, baseline wander, jitter, frequency errors intersymbol interference. adaptive equalizer function conditions incoming 100Base-T receive signal compensate this distortion. Transceivers that utilize analog methodology equalize subject system noise degrading their performance while digital methodology provides better noise immunity with tradeoff high power consumption. This design uses optimal combination analog digital techniques resulting superior performance signal recovery with power consumption. This equalizer uses forward analog equalization digital decision feedback equalization(DFE). Gain, offset, baseline wander, jitter frequency error addressed compensated. This technique enables outstanding performance 100meters twisted pair even noisy environments. 10Base-T transmission utilizes pre-equalization technique, adaptive equalizer bypassed.
ADMtek Incorporated August 2001
Industrial Road, SBIP, Hsin-Chu Version 1.01
(03)578-8879 (03)578-8871 ADMtek Incorporated Confidential
ADM6509 Specification
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7.1.5 Clock Recovery clock recovery function based equalized signal sampled with clock with feedback mechanism shift sampling point optimum position. This recovered clock used synchronize other functions "Receive" section especially data recovery data transmittal. 7.1.6 Stream Cipher Scrambler/ De-scrambler reduce radiated emissions twisted pair cable, scrambling function implemented randomize data. data combined with 11bit wide linear shift register producing 2047 repeating sequence. de-scrambling function requires that data synchronized aligned. de-scrambler monitors recovered data sequence representing idle codes achieve synchronization with transmit shift register. Once pattern deciphered, data then retrieved further processing. 7.1.7 Encoder/Decoder reduce radiated emissions, ensure bandwidth spread, ensure sufficient signal transitions clock recovery, provide framing 100Base-TX mode, IEEE 802.3 provides 4B(4bit data nibble symbol) conversion. well, MLT-3 line coding introduced limit signal transitions half peak value cycle. Thus significantly reducing emissions above MHz. Thus signal encoded transmission along line decoded upon signal recovery.
ADMtek Incorporated August 2001
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Switch Engine
7.2.1 Hashing Function ADM6509 provides address look-up table, 4-layers embedded address table implement address recognition. Using 4-layer address table reduce address collision rate. entry hashing table calculated direct mapping function produce 10-bit hashing address entry. 7.2.2 Learning Process Address learning process composed packets hashing function. security mode, ADM6509 will compare source address (SA) each incoming packet: source address incoming packet same source address table, then aging status port number will updated. source address differs from source address table there empty layer, port number, aging status will stored onto empty layers. source address different from source address table there empty layer, i.e. none four layers vacant, then learning process will occur. 7.2.3 Routing When packet comes, ADM6509 will compare destination address with address lookup table. addresses port numbers same, means that this local packet, routing function will discard addresses same port numbers different, packet unicast packet, will forwarded assigned port. incoming packet broadcasted one, multicast one, unknown (i.e. address cannot found lookup table), then routing scheme will broadcast ports. 7.2.4 Forwarding ADM6509 provides store-and-forward method forwarding scheme. Each outgoing packet will stored buffer first, then directly sent assigned port. However, only good non-local packets will sent. 7.2.5 Buffer Management buffer memory (SSRAM) embedded ADM6509 nine-port switch operations, which designed based output queuing dynamic shared memory management architecture. will assign buffer resources based traffic status. addition, this method avoid problem (Head-on-Line) blocking cause better transmitting performance. 7.2.6 Flow Control (Patent Pending) on/off status flow control depends global empty buffer count per-port waiting-transmit count. Based this intelligent scheme, packet transmits full port, then flow control will turned off. 7.2.6.1 Full Duplex full duplex flow control, ADM6509 follows IEEE 802.3x standards. ADM6509, PAUSE frame received from certain port, ADM6509 will stop port transmission packets until timer timeout another PAUSE frame with zero time received. buffer full full-duplex mode, ADM6509 will send PAUSE frame with maximum value, defer receiving packet. When enough buffer space released, PAUSE frame with zero delay sent. 7.2.6.2 Half Duplex half duplex operation, ADM6509 supports backpressure features. free blocks buffer memory below threshold, packet (jam mode) carrier sense (carrier mode) sent connected segment, regardless routing decisions. mode, number programmed EEPROM. carrier mode, will provide better connection, with repeaters that prevent connected port repeater from switching partition state jam.
7.2.7 EEPROM Dynamic configured 8051 EEPROM configuration option 9-port switch setting, recalls after power-on reset. 8051 emulate EEPROM interface update content toggle RECALL. block diagram below.
ADMtek Incorporated August 2001
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ADM6509 Specification
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EEPROM
6509
8051
RECALL
7.2.8 EEPROM Content
EEPROM setting must 16-bit mode. Offset Content recommend Check Pattern (6508) System (1000) Configuration Description
Must 6508 [3:0] Inter Frame half duplex mode only. Default zero time). sign bit. When zero, means negative. present decimal value time (times four). example, 1010, equal 104. Bit[7:4] Configurable aging time. Default sec. When one, fast aging time sec) set. zero, aging timer disabled. other value, list below. Aging time (Default) Aging time Aging time 1200 Aging time 2400 Aging time 4800 Aging time 9600 Aging time 38400 Bit[9:8] Broadcast storming mode. This mode only broadcast destination address Disable (Default) blocks blocks blocks Bit[11:10] Maximum Length data field frame format. Maximum length 1536 bytes (Default) Maximum length 1518 bytes Maximum length 1522 bytes
ADMtek Incorporated August 2001
Industrial Road, SBIP, Hsin-Chu Version 1.01
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ADM6509 Specification
www.admtek.com.tw Reserved
Continuous 16-time collision abort packet enabled zero. Default one. Hashing algorithm selection. zero, direct mapping algorithm selected. Otherwise, hashing algorithm adopted. Default zero. Must zero. Must zero. Back Pressure Bit[2:0] Must Back-off Bit[6:4] Must Bit[11:8] number algorithm (recommend value: 1010) Bit[13:12] mode disableBP jamALL carrier (Default) (Default) Bit[7:0] auto-negotiation disable port7 port0 [7:0]. Enable (Default) Bit[15:8] Port disable port7 port0 [7:0]. Enable (Default) Bit[15:14] port7. bit[13:12] port6 etc. reserved, 10Base only, 100Base only, 10/100Base both Bit[7] port7, bit[6] port6 etc. half/full duplex both, half only Bit[8:0] Port group port8 port0, Default 01FFh. Bit[8:0] Port group port8 port0, Default 0000h. Bit[8:0] Port group port8 port0, Default 0000h. Bit[8:0] Port group port8 port0, Default 0000h. Bit[8:0] Port group port8 port0, Default 0000h. Bit[8:0] Port group port8 port0, Default 0000h. Bit[8:0] Port group port8 port0, Default 0000h. Bit[8:0] Port group VIII port8 port0, Default 0000h.
Port7-0 setting
Port7-0 force speed Port7-0 force duplex VLAN1 Port-Group VLAN2 Port-Group VLAN3 Port-Group VLAN4 Port-Group VLAN5 Port-Group VLAN6 Port-Group VLAN7 Port-Group VLAN8 Port-Group
802.3x flow Bit[7:0] port7 port0 enabled[7:0], stands Enable. enabled, must control Half duplex mode. Back Bit[15:8] port7 port0 802.3x flow control enabled[7:0]. stands Disable pressure enable (Both default determined pins) Port8 setting Bit[0] port8 disable, 0:enable(dft) Bit[1] port8 NWAY monitor disable, 0:enable
ADMtek Incorporated August 2001
Industrial Road, SBIP, Hsin-Chu Version 1.01
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ADM6509 Specification
www.admtek.com.tw Bit[2] port8 speed NWAY monitor disable), 0:10M Bit[3] port8 duplex NWAY monitor disable), 0:half Bit[4] port enable, 0:disable pin) Bit[5] 802.3x flow control enable, 0:disable pin) Bit[6] write FC-bit(10th bit)of register4 [7:0] port8 (wxfc_en) enable (dft) Bit[8] port8 high priority port, 0:disable (dft) Bit[9] enable port8 VLAN priority, 0:disable (dft) Bit[10] enable port8 priority, 0:disable (dft) Bit[11] enable port8 auto-off BP/FC, priority packet, 0:disable (dft) Bit[8:0] Force port8 port0 802.3x flow control (ignore AN). enabled, must full duplex. stands disable (Default).
Force 802.3x flow control
Reserved Must 12CH (Bit[15:0]) Reserved Must 150H Reserved Must Reserved Must Reserved Must 170H Reserved Must 194H Reserved Must 170H Reserved Must 194H Reserved Must Reserved Must 106H Reserved Must 0C18H Priority Frame Bit[7:0] Auto turn BP/FC port7-0, priority packet [7:0]. stands disable operation (Default) Bit[11:8] -Round-robin(sequential) number high priority frame example follows: bit11 bit10 bit9 bit8 Weighted ratio unlimited Weighted ratio Weighted ratio Weighted ratio (Default) Must -Must Priority enable, stands enable (Default). priority port Bit[15:8] priority port7-0, stands check (Default). port. e.g. port port Bit[7:0] high priority port port7-0, priority (default) VLAN Bit[7:0] VLAN priority port[7:0], stands check (Default). port. e.g. port port Bit[15:8] First, ADM6509 will check specific bits recorded type field packet format verify VLAN status packets, then threshold VLAN. default threshold threshold packet high priority. port. e.g. port port Bit[15:0] Default First, ADM6509 will check specific bits recorded type field TCP/IP packet format, verify status packets, then implement bits mapping priority setting each port. Bit[15:0] Default First, ADM6509 will check specific bits recorded type field TCP/IP packet format, verify status packets, then implement bits mapping priority setting each port. Bit[15:0] Default First, ADM6509 will check specific bits recorded type field
ADMtek Incorporated August 2001
Industrial Road, SBIP, Hsin-Chu Version 1.01
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ADM6509 Specification
www.admtek.com.tw TCP/IP packet format, verify status packets, then implement bits mapping priority setting each port. Bit[15:0] Default First, ADM6509 will check specific bits recorded type field TCP/IP packet format, verify status packets, then implement bits mapping priority setting each port. Must Must Must Must Must Must Must Must
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
operation Bit[4:0] -PHY rewrite register address. These bits present register address selection. rewrite. Default zero (disable). Bit[12:8] port8 (MII port). Default 00H. Bit[15:13] N/A. operation Bit[15:0] rewrite data. After rewrite register address selected, register each port rewrite data. Reserved Bit[15]: soft reset, bit[14:0]: must 113H Custom priority Bit[8:0] mean port8 custom priority disable (default) enable Custom type When enable, Ethernet type field IEEE standard) must matched Custom offset When enable, base offset (byte number) check custom define byte. Custom define When enable, Bit[15:8] custom defined byte content Bit[7:0] mask bit, ignore
7.2.8 Priority Frame (CoS) Operations ADM6509 packets high priority follows:
Port Number (set pin) VLAN TCP/IP TOS/DS Custom type (all EEPROM)
priority setting port means that packets received port will priority frames; ADM6509 also judge priority frames checking specific bits VLAN TCP/IP TOS/DS frame. ADM6509 will determine packet priority. First will check packet type meets VLAN TCP/IP. Then, will check whether value VLAN TCP/IP TOS/DS field meets register setting. ADM6509 also check custom proprietary packet type 8-bit mask-able data which adjust offset counted from type field. match, packet treated priority one. Depending these conditions, scheme weighted round robin determine high priority frames, thus transmitting order. When port receives priority frame, back pressure 802.3x flow control turned until priority frame occurs within seconds, then turned back again (Patent Pending). This programmable function EEPROM.
ADMtek Incorporated August 2001
Industrial Road, SBIP, Hsin-Chu Version 1.01
(03)578-8879 (03)578-8871 ADMtek Incorporated Confidential
ADM6509 Specification
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7.2.9 VLAN Broadcast Storming Prevention ADM6509 supports VLAN function ease administration logical groups stations that communicate they were same LAN, move, change numbers these groups. ADM6909 also supports port-groups scheme effectively prevent broadcast storming from interfering with whole transmission performance between ports. ports divided into groups while broadcast storming starts; then broadcast frames transmitted destination port belonging other groups will prohibited. During this time, ports belonging different groups independent. Only destination port broadcast frames same group will allowed. Furthermore, scheme port-group dividing very flexible. overlapped port-groups allowed during some operations, example, port shared groups, other operations between these groups remain independent except overlapped port. Only overlapped port could same different VLAN port-groups. ADM6509 also provide broadcast storming protection function which will block incoming broadcast packet accumulated broadcast packet buffer larger than EEPROM setting.
ADMtek Incorporated August 2001
Industrial Road, SBIP, Hsin-Chu Version 1.01
(03)578-8879 (03)578-8871 ADMtek Incorporated Confidential
ADM6509 Specification
www.admtek.com.tw
Electrical Specification Timing
Absolute Maximum Ratings
Absolute maximum ratings specifications that indicate levels where permanent damage device occur. Functional performance device reliability guaranteed under these conditions. voltages specified with respect GND. Supply Voltage -.3V 4.0V Input Voltage -.3V 5.0V Output Voltage -.3V 5.0V Storage Temperature -40C 125C Ambient Temperature Protection 2000V
Specifications
Parameter VDDH VDDAH VDDL VDDAL VDDT IDDL IDDH Description Supply Voltage Supply Voltage Condition 2.25 2.75 Unit
Power Supply Power Supply Input High Voltage Input Voltage Input High Current Input Current Output High Voltage Output Voltage
Transmitting Transmitting
Auto-Negotiation Timing
Parameter TPWL TPPD TCPDP TFBD TPWB Description Link Test Pulse Width Clock Pulse Clock Pulse Clock Pulse Data Pulse Burst Interval Burst width Number Burst pulses Condition 55.5 69.5 Unit pulses
ADMtek Incorporated August 2001
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ADM6509 Specification
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Fast link Pulse Timing
Clock Pulse Data
Pulse TPWL
Clock Pulse
TCPDP TPPD TFBD
TPWB
Management Interface Timing
Parameter TMDCC TMDCH/ TMDCL TMDCR/ TMDCF TMDIOS TMDIOH TMDIOD Description Cycle Time High/ Time Rise/Fall Time Rising Edge MDIO Input Setup Time MDIO Input Hold Time Rising Edge MDIO Output Delay Rising Edge Condition Unit
Management Interface Timing
TMDCC TMDCH TMDCL
TMDIOS TMDIOH
MDIO
TMDIOD
MDIO (output)
ADMtek Incorporated August 2001
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ADM6509 Specification
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Management Interface Timing (Preamble Suppression)
MDIO Suppress Preamble -PHY Address-REG Address-TA-DATA Bits-
Specifications
8.8.1 EEPROM Timing
Parameter
Description
EECK (50% duty cycle) EECS/EEDI delay from falling EECK idle time EECS EEDO valid before rising EECK EEDO hold after rising EECK
Condition
1280 4000
Units
ADMtek Incorporated August 2001
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ADM6509 Specification 8.8.2 Transmit Receive Timing
www.admtek.com.tw
Parameter
Description
TXEN/TXD delay from rising TXCLK RXDV/RXD valid before rising RXCLK RXDV/RXD hold from rising RXCLK pulse width MDIO delay from rising MDIO valid before rising MDIO hold after rising
Condition
25MHz
Units
Package Outline
ADMtek Incorporated August 2001
Industrial Road, SBIP, Hsin-Chu Version 1.01
(03)578-8879 (03)578-8871 ADMtek Incorporated Confidential
ADM6509 Specification
www.admtek.com.tw
Revision History
Revision date
August 2001
Revision
1.01
Description
1.supplement description VDDL VDDH, Port_Pri[0.8] Ref_Res page correct description eeprom setting page
ADMtek Incorporated August 2001
Industrial Road, SBIP, Hsin-Chu Version 1.01
(03)578-8879 (03)578-8871 ADMtek Incorporated Confidential
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