BluetoothBaseband Controller Variable input clock frequency 16C55

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BluetoothBaseband Controller Variable input clock frequency 16C55

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BluetoothBaseband Controller
Variable input clock frequency 16C550 UART interfaces bits general purpose interface Full-speed compliant interface JTAG Debug Test interface Capability embedded solutions External flexible Flash sizes, 2-16 Mbit Point multipoint, slaves Power management, PARK, SNIFF HOLD Qualified Bluetooth spec.
Description
Bluetooth Baseband from Ericsson Microelectronics generic baseband controller designed suitable both host embedded applications. baseband controller will together with radio module Flash memory form complete Bluetooth system. generic product, used many different types applications that require Bluetooth capability such Data Voice access points Cable replacement networking based scalable Ericsson Bluetooth Core (EBC) architecture. system controller embedded ARM7 TDMImicroprocessor communicating with peripheral interfaces over AMBAsystem bus. This configuration allows embedded stand-alone Bluetooth applications where your target application embedded within baseband controller, addition traditional host-based applications. This possibility especially useful accessory type applications like cordless headsets, industrial sensor actuator devices. Providing wide range external interfaces like USB, I2C, GPIO, pair UARTS, ideally suited access applications desktop mobile computing environments, home base stations, spot network access points.
Block diagram
lock Dividers
ARM7
ystem ontroller, ers, atchdog
64kByte 4kByte
Interrupt ontroller TESTEN NTRS xternal
ebug
0.15
Misc. ontrol
ricsson Bluetooth Start tect utobaud
DATA MCLK
Figure Block diagram.
Absolute Maximum Ratings
Parameter Condition Symbol Unit
supply range, groups Core supply range Input voltage range Output voltage range Input clamp current VSSIO VDDIO Output clamp current VSSIO VDDIO Operating ambient temperature range Storage temperature
VDDIO VDDCORE TAmb TStg
-0.3 -0.3 -0.3 -0.3
+3.6 +2.8 VDDIO +0.3 VDDIO +0.3 +125
Characteristic Data
Static data Unless otherwise stated: VDDCORE VDDIO 2.5V ;VSS TAmb -40.+85°C
Parameter Condition Symbol Unit
Supply voltage Core Supply voltage group Supply voltage group Supply voltage group Supply voltage group Supply current level input voltage, digital input High level input voltage, digital input Schmitt trigger input Schmitt trigger input Input leakage current level output voltage High level output voltage Output leakage current, tri-state
Guaranteed input Guaranteed input high Hysteresis 0.49 Hysteresis 0.49 VSSIO VDDIO =800 =-800 VSSIO VDDIO
VDDCORE VDDIO1 VDDIO2 VDDIO3 VDDIO4
VDDCORE VDDCORE VDDCORE VDDCORE VSSIO 1.42 0.92 VDDIO -0.1
VDDIO+0.3 1.46 0.97 VSSIO+0.1 VDDIO
1.45 0.94
Notes static data:
core voltage greater than either voltages about more, then will work. This because inputs core from pads will sufficiently high level drive core gates. level shifter between core only designed shift from core high I/O. core voltage off, voltage left then this will cause drive logic output pins. example NEXTWR, NEXTRD, EXTDATA three NEXTCS signals will driven which will result Bidirectional clash databus several external units driving bus. pins connected external driving before turning supply, without chip being damaged. However cannot guaranteed that does load external this case, unless core supply voltage completely discharged prior this event.
Dynamic data
Requirements input pins Conditions: Rise fall times measured between VDDIO level.
Type Symbol Parameter Unit
input pins
Rise time Fall time
Requirements
Input frequency Symbol Parameter Unit
facc Using PLL: facc Example frequencies: 12.60, 12.80, 13.00, 14.40, 16.80, 19.20, 19.44 Requirements LPOXIN
Input frequency Symbol
Without using PLL:12.40
Frequency accuracy Jitter Duty cycle Frequency accuracy Jitter Duty cycle
Parameter
Unit
3.200
32.000
32.768
facc facc facc
Frequency accuracy Jitter Duty cycle Frequency accuracy Jitter Duty cycle Frequency accuracy Jitter Duty cycle
Digital output pins characteristics Conditions: TAmb CLoad VDDCORE 2.7V, VDDIO Rise fall times measured between VDDIO level.
Type Symbol Parameter Unit
digital output bi-directional output pins drive, Transceiver pins characteristics
Rise time Fall time
10.0 10.0
Conditions: TAmb CLoad VDDCORE VDDIO2
Symbol Parameter Unit
tr/tf ZDRV Note:
Transition Rise Fall time Transition Rise/Fall time ratio Cross-over voltage Driver output resistance (See Note)
Excluding external resistor. order comply with specification, external resistors each branches recommended.
characteristics generate higher internal clock frequencies from input clock on-chip included adapted different input frequencies programmable registers. Register values following common crystal frequencies have been defined: 12.60, 12.80, 13.00, 14.40, 16.80, 19.20 19.44 MHz. internal current reference block, IREF, which disabled when used order save power. start-up time dependent whether IREF enabled prior start not.
Symbol Parameter Unit
tst1 tst2
Input frequency Start-up time, IREF enabled before start Start-up time, IREF disabled before start
13.00
Connection
DATA1
DATA0
NEXTRD
ADDR0
NEXT
ADDR16
VDDIO1
CORE
UART2
NRESET
PCMA
PCMB
DATA10
DATA9
DATA8
DATA3
TA11
VSSIO3
CORE
UART2
VSSIO1
USBVT_ WAKUP
SYNC
DATA
DATA
UART1
UART1
VDDIO
VSSIO3
VSSIO2
VDDIO2
DATA13
DATA12
UART1 USBDM
UART1 UART1 DCD_ USBDP
DATA7
DATA15
ADDR15
ADDR9
ADDR14
DATA14
Core supply pins group pins group pins group pins group pins
ADDR13
ADDR17
VDDIO3
VSSIO3
ADDR11
ADDR6
ADDR8
ADDR3
NEXT
ADDR1
ADDR2
ADDR5
DATA
ADDR12
NEXT
CORE
ADDR19
ADDR7
ADDR4
ADDR18
ADDR10
CORE
NEXT
Figure configuration (top view, balls face down).
description
name direction type Reset state group Functional description
Input clock interface pin)
System input clock (square wave)
System controller interface pins)
NRESET LPOXIN NSYSWAKUP SYSCLKREQ
DO3T
System reset (active low) power operation clock (square wave) System external wakeup (active low) System clock request (tri-stateable)
Vterm wakeup interface pin)
USBVT_EBCWAKUP
Vterm wakeup
External interface pins)
NEXTCS0 NEXTCS1 NEXTCS2 NEXTRD NEXTWR EXTADDR0 EXTADDR1 EXTADDR2 EXTADDR3 EXTADDR4 EXTADDR5 EXTADDR6 EXTADDR7 EXTADDR8 EXTADDR9 EXTADDR10 EXTADDR11 EXTADDR12 EXTADDR13 EXTADDR14 EXTADDR15 EXTADDR16 EXTADDR17 EXTADDR18 EXTADDR19 EXTDATA0 EXTDATA1 EXTDATA2 EXTDATA3 EXTDATA4 EXTDATA5 EXTDATA6 EXTDATA7 EXTDATA8 EXTDATA9
External chip select External chip select External chip select External read strobe External write strobe External address line External address line External address line External address line External address line External address line External address line External address line External address line External address line External address line External address line External address line External address line External address line External address line External address line External address line External address line External address line External data line External data line External data line External data line External data line External data line External data line External data line External data line GPIOB0 External data line GPIOB1
name direction type Reset state group Functional description
EXTDATA10 EXTDATA11 EXTDATA12 EXTDATA13 EXTDATA14 EXTDATA15
External data line GPIOA2 External data line GPIOA3 External data line GPIOA4 External data line GPIOA5 External data line GPIOA6 External data line GPIOA7
interface pins)
SERIALCLK SERIALDATA
serial clock (GPIOA0) serial data (GPIOA1)
interface pins)
PCMA PCMB PCMCLK PCMSYNC
digital serial audio channel digital serial audio channel digital serial audio clock digital serial audio sync pulse
Radio interface pins)
TXCLK TXDATA TXON PHDOFF PXON SYNTON RXDATA RXON CDCLK
Radio transmit data clock, Radio transmit data Radio transmitter Radio phase detector loop Radio packet Radio synthesizer Radio receive data Radio receiver Radio serial control clock Radio serial control data input Radio serial control data output Radio serial control mode select
UART1 interface pins)
UART1CTS UART1DSR UART1DTR UART1RTS UART1RX UART1TX UART1DCD_USB UART1RI_USBDM
BD3, BD3,
UART1 clear send UART1 data ready UART1 data terminal ready UART1 request send UART1 receive data UART1 transmit data UART1DCD USBDP UART1RI USBDM
UART2 interface pins)
UART2RX UART2TX
UART2 receive data UART2 transmit data
name direction type Reset state group Functional description
Debug Test interface pins)
TESTEN NTRST
DO3T
Test enable (pull-down, active high) JTAG clock (pull-up) JTAG data (pull-up) JTAG data JTAG mode select (pull-up) JTAG reset (pull-down)
Power pins)
VDDCORE VDDCORE VDDIO1 VDDIO2 VDDIO3 VDDIO3 VDDIO4 VSSCORE VSSCORE VSSIO1 VSSIO2 VSSIO3 VSSIO3 VSSIO3 VSSIO4
GND,
Core supply Core supply group supply group supply group supply group supply group supply Core ground Core ground group ground group ground group ground group ground group ground group ground
Notes description: direction: Input, Output, Bi-directional, Analog input Reset state: High, Low, Tri-state, High types: DO3T Input Input with pull-up (Resistor: Input with pull-down (Resistor: Schmitt trigger input Analog drive, output Tri-stateable drive, output drive, bi-directional output Core power supply power supply power supply transceiver shared with UART1 pins.
Other information: pins which defined inputs application connected driving external circuit must pulled either VDDIO i.e. must floating. only pins that have on-chip pull resistors Debug Test Interface input pins. names that start with active low.
Mechanical description, package
ball corner Seating Plane
Mechanical Drawing
ball indicator NOTES maximum allowable number solder balls maximum solder ball matrix size basic solder ball grid pitch 0.50mm. dimensions tolerances conform ASME Y14.5M-1994. Unless otherwise stated.
8.00 0.05
Dimension measured maximum solder ball diameter, parallel primary datum Primary datum seating plane defined spherical crowns solder balls. ball corner I.D. marked laser.
8.00 0.05
0.08 0.10 0.12 0.75
0.50
0.50 0.75
0.320
0.050
0.15 0.08
BOTTOM
Seating Plane
0.22 0.06 0.085 0.65 0.04 0.85 0.10
Ball Corner Indicator Solder Ball)
Figure Mechanical Drawing.
Functional Description
Overview purpose this section give brief description features functions product work system. figure one-chip solution, packaged into package, footprint with 0.50 pitch 0.85 building height. handles baseband functionality Bluetooth radio link, i.e. digital controller logic. baseband functionality partitioned hardware software part. software part executed on-chip microprocessor ARM7 TDMI. increase ease use, standard interfaces like Full-speed, UARTs, integrated chip. philosophy provide scalable solution with high level flexibility. goal offer solution that easily added existing system thus enabling Bluetooth capabilities. solution offers designers: Power versus performance trade-offs Reduced need external components (osc's, etc) save power, interfaces individually turned processor speed adapted produce suitable capacity depending what application running. radio part requires crystal clock frequency with accuracy. designed flexible this matter re-use square clock signal wide spectrum frequencies depending kind reference signal used radio. software also able offer flexibility choice brand size Flash memory. both flexibility scalability. system architecture based around ARM7 TDMI processor, executing Bluetooth stack drivers, Hardware block: Ericsson Bluetooth Core supporting Bluetooth Standard 1.1. supported interfaces: Full-speed UARTs used access chip from host system. Peripheral components such Flash, RAM, ROM, etc. connected through External Interface. External Interface configurable variety peripheral components. together with Bluetooth radio Flash holding firmware, forms Bluetooth radio link, figure
Ericsson Bluetooth Core (EBC)
name Bluetooth dedicated hardware designed offload processor taking care heavy calculation tasks such whitening, check, ciphering data, forward error correction Bluetooth packet segmentation reassemble. compliant with Bluetooth specification revision includes following features: link support giving data rates kbit/s over interface. link with support three voice channels over interface. support packet types. Support PCM-channel. Architecture designed power consumption. Hold, sniff, parked modes Ciphering keys bits High quality filtering voice packets enables excellent audio quality. Flexible voice formats host over (CVSD, PCM, 16/8 complement, signed, A-law, µ-law). Point multipoint with support slaves. Master/Slave switch capability Radio interface compliant with BlueRF interface V0.9, Unidirectional mode, RXMODE2.
Architecture
Bluetooth functionality based both hardware software, forming embedded system design targeting
Flash
Intel Toshiba
Data Ctrl Addr
Base Band Chip
Blue
Bluetooth Radio
Ericsson Others
Host System
Codec
UART (max kb/s) Mb/s)
Figure Example system using
Host interfaces
enable host system access Bluetooth radio link, Host Controller Interface (HCI) been defined. host system controls distributes data from Bluetooth Link Manager with commands. These commands carried physically either UART interface.
UARTs
There on-chip UART 16C550 compatible interfaces, UART1 UART2. UART1 byte FIFOs full modem control support used data transmission rates kbit/s. UART1 setup configuration default. changed configuration software. then become outputs, swapped with swapped with externally.
Name
UART1CTS UART1DSR UART1DCD UART1RI UART1RTS UART1DTR
Full-speed
serial interface supporting Mbit/s. interface "Plug Play" nature therefore easy equipment that constantly moved around. interface implemented based Full-speed version standard configured endpoints: Control endpoint with bytes buffer. Isochronous endpoints (Rx/Tx) Double buffered with bytes each buffer. Bulk transfer endpoints (Rx/Tx) Double buffered with bytes each buffer. Interrupt endpoint with bytes buffer. divided into three parts, PHY, core, driver software integrated firmware. integrated PHY, necessary analog line driver signalling, thus avoiding external component. simplified configuration where only used, means that interface does require power from host. core digital hardware part handling packet transmission reception. also handles level control. software driver integrated firmware delivered with chip. Measured throughput (USB-airlink-USB) Packet type Full Duplex 420/420 kbit/s Half Duplex kbit/s
configuration
Clear Send input Data Ready input Data Carrier Detect input Ring Indicator input Request Send output Data Terminal Ready output
configuration
Request Send input Data Terminal Ready input Data Carrier Detect output Ring Indicator output Clear Send output Data Ready output
other UART, UART2 byte FIFOs used control and/or boot. UART2 only pins available support rates kbit/s. Start-detect Auto-baud functionality available both UARTs.
Default Settings UART1, UART2 Speed 57600 bit/s Data Stop Parity None Flow CTS/RTS (Not applicable UART2)
Note: These settings changed from level using Ericsson specific commands.
ARM7 TDMI
AMBA
UART UART GPIO Test Interface
Host
GPIO Debug Test
External Interface SRAM
Bluetooth Radio
Blue
Ericsson Bluetooth Core
Figure Architecture.
Other interfaces
External Interface External Interface allows designer peripheral circuits included memory map. support three memory banks each offering address range 1024 positions individually configurable memory mapped registers described below. Memory bank used Flash memory holding firmware executing processor. Bank used expand other components. Each memory bank configured according table right:
Configuration type Access type Memory width Burst mode Write protect Write protect error status flag transfer error status flag Wait state write accesses Options retry, Retry after every access Retry after every four memory accesses 16-bit Non-burst devices burst Error, error Clear flag Error, error Clear flag 1.32 internal system clock cycles wait state(s) (SRAM) 0.31 clock cycles wait state(s) (burst ROM) 1.32 internal system clock cycles wait state(s) 1.16 internal system clock cycles wait state(s) access
Wait state read accesses turnaround cycles between read write
Address Data
Flash
External Interface
NEXTRD NEXTWR NEXTCS0 NEXTCS1 NEXTCS2
Figure External interface.
wait state
Int. Addr. [31:0] EXTADDR[19:0] EXTDATA[15:0] Int. Data [31:0] NEXTCS[X] NEXTRD
Valid Valid Valid 0x00000000 Valid
Figure Example external wait state read access.
GPIO
supports General Purpose I/O's. bits GPIO available default these also used interface. bits extra GPIO obtained using most significant bits data bus. interface function based software using GPIO's. interface capacity handling approximately kbit/s. different configurations GPIO controlled memory mapped registers described below.
GPIO register name Function GPIOACCEN GPIOPADDR Select between external data external data extra GPIO. Data direction register GPIOA bits. Each GPIOA setup either input output. Data direction register GPIOB bits. Each GPIOB setup either input output. Data register GPIOA bits. This register used apply read data from GPIOA bits. Data register GPIOB bits. This register used apply read data from GPIOB bits. Interrupt control register This register selects available GPIO bits connected GPIO interrupt also sets polarity edge properties, enable clear interrupt. Interrupt control register This register selects available GPIO bits connected GPIO interrupt also sets polarity edge properties, enable clear interrupt.
Interface (PIF) block provides interface between serial transfer lines Receive Transmit voice blocks inside EBC. This interfacing task involves: Synchronization between asynchronous clock domains Direction switching bi-directional data control signals Synchronous serial data parallel data conversion. supports channel interface. line interface either slave master. When line interface slave frequency range PCMCLK (in) MHz. When line interface master PCMCLK (out) always MHz. Each symbol received PCMA PCMB line organized 16-bit sequence bits, arriving synchronous PCMCLK line interface slave) PCMCLK line interface master). symbol starts with most significant arriving after positive edge PCMCLK out), clock cycle after PCMSYNC out) positive transition. symbol then transferred each PCMCLK out) clock cycle until least significant transferred. then samples arriving falling edges PCMCLK out). symbols transmitted starting with MSB, clock cycle after positive edge PCMCLK line interface slave) PCMCLK line interface master), clock cycle after PCMSYNC out) positive transition. rest bits then transferred each PCMCLK out) cycle, synchronized with rising edge this clock.
required receive. PCMCLKx
GPIOPBDDR
GPIOPADR
GPIOPBDR
GPIOINTC1
GPIOINTC2
PCMSYNCx
PCMxin
0,1,or
MSB-1
MSB-2
MSB-3
MSB-4
0,1,or
Figure interface receive timing diagram.
This pulse overlaps with first pulse when symbols aligned. This necessary disable output. PCMCLKx
PCMSYNCx
PCMxout
0,1,or
MSB-1
MSB-2
MSB-3
MSB-4
0,1,or
Figure interface transmit timing diagram.
Debug interface
support development smaller applications, JTAG based debug interface. debug interface opens possibility access processor system Multi-ICEusing debug environment such 1.1from Ltd. System clock divider System clock defines speed processor. important have enough capacity when using UART kb/s. frequency changed from level writing memory mapped register change value divider parameters (SYSCLKXDIV, SYSCLKYDIV), which have following relation: SYSCLK CLKMAIN
ARM7 TDMI processor
This system based around ARM7 TDMI microprocessor. ARM, together with ROM, RAM, System controller, External Interface external Flash forms processor system, which executes Bluetooth firmware. system offers some flexibility terms system performance, power management scalability. configuration done writing memory mapped registers.
SYSCLKXDIV SYSCLKYDIV
Note: values between 255. X-value must less than equal Y-value. UART clock divider frequency UART clock depends what rate required. 921.6 kbit/s frequency 14.7456 required. relation between UARTCLK CLKMAIN programmed setting divider parameter values (UARTXDIV, UARTYDIV) according expression below: CLKBAUD CLKMAIN
System controller Miscellaneous control
These functions handle system configuration power management. They configure built-in PLL, deactivate blocks that used, adjust system frequency match performance needed application, etc. This flexibility important power management. Figure below illustrates clock generation built from input clock.
UARTXDIV UARTYDIV
Note: values between 255. X-value must less than equal Y-value. Bluetooth clock, CLK4M, divider Bluetooth part chip, EBC, needs clock frequency. This clock trimmed using divider suit frequency available SYSCLK. important notice that CLK4M function SYSCLK therefore function SYSCLK parameter values. CLK4M SYSCLK
feedback divider
This block controls feedback divider Phase Locked Loop. combining input clock, programmable divider, able operate with wide variety input clock frequencies. that designer will able re-use existing system clock constrained frequency requirements, thus reducing need additional discrete components (such oscillator). following formula used derive input frequencies that supported 137; fXIN
CLK4MXDIV CLK4MYDIV
CLK4MXDIV CLK4MYDIV
CLK4M CLKMAIN
SYSCLKXDIV SYSCLKYDIV
Note: values between 255. X-value must less than equal Y-value.
Writing memory mapped register sets value
feedback divider
USBCLK
Programmable Dividers
CLKMAIN
UARTCLK CLK4M SYSCLK
Programmable Divider
Programmable control:
Figure Clock generation.
power operation (LPO) clock support
This function essential wake function. When radio link unused, circuit will power saving mode inactivating other blocks including PLL. this time clock small number gates only active logic circuit. associated logic activates processor periodically page- inquiryscan. clock input, LPOXIN requires external 32.768 square wave.
Software
Bluetooth link partitioned into hardware part software part. software relates Bluetooth protocol stack. Depending level integration, there will different firmware models available, including hardware specific drivers Bluetooth core, USB, UARTs, GPIO I2C. level integration follows scenarios: firmware Embedded Bluetooth stack firmware
Vterm wakeup support
These functions shared same USBVT_EBCWAKUP selected memory mapped register. Only functions used given system configuration. USBVT functionality: default state after reset Vterm output pin. Vterm output used either connect disconnect external termination resistor between USB_DP VDDIO2 (3.3 this case). connect indicates that high speed unit attached line. disconnect indicates that unit detached from line. default state after reset disconnect, i.e. USBVT tristated. EBCWAKUP functionality: alternative function active high wakeup input pin. This used external unit order start Bluetooth scan procedure.
firmware
this configuration customer will access through Host Controller Interface (HCI) protocol distributed over UART. figure
Embedded Bluetooth stack firmware
This configuration opens possibility customer build small applications based chip, using processor main processor. figure
System wakeup power operation
NSYSWAKUP active unconditional system wakeup input pin. connected VDDIO4 this functionality used.
Application
UART
RFCOMM L2CAP
Running
UART/USB
Host System Controller
Running:
UARTs GPIO
Running: Stack Customer
Figure Embedded Bluetooth stack firmware.
Figure firmware.
Information given this data sheet believed accurate reliable. responsibility assumed consequences infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Ericsson Microelectronics. These products sold only according Ericsson Microelectronics' general conditions sale, unless otherwise confirmed writing. Specifications subject change without notice.
Ericsson Microelectronics
SE-164 Kista, Sweden local sales contacts, please refer website call: Fax:
Preliminary Data Sheet
EN/LZT Ericsson Microelectronics December 2001

BluetoothBaseband Controller Variable input clock frequency 16C55

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