QUALITY SEMICONDUCTOR, INC. QuickSwitch® Products High-Speed CMOS

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QUALITY SEMICONDUCTOR, INC. QuickSwitch® Products High-Speed CMOS

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QS34XST257 ADVANCE INFORMATION
QUALITY SEMICONDUCTOR, INC.
QuickSwitch® Products High-Speed CMOS SynchroSwitch32:16 Mux/Demux With Active Terminators
DESCRIPTION
QS34XST257 ADVANCE INFORMATION
FEATURES/BENEFITS
Enhanced channel with inherent diode Bidirectional signal flow Flow-through pinout Zero propagation delay, zero ground bounce banks Mux/Demux Port select synchronous clock Clock enable Asynchronous enable "Bus hold" terminators demux side Undershoot clamp diodes switch control pins Asynchronous option Break-before-make feature Available 80-pin MillipaQ (Q3) Bus-hold eliminates floating lines reduces static power consumption
QS34XST257 high speed CMOS quad 32:16 multiplexer/demultiplexer with active terminators (bus-hold circuits) demux side. organized four independent quad mux/demux blocks. Port selection connection, controlled signals, either asynchronous synchronous. synchronous mode, port port connection updated rising edge input clock CLK. Once port-to-port connection made, data flow bi-directional with typical 250ps propagation delay through switch. Clock Enable, over-riding Asynchronous Enable, Asynchronous Select controls provide additional design flexibility. bus-hold circuits latch last data driven demux side, providing infinite hold time glitch-free signal transitions. Synchronous controls bus-hold ease timing constraints many high speed data mux/demux applications such bank interleaving. QS34XST257 available space-saving, 80-pin dual-in-line MillipaQ package.
APPLICATIONS
Video, audio, graphics switching, muxing funneling
Figure Functional Block Diagram
SELn CLKn CLKENn SYNCn
CONTROL LOGIC
Note: four blocks shown MDSL-00214-00 JULY 1997 QUALITY SEMICONDUCTOR, INC.
QS34XST257 ADVANCE INFORMATION
Table Description
Name An0.An3 Bn0.Bn3 Yn0.Yn3 SELn CLKn CLKENn SYNCn Description Demux Port Demux Port Port Select Input Clock Clock Enable Output Enable Synchronous Selection Enable
Figure Configuration (All Pins View)
MillipaQ (Q3)
SEL0 CLKEN0 CLK0 SYNC0 SEL1 CLKEN1 CLK1 SYNC1 SEL2 CLKEN2 CLK2 SYNC2 SEL3 CLKEN3 CLK3 SYNC3
Figure Control Logic*
*One four blocks shown
SELn CLKENn CLKn SYNCn Port Switches Port Switches
QUALITY SEMICONDUCTOR, INC.
MDSL-00214-00 JULY 1997
QS34XST257 ADVANCE INFORMATION Table Function Table
CONTROL INPUTS PORT STATUS Select Port Select Port FUNCTION
CLKENn SYNC CLKn CLKEN SELn
change connection Hold previous data(1) (Switch OFF) change connection Hold previous connection(2) (Switch change connection Hold previous data(3) (Switch OFF) Select Port Select Port
change connection Hold previous data (Switch OFF)
Notes: switches turned terminators (last value latches) hold previous data state. port connection changed input. contents "mux select register" unchanged previous connection unchanged. output (Mux port) data state will depend present data state input (Demux port). contents "mux select register" unchanged last value latches hold previous data state.
Table Absolute Maximum Ratings
Supply Voltage Ground -0.5V +7.0V Switch Voltage -0.5V +7.0V Input Voltage -0.5V +7.0V Input Voltage (for pulse width 20ns) -3.0V Output Current Max. Sink Current/Pin 120mA Maximum Power Dissipation 85°C 1.16 watts TSTG Storage Temperature -65° +150°C
Note: ABSOLUTE MAXIMUM CONTINUOUS RATINGS those values beyond which damage device occur. Exposure these conditions conditions beyond those indicated adversely affect device reliability. Functional operation under absolute-maximum conditions implied.
Table Capacitance
25°C, 1MHz, VOUT Pins Control Inputs QuickSwitch Channels (Switch OFF) Demux MillipaQ Unit
Note: Capacitance guaranteed, production tested. total capacitance while switch please Section under "Input Switch Capacitance."
MDSL-00214-00 JULY 1997
QUALITY SEMICONDUCTOR, INC.
QS34XST257 ADVANCE INFORMATION Table Electrical Characteristics Over Operating Range
-40°C 85°C, 5.0V Symbol Parameter IBHL IBHH Input HIGH Voltage Input Voltage Input Leakage Current (Control Inputs) Test Conditions Guaranteed Logic HIGH Control Pins Guaranteed Logic Control Pins Typ(1) 500(4) Unit
Switch Resistance(2,3) Min., 0.0V, 30mA Min., 2.4V, 15mA Input Hold Current port)(6) Input Current(7,8) port
Min. Switch Max.
0.8V 2.0V 2.0V
Notes: Typical values indicate 5.0V 25°C. Measured voltage drop between indicated current through switch. diagram explaining procedure measurement, please Section under Electrical Characterization." guaranteed, production tested. external driver must provide least during transition guarantee that Bus-hold input will change states. IBHL Minimum sustaining `sink' current input 0.8V. This parameter signifies latching capability Bus-hold circuit logic state. IBHH Minimum sustaining `source' current input 2.0V. This parameter signifies latching capability Bus-hold circuit logic HIGH state. Magnitude input current specified under conditions: Input voltage This indicates input current under steady-state condition. Input voltage between 0.8V 2.0V (TTL input threshold range). This indicates maximum input current during transient condition. driver connected input must overcome this current requirement order switch logic state Bus-hold circuit.
Figure Typical Resistance 5.0V
(ohms)
(Volts)
QUALITY SEMICONDUCTOR, INC.
MDSL-00214-00 JULY 1997
QS34XST257 ADVANCE INFORMATION Table Power Supply Characteristics Over Operating Range
-40°C 85°C, 5.0V Symbol ICCQ QCCD Parameter Quiescent Power Supply Current Power Supply Current(2) Control Input HIGH Dynamic Power Supply Current MHz(3) Test Conditions(1) Max., VCTRL VCC, Max., 3.4V, Max., Pins Open, Control Input Toggling Duty Cycle 0.25 Unit
Notes: conditions shown Min. Max., appropriate values specified under specifications. driven control inputs. pins contribute ICC. This current applies control inputs only represents current required switch internal capacitance specified frequency. inputs generate significant currents they transition. This parameter guaranteed, production tested.
Table Switching Characteristics Over Operating Range
-40°C 85°C, 5.0V CLOAD 50pF, RLOAD unless otherwise noted. Symbol tPLH tPHL tSEC tHEC tCSO tASO tSCS tHCS tPZL, tPZH tPLZ, tPHZ Description(1) Data Propagation Delay(2,3) Clock Enable Clock Setup Time Clock Enable Clock Hold Time Clock Switch Turn-on Delay
Unit
0.25
Asynchronous Select Switch Turn-on Delay(4) Clock Pulse Width (High) Clock Setup Time Clock Hold Time Asynchronous Enable Switch Turn-on Delay(4) Asynchronous Enable Switch Turn-off Delay
(2,4)
Notes: Test Circuit Waveforms. This parameter guaranteed, production tested. switch contributes propagation delay other than delay resistance switch load capacitance. time constant switch alone order 0.25ns 50pF. Since this time constant much smaller than rise/fall times typical driving signals, adds very little propagation delay system. Propagation delay switch when used system determined driving circuit driving side switch interaction with load driven side. Minimums guaranteed production tested.
MDSL-00214-00 JULY 1997
QUALITY SEMICONDUCTOR, INC.
QS34XST257 ADVANCE INFORMATION Figure Timing Waveforms Synchronous Mode, Demux Function
SYNC
tSEC tHEC
CLKEN
tSCS tHCS tSCS tHCS
Port
DATA0
DATA1
tPLH, tPHL
DATA2
tCSO
Port INVALID DATA
Port
DATA0
DATA1
HOLD PREVIOUS DATA, DATA1
PLH, tPHL
tCSO
INVALID DATA
DATA1 DATA2
HOLD PREVIOUS DATA, DATA2
QUALITY SEMICONDUCTOR, INC.
MDSL-00214-00 JULY 1997
QS34XST257 ADVANCE INFORMATION Figure Timing Waveforms Synchronous Mode, Function
SYNC
tSEC tHEC
CLKEN
tSCS tHCS tSCS tHCS
SEL0, SEL1
Port
DATA1
DATA2
Port
INVALID DATA
tCSO tPLH, tPHL
DATA1
DATA3
tCSO
DATA4
tPLH, tPHL
Port
INVALID DATA
DATA2
DATA3
DATA4
MDSL-00214-00 JULY 1997
QUALITY SEMICONDUCTOR, INC.
QS34XST257 ADVANCE INFORMATION Figure Timing Waveforms Asynchronous Mode, Function
SYNC
Port
INVALID DATA
DATA1
tPLH, tPHL
DATA2
tPLH,
Port
INVALID DATA
DATA3
tASO
tPLZ, tPHZ
DATA3
tPZL, tPZH
Port
INVALID DATA
DATA1
DATA2
DATA3
QUALITY SEMICONDUCTOR, INC.
MDSL-00214-00 JULY 1997
QS34XST257 ADVANCE INFORMATION ACTIVE TERMINATOR 'BUS-HOLD' CIRCUIT
Active Terminator circuit, also known Bus-hold circuit, configured `weak latch' with positive feedback. When connected CMOS input port, Bus-hold circuit holds last logic state input when input `disconnected' from driver. When output device connected such input attempts logic level transition, will overdrive Bus-hold circuit. primary benefit Bus-hold circuit that prevents CMOS inputs from floating, situation which should avoided prevent spurious switching inputs unnecessary power dissipation. Bus-hold better solution than traditional approach using resistive termination prevent floating, because Bus-hold circuit does consume static power.
Figure Characteristics Bus-hold Circuit
Sinking Current
IBHL IBHH
IBHL
IBHH
Voltage
Sourcing Current
-500
Threshold Voltage 1.5V
Figure Shows input characteristics typical Bus-hold implementation. input characteristics resemble resistor. input voltage increased from volts, input `sink' current increases linearly. When threshold circuit reached (typically Volts), latch changes logic state positive feedback direction current reversed. input voltage further increased towards VCC, input `source' current begins decrease, reaching lowest level VCC.
MDSL-00214-00 JULY 1997
QUALITY SEMICONDUCTOR, INC.

QUALITY SEMICONDUCTOR, INC. QuickSwitch® Products High-Speed CMOS

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