QUALITY SEMICONDUCTOR, INC. QuickSwitch® Products High-Speed CMOS

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QUALITY SEMICONDUCTOR, INC. QuickSwitch® Products High-Speed CMOS

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QS34XST253
QUALITY SEMICONDUCTOR, INC.
QuickSwitch® Products High-Speed CMOS SynchroSwitch32:8 Mux/Demux With Active Terminators
DESCRIPTION
QS34XST253
FEATURES/BENEFITS
Enhanced channel with inherent diode Bidirectional signal flow Flow-through pinout Zero propagation delay, zero ground bounce banks Mux/Demux Port select synchronous clock Clock enable Asynchronous enable "Bus hold" terminators demux side Asynchronous option Break-before-make feature Undershoot clamp diodes switch control pins Available 80-pin MillipaQ Bus-hold eliminates floating lines reduces static power consumption
QS34XST253 high-speed CMOS 32:8 multiplexer/demultiplexer with active terminators (bus-hold circuits) demux side. organized four independent dual mux/demux blocks. Port selection connection, controlled signals, either asynchronous synchronous. synchronous mode, port port connection updated rising edge input clock CLK. Once port-to-port connection made, data flow bi-directional with typical 250ps propagation delay through switch. Clock Enable, over-riding Asynchronous Enable, Asynchronous Select controls provide addiitonal design flexibility. bus-hold circuits latch last data driven demux side, providing infinite hold time glitchfree signal transitions. Synchronous controls bus-hold ease timing constraints many high speed data mux/demux applications such bank interleaving. QS34XST253 available space-saving, 80-pin dual-in-line MillipaQ package.
APPLICATIONS
Video, audio, graphics switching, muxing
Figure Functional Block Diagram
OEn0 OEn1 SELn0 SELn1 CLKn CLKENn SYNCn
Control Logic
Note: four blocks shown. MDSL-00213-00 JULY 1997 QUALITY SEMICONDUCTOR, INC.
QS34XST253 Table Description
Name An0.Dn0 An1.Dn1 Yn0, SELn0, SELn1 CLKn CLKENn OEn0, OEn1 SYNCn Description Demux Ports Demux Ports Ports Select Inputs Clock Clock Enable Output Enable Synchronous Enable
Figure Configuration (All Pins View)
MillipaQ (Q3)
OE00 OE01 SEL00 SEL01 CLKEN0 CLK0 SYNC0 OE10 OE11 SEL10 SEL11 CLKEN1 CLK1 SYNC1 OE20 OE21 SEL20 SEL21 CLKEN2 CLK2 SYNC2 OE30 OE31 SEL30 SEL31 CLKEN3 CLK3 SYNC3
Figure Control Logic
OEn0
SELn0 CLKENn CLKn SYNCn
Bank Switches
DECODE LOGIC SWITCH CONTROL
SELn1
Bank Switches
OEn1
QUALITY SEMICONDUCTOR, INC.
MDSL-00213-00 JULY 1997
QS34XST253 Table Function Table
CONTROL INPUTS SYNCn OEn0 OEn1 CLKn CLKENn SELn0 SELn1 PORTS
Hold previous data(1) Hold previous data(1) (Switch OFF) (Swich OFF) Hold previous connection(2) (Switch Hold previous connection(2) (Switch
Hold previous data(3) Hold previous data(3) (Switch OFF) (Switch OFF)
Hold previous data (Switch OFF)
Hold previous data (Switch OFF)
Notes: switches turned terminators (last value latches) hold previous data state. port connections changed input. contents "mux select register" unchanged previous connection unchanged. output (Mux port) data state will depend present data state input (Demux port). contents "mux select register" unchanged last value latch holds previous data state.
Table Absolute Maximum Ratings
Supply Voltage Ground -0.5V +7.0V Switch Voltage -0.5V +7.0V Input Voltage -0.5V +7.0V Input Voltage (for pulse width 20ns) -3.0V Output Current Max. Sink Current/Pin 120mA Maximum Power Dissipation 85°C 1.16W TSTG Storage Temperature -65°C +150°C
Note: ABSOLUTE MAXIMUM CONTINUOUS RATING those values beyond which damage device occur. Exposure these conditions conditions beyond those indicated rating adversely affect device reliability. Functional operation under absolute-maximum conditions implied.
Table Capacitance
25°C, 1MHz, VOUT Pins Control Inputs QuickSwitch Channels (Switch OFF) Demux MillipaQ Unit
Note: Capacitance guaranteed, production tested. total capacitance while switch please Section under "Input Switch Capacitance."
MDSL-00213-00 JULY 1997
QUALITY SEMICONDUCTOR, INC.
QS34XST253 Table Electrical Characteristics Over Operating Range
-40°C 85°C, 5.0V Symbol IBHL IBHH Parameter Input HIGH Voltage Input Voltage Input Leakage Current (Control Inputs) Switch Resistance(2) Test Conditions Guaranteed Logic HIGH Control Pins Guaranteed Logic Control Pins Min., 0.0V, 30mA Min., 2.4V, 15mA Input Hold Current(3,4) Input Current(5) 4.50V Switch Max. 0.8V 2.0V 2.0V Typ(1) 500(5) Unit
Notes: Typical values indicate 5.0V 25°C. Measured voltage drop between indicated current throught switch. diagram explaining procedure measurement, please Section under Electrical Characteristics." guaranteed, production tested. external driver must provide least during transition guarantee that Bus-hold input will change states. IBHL Minimum sustaining `sink' current input 0.8V. This parameter signifies latching capability Bus-hold circuit logic state. IBHH Minimum sustaining `source' current input 2.0V. This parameter signifies latching capability Bus-hold circuit logic HIGH state. Magnitude input current specified under conditions: Input voltage This indicates input current under steady-state condition. Input voltage between 0.8V 2.0V (TTL input threshold range). This indicates maximum input current during transient condition. driver connected input must overcome this current requirement order switch logic state Bus-hold circuit.
Figure Typical Resistance 5.0V
(ohms)
(Volts)
QUALITY SEMICONDUCTOR, INC.
MDSL-00213-00 JULY 1997
QS34XST253 Table Power Supply Characteristics Over Operating Range
-40°C 85°C, 5.0V Symbol ICCQ QCCD
Notes: conditions shown Min. Max., appropriate values specified under specifications. driven input (VIN=3.4V, control inputs only). A/B/C/D pins contribute ICC. This current applies control inputs only represents current required switch internal capacitance specified frequency. A/B/C/D inputs generate significant currents they transition. This parameter guaranteed, production tested.
Parameter Quiescent Power Supply Current Power Supply Current Control Input HIGH(2) Dynamic Power Supply Current MHz(3)
Test Conditions(1) Max., VCC, Max., 3.4V, Max., A/B/C/D Pins Open, Control Input Toggling Duty Cycle
0.25
Unit
Table Switching Characteristics Over Operating Range
-40°C 85°C, 5.0V CLOAD 50pF, RLOAD unless otherwise noted.
Symbol tPLH tPHL tSEC tHEC tCSO tASO tSCS tHCS tPZL, tPZH tPLZ, tPHZ
Description(1) Data Propagation Delay(2,3) A/B/C/D A/B/C/D Clock Enable Clock Setup Time Clock Enable Clock Hold Time Clock Switch Turn-on Delay
Unit
QS34XST253 0.25
Asynchronous Select Switch Turn-on Delay(4) Clock Pulse Width (High) Clock Setup Time Clock Hold Time Asynchronous Enable Switch Turn-on Delay(4) Asynchronous Enable Switch Turn-off Delay
(2,4)
Notes: Test Circuit Waveforms. This parameter guaranteed, production tested. switch contributes propagation delay other than delay resistance switch load capacitance. time constant switch alone order 0.25ns 50pF. Since this time constant much smaller than rise/fall times typical driving signals, adds very little propagation delay system. Propagation delay switch when used system determined driving circuit driving side switch interaction with load driven side. Minimums guaranteed production tested.
MDSL-00213-00 JULY 1997
QUALITY SEMICONDUCTOR, INC.
QS34XST253 Figure Timing Waveforms Synchronous Mode, Demux Function
Example: Port Port A/Port
SYNC
tSEC tHEC
CLKEN
tSCS tHCS tSCS tHCS
tCSO
Port
DATA0 DATA0 INVALID DATA
DATA1
tPLH, tPHL
DATA2
Port INVALID DATA
DATA1
HOLD PREVIOUS DATA, DATA1
PLH, tPHL
tCSO
Port
DATA1 DATA2
HOLD PREVIOUS DATA, DATA2
QUALITY SEMICONDUCTOR, INC.
MDSL-00213-00 JULY 1997
QS34XST253 Figure Timing Waveforms Synchronous Mode, Function
Example: Port A/Port Port
SYNC
tSEC tHEC
CLKEN
tSCS tHCS tSCS tHCS
SEL0, SEL1
Port
DATA1
DATA2
Port
tCSO tPLH, tPHL tCSO
DATA3
DATA4
tPLH, tPHL
Port
INVALID DATA
DATA1
DATA2
DATA3
DATA4
MDSL-00213-00 JULY 1997
QUALITY SEMICONDUCTOR, INC.
QS34XST253 Figure Timing Waveforms Synchronous Mode, Function
Example: Port A/Port Port
SYNC
Port
INVALID DATA
DATA1
tPLH, tPHL
DATA2
tPLH,
Port
INVALID DATA
DATA3
tASO
tPLZ, tPHZ
DATA3
tPZL, tPZH
Port
INVALID DATA
DATA1
DATA2
DATA3
QUALITY SEMICONDUCTOR, INC.
MDSL-00213-00 JULY 1997
QS34XST253 ACTIVE TERMINATOR 'BUS-HOLD' CIRCUIT
Active Terminator circuit, also known Bus-hold circuit, configured `weak latch' with positive feedback. When connected CMOS input port, Bus-hold circuit holds last logic state input when input `disconnected' from driver. When output device connected such input attempts logic level transition, will overdrive Bus-hold circuit. primary benefit Bus-hold circuit that prevents CMOS inputs from floating, situation which should avoided prevent spurious switching inputs unnecessary power dissipation. Bus-hold better solution than traditional approach using resistive termination prevent floating, because Bus-hold circuit does consume static power.
Figure Characteristics Bus-hold Circuit
Sinking Current
IBHL IBHH
IBHL
IBHH
Voltage
Sourcing Current
-500
Threshold Voltage 1.5V
Figure Shows input characteristics typical Bus-hold implementation. input characteristics resemble resistor. input voltage increased from volts, input `sink' current increases linearly. When threshold circuit reached (typically Volts), latch changes logic state positive feedback direction current reversed. input voltage further increased towards VCC, input `source' current begins decrease, reaching lowest level VCC.
MDSL-00213-00 JULY 1997
QUALITY SEMICONDUCTOR, INC.

QUALITY SEMICONDUCTOR, INC. QuickSwitch® Products High-Speed CMOS

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