Edition 2000-07 Published Infineon Technologies St.-Martin-Strasse D-8

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Edition 2000-07 Published Infineon Technologies St.-Martin-Strasse D-8

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Edition 2000-07 Published Infineon Technologies St.-Martin-Strasse D-81541 Germany
Infineon Technologies 7/13/00. Rights Reserved.
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I
3452 PRELIMINARY Revision History: Previous Version: Page
2000-07 none
Subjects (major changes since last revision)
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3452 PUCCINIV1.2
PRELIMINARY
Preface
This document describes changes implemented PUCCINIversion related previous version 1.1. intended give overview improved functionality device. functions mentioned this document remain unchanged. Organization this Document This Delta Sheet organized follows: Chapter Overview Gives general description product differences predecessor. Chapter Description Functional Enhancements Shows functional enhancements current version detail. Chapter Descriptions This chapter describes modified functions. Chapter Application Example Shows principle application circuit.
Related Documentation Preliminary Data Sheet 3452 V1.1
Your Comments welcome your comments this document. continuously trying improving documentation. Please send your remarks suggestions e-mail sc.docu_comments@infineon.com Please provide subject your e-mail: device name (PUCCINITM), device number (PEB 3452), device version (Version 1.2), body your e-mail: document type (Delta Sheet), issue date (2000-07) document revision number
Delta Sheet 2000-07
3452 PUCCINIV1.2
PRELIMINARY Overview
Overview
Functional Enhancements
Version PUCCINIis compatible upgrade version 1.1. addition previous device, integrated transmit jitter attenuator provided.
Device Marking Pattern
complete marking pattern
Engineering Samples:
Final Devices:
3452 V1.2 PUCCINI Germany
3452 V1.2 PUCCINI Germany
F0215
Figure
Marking Pattern
Delta Sheet
2000-07
3452 PUCCINIV1.2
PRELIMINARY Description Functional Enhancements
Description Functional Enhancements
PUCCINIVersion provides integrated transmit jitter attenuator, reducing number external components required jitter attenuation minimum. jitter attenuation buffer jitter attenuation integrated on-chip. Only pullable quartz required externally. This quartz frequency nominal clock frequency allow cost effective realization. jitter attenuation enabled single additional control signal, which makes device compatible version 1.1. complete block diagram shown below.
Autom. Gain Control Level Detection ALOS Detection LOS, Detection
Gain Stage
Noise Filter
Var. Gain Amplifier
Equalizer
Clock Data Recovery
Decoder
RCLK RDOP RDON/BPV
REFCLK Local Loop Transmit Jitter Attenuator XTAL1 XTAL2 JATT
DR/SR LCODE DS3/STS1/E3 Remote Loop
Line Driver
Pulse Shaper
Jitter Attenuator Buffer
Insertion
Encoder
XCLK XDIP XDIN
Hardware/µP Interface General Control
XAIS Test Mode Control
DR/SR LCODE DS3/STS1/E3
DS3/E3 DS3/STS-1 XAIS LCODE DR/SR JATT
REFCLK
Figure
Delta Sheet
V1.2
F0159
Block Diagram
2000-07
3452 PUCCINIV1.2
PRELIMINARY Jitter Attenuation Jitter reduced intransmit direction, jitter attenuator activated (JATT JATT control signal enables/disables JPLL activates/bypasses buffer. jitter attenuator consists buffer PLL. jitter attenuation deliveres 'jitter-free' clock (nominal frequency divided Table transmit which generates buffer read clock. jitter attenuation uses pullable quartz with tuning range ppm. jitter attenuator uses 64-bit dual rail buffer fulfills requirements GR-499CORE GR-253-CORE shown Figure avoid need high frequency quartz devices, reference clock jitter attenuation only third nominal frequency. detailed block diagram transmit clocking given Figure below. Table Jitter Attenuation Operation Frequencies Jitter Attenuation Input Frequency 44.736 51.840 34.368 Jitter Attenuation Output Frequency 14.912 17.280 11.456 Quartz Frequency Description Functional Enhancements
Operation mode
STS-1
14.912 17.280 11.456
Further requirements external quartz: Motional capacitance: Shunt capacitance: Load capacitance: Resistance:
Delta Sheet
2000-07
3452 PUCCINIV1.2
PRELIMINARY Description Functional Enhancements
XAIS
fnom REFCLK JATT XTAL1 XTAL2 disable testmode fnom fnom Transmit
Jitter Attenuator XAIS fnom
fnom
XCLK XDIP XDIN
Encoder
Insertion
Jitter Attenuator Buffer
Pulse Shaper
Line Driver
V1.2
F0160
Figure
Transmit Clocking Details
dB/decade Jitter Gain
GR-499-CORE GR-253-CORE
acceptable range
1000 Jitter Frequency
10000 100000 15000
F0141
Figure
Jitter Attenuation Characteristic
Delta Sheet
2000-07
3452 PUCCINIV1.2
PRELIMINARY Descriptions
Descriptions
Diagram
P-MQFP-44-2 (Top View)
RDON/BPV
REFCLK
RCLK
RDOP
XCLK
XDIN
XDIP
VDDXP XTAL2 XTAL1 VSSXP JATT VDDX
3452 PUCCINI
VDDRP VSSRP
XAIS
LCODE
DR/SR
DS3/E3
VSSX
VSSR
DS3/STS1
VDDR
V1.2 F0216
Figure Table
Configuration P-MQFP-44-2 Modified Definitions Symbol Function Input Output Supply Connection external pullable quartz. DS3: 14.912 STS-1: 17.280 11.456 Jitter attenuation enable signal
XTAL1 XTAL2
JATT
Delta Sheet
2000-07
3452 PUCCINIV1.2
PRELIMINARY Application Example
Application Example
following picture shows typical appliction circuit (excluding surge protection).
Jitter Attenuation Reference
XTAL1/2 VDDRP/VSSRP
VDDR/VSSR
DS3/STS-1/E3 Receive Line Interface
RL1/2
Receive Path
RDOP RDON RCLK
DS3/STS-1/E3 Framer/Mapper Receive Interface
PUCCINIV1.2
DS3/STS-1/E3 Transmit Line Interface XDIP XDIN XCLK DS3/STS-1/E3 Framer/Mapper Transmit Interface
XL1/2
Transmit Path
VDDXP/VSSXP
VDDX/VSSX VDD/VSS REFCLK TEST
V1.2 Reference Clock N.C. Control Interface F0218
Figure
Delta Sheet
Application Circuit
2000-07

Edition 2000-07 Published Infineon Technologies St.-Martin-Strasse D-8

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