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L64381 4-Port Ethernet Controller Device Technical Manual
This document preliminary. such, contains data derived from functional simulations performance estimates. Logic verified either functional descriptions, electrical mechanical specifications using production parts. Document DB14-000002-01, Second Edition (August 1996) This document describes revision Logic Corporation's L64381 4-Port Ethernet Controller (Quad CASCADE®) Device will remain official reference source revisions/releases this product until rescinded update. receive product literature, call 1.800.574.4286 (U.S. Canada); +32.11.300.531 (Europe); 408.433.7700 (outside U.S., Canada, Europe) Department JDS; visit http://www.lsilogic.com. Logic Corporation reserves right make changes products herein time without notice. Logic does assume responsibility liability arising application product described herein, except expressly agreed writing Logic; does purchase product from Logic convey license under patent rights, copyrights, trademark rights, other intellectual property rights Logic third parties. Copyright 1995, 1996 Logic Corporation. rights reserved. TRADEMARK ACKNOWLEDGMENT Logic logo design CASCADE registered trademarks Logic Corporation. other brand product names trademarks their respective companies.
Preface
This book primary reference technical manual L64381 4-Port Ethernet Controller (Quad CASCADE) Device. contains complete functional description L64381 includes complete physical electrical specifications L64381.
Audience
This document assumes that have some familiarity with networking, microprocessors, related support devices. people benefit from this book are:
Engineers managers evaluating L64381 possible
networking system
Engineers designing L64381 into system
Organization This document following chapters appendixes:
Chapter Introduction, describes general characteristics
capabilities L64381 product.
Chapter Registers, defines on-chip registers. Chapter Signal Descriptions, describes input, output,
bidirectional signals L64381 chip.
Chapter L64381 Operation, provides detailed description
functional blocks interfaces within L64381 chip.
Chapter Statistics Counters, lists purpose contents
32-bit Statistics Counters.
Chapter Instruction Set, defines L64381 instruction
provides each instruction's valid modes.
Chapter Specifications, provides specifications
packaging information L64381 chip.
Preface
Appendix Customer Feedback, includes form that
your comments about this document.
Related Publications
Compacted Scalable Dedicated Ethernet (CASCADE) Core Technical Manual, Order C14015
Conventions Used This Manual
first time word phrase defined this manual, italicized. following signal naming conventions used throughout this manual:
level-significant signal that true valid when signal
always overbar over name. over name.
edge-significant signal that initiates actions HIGH-to-LOW
transition always overbar word assert means drive signal true active. word deassert means drive signal false inactive. Hexadecimal numbers indicated prefix "0x" before number-for example, 0x32CF. Binary numbers indicated subscripted following number-for example, 0011.0010.1100.11112. word 32-bits long. halfword 16-bits long. byte 8-bits long.
Preface
Contents
Chapter
Introduction Overview Features 1.2.1 Ethernet Core 1.2.2 Internal Architecture 1.2.3 Interface 1.2.4 Processor Interface 1.2.5 Programmable Features Registers Register Addresses Configuration Registers 2.2.1 Configuration Register 2.2.2 Configuration Register 2.2.3 Packet Configuration Register Ethernet Address Registers Error Registers 2.4.1 Error Register 2.4.2 Error Register Error Mask Registers 2.5.1 Error Mask Register 2.5.2 Error Mask Register Statistics Counters Registers 2.6.1 Statistics Counters Address Register 2.6.2 Statistics Counters Data-In Registers 2.6.3 Statistics Counters Data-Out Registers Data FIFO Registers 2.7.1 Data FIFO Address Register 2.7.2 Data FIFO Data-In Registers
Chapter
2-10 2-11 2-11 2-12 2-13 2-13 2-14 2-15 2-15 2-16 2-16 2-17 2-17 2-19
Contents
2.10 2.11 2.12 2.13 Chapter
2.7.3 Data FIFO Data-Out Registers Receive FIFO Head Pointer Registers Receive FIFO Tail Pointer Registers Transmit FIFO Head Pointer Registers Transmit FIFO Tail Pointer Registers Receive Counters Transmit Counters
2-19 2-20 2-20 2-21 2-22 2-22 2-23
Signal Descriptions Network Interface Signals Interface Signals Processor Interface Signals Status Signals Clock Signals Test Signals Miscellaneous Signals L64381 Operation Ethernet Cores On-chip FIFOs 4.2.1 Transmit FIFO 4.2.2 Receive FIFO Interface 4.3.1 Bus-Out State Machine 4.3.2 Bus-In State Machine Processor Interface 4.4.1 Reading L64381 Internal Registers 4.4.2 Writing L64381 Internal Registers 4.4.3 Burst Mode Reads Statistics Counters Connections Twisted-Pair Interface Interface JTAG Initialization Statistics Counters
3-12 3-13 3-15 3-15 3-16
Chapter
4-10 4-15 4-15 4-16 4-17 4-17 4-18 4-19 4-19
Chapter
Contents
Chapter
Instruction Instruction Summary Accessing Data FIFO 6.2.1 Reading Data FIFO 6.2.2 Writing Data FIFO Accessing Statistics Counters 6.3.1 Reading Statistics Counters 6.3.2 Writing Statistics Counters 6.3.3 Burst Read Statistics Counters Specifications Timing Electrical Requirements Special Connections Packaging 7.4.1 Ordering Information 7.4.2 Package Information Customer Feedback 2.10 2.11 2.12 2.13 2.14 2.15 L64381 Block Diagram Configuration Register Configuration Register Big-Endian Addressing Little-Endian Addressing Packet Configuration Register Error Register Error Register Error Mask Register Error Mask Register Statistics Counters Address Register Statistics Counters Data In-Register Statistics Counters Data In-Register Statistics Counters Data Register Statistics Counters Data Register Data FIFO Address Register
Chapter
7-12 7-12 7-13 7-13
Appendix Figures
2-11 2-12 2-13 2-14 2-15 2-16 2-16 2-17 2-17 2-18
Contents
2.16 2.17 2.18 2.19 2.20 2.21 2.22 2.23 2.24 2.25 2.26 2.27 2.28 2.29 2.30 2.31 4.10 4.11 4.12 4.13 4.14 4.15 4.16 4.17
Data FIFO Data Register Data FIFO Data Register Data FIFO Data Register Data FIFO Data Register Receive FIFO Head Pointer Register Receive FIFO Head Pointer Register Receive FIFO Tail Pointer Register Receive FIFO Tail Pointer Register Transmit FIFO Head Pointer Register Transmit FIFO Head Pointer Register Transmit FIFO Tail Pointer Register Transmit FIFO Tail Pointer Register Receive Counter Receive Counter Transmit Counter Transmit Counter L64381 Logic Diagram L64381 Block Diagram Data FIFO Block Diagram STROBE PKT_AVAIL Timing Relationship Reading Packets from L64381 Read Packet with Middle Transfer Read Data with ABORT_IN Assertion STROBE BUF_AVAIL Timing Writing Packets L64381 with Port Operation Aborted Writing Packets L64381 with ABORT_OUT Asserted Read-then-Write Operations Write-then-Read Operations Processor Read Timing Processor Write Timing Burst Read Access Timing L64381 Loop Filter PLLVDD Decoupling Typical L64381 Twisted-Pair Application Typical L64381 Application Test Load Waveform Standard Outputs Test Load Waveform 3-State Outputs
2-19 2-19 2-19 2-19 2-20 2-20 2-21 2-21 2-21 2-21 2-22 2-22 2-23 2-23 2-23 2-23 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-16 4-17 4-18 4-18 4-19
viii
Contents
7.10 7.11 Tables
Interface Read Write Timing Abort Operation Timing Reset Timing Processor Interface Timing Interrupt Timing Status Timing Clock Timing 208-Pin PQFP Pinout 208-Pin PQFP Mechanical Drawing L64381 Register Summary Descriptions Statistics Counters L64381 Instructions Timing Values Absolute Maximum Ratings Recommended Operating Conditions Capacitance Characteristics Description Summary VDD/VSS Numbers Port L64381 Ordering Information Alphabetical List 208-Pin PQFP
7-15 7-16 7-10 7-11 7-12 7-13 7-14
Contents
Contents
Chapter Introduction
This document describes L64381 (Quad CASCADE) 4-Port Ethernet Controller device, highly integrated CMOS solution Local Area Network (LAN) applications. L64381 derived from 10-Mbps Ethernet Controller core. This multiport solution allows system designers build cost-effective switched Ethernet router products. L64381 consists four ports, each with separate 128-byte Transmit Receive FIFOs. device architecture includes high-performance 1-Gbps interface designed fast packet transfers, processor interface control status checking purposes. L64381 programmed full-duplex half-duplex operation, individual, promiscuous addressing modes, supports both twisted-pair (Attachment Unit Interface) interfaces. L64381 IEEE 802.3 signal conformance interoperability tests. Chapter provides overview L64381. contains sections:
Section 1.1, "Overview" Section 1.2, "Key Features"
Overview Figure shows block diagram L64381 device. four Ethernet controllers fully independent. Each L64381 port (Medium Access Control), Manchester Encoder/Decoder, twistedpair/AUI transceivers. device fully synchronous. operates 16-MHz 33-MHz host clock 20-MHz network clock. 128-byte FIFOs configurable optimizing latency throughput. Each port Statistical Counters, which provide on-chip maintenance. These counters meet statistics requirements Simple Network Management Protocol (SNMP).
Figure L64381 Block Diagram
Processor Interface
Statistics Counters
Configuration Control Receive FIFO
Port
Ethernet Core
Transmit FIFO
Statistics Counters Receive FIFO Port Ethernet Core Transmit FIFO Interface
Network Interface
Statistics Counters Receive FIFO Port Ethernet Core Transmit FIFO
Statistics Counters Receive FIFO Port Ethernet Core Transmit FIFO
chip provides several programmable configurations allow customer product differentiation, such source address insertion, insertion, immediate retransmission collision, transfer size, transmit buffer threshold size. L64381 configured using 6-bit Address 16-bit PData bus. internal registers read, most also written. Special test modes provided that make functional system testing simpler.
Introduction
Interface designed allow efficient transfers packet data from L64381. Four bytes data transferred cycle with burst size words. dead cycle required between each burst cycle. scan interface allows board-level testing using JTAG (IEEE 1149.1) standard. Logic fabricates L64381 CMOS cell-based process. L64381 available 208-pin Plastic Quad Flat Pack (PQFP) package.
Features 1.2.1 Ethernet Core
This section lists general features L64381.
Ethernet core features categorized into four subsections: MAC, Encoder/Decoder, twisted-pair transceivers, transceivers. 1.2.1.1 Features
IEEE 802.3 Ethernet Standards support Complete CSMA/CD Medium Access Control functions Twisted-pair, full-duplex mode Mbit/s throughput Individual address filter (individual promiscuous addressing
modes)
Internal generator checker
1.2.1.2 Encoder/Decoder
Mbit/s Manchester encoding/decoding Digital with synchronous data recovery Manchester data decoded with 18-ns jitter with fast-lock time Elasticity:
Maximum time: Maximum clock error 1518 byte frame: 0.05% Maximum clock error 4500 byte frame: 0.016%
Features
1.2.1.3 Twisted-Pair (10BASE-T) Transceivers
Integrated transceiver interface Collision detect Link integrity test Loopback test capabilities Autopolarity detection correction
1.2.1.4 Attachment Unit Interface (AUI) Transceivers
Signal Quality Error test (Heartbeat) Smart receive squelch receive data Smart squelch collision detection 10BASE-2, 10BASE-5, 10BASE-F interface
1.2.2 Internal Architecture This subsection highlights features internal architecture:
Independent 128-Byte Transmit Receive FIFOs Ethernet port Autotransmit collision feature. First transmit bytes buffered
chip allow retransmission collision without requiring transactions first bytes packet
Ability generate suppress Next packet transmit queued while previous packet still being
transmitted, thus providing multiple back-to-back packet transmissions without wasted bandwidth
Statistics Ethernet core maintained chip registers fully observable, most controllable
1.2.3 Interface This subsection summarizes features L64381 interface:
32-bit data width ports devices) Mbit/s connected based
approximately 1-Gbit bandwidth
Introduction
PKT_AVAIL signal informs system when Receive FIFO more
data than programmable transfer size, that End-of-Packet (EOP) signal present Receive FIFO, that FIFO data read system
BUF_AVAIL signal informs system when Transmit FIFO more
space than programmable transfer size, that system write transmit data FIFO
Four BYTE_VALID signals specify which bytes valid
current data word (significant only first last transfer packet when either start-of-packet signal end-ofpacket signal asserted)
signals delimit start packet packet,
respectively
PORT_BUSY signal Ethernet core when operating full-duplex
half-duplex mode 1.2.4 Processor Interface This subsection highlights features L64381 processor interface:
6-bit Address 16-bit PData buses Slave mode device Chip Control Status information read from Control
Status Registers
Burst mode reads Ethernet Statistics Interrupt signal inform processor error condition occurs
1.2.5 Programmable Features L64381 several programmable features:
Individual twisted-pair assignment port Automatic source address insertion Automatic insertion transfer size configurable words Addressing modes (individual, promiscuous, multicast) Auto padding packets less than bytes length Programmable little-endian big-endian addressing modes
Features
Introduction
Chapter Registers
L64381 number on-chip registers that configure control addition, FIFO pointers, FIFO Address Data registers, Statistics Counters decoded register addresses, that Processor Interface read write their values. This chapter describes function registers with their associated fields. This chapter following sections:
Section 2.1, "Register Addresses" Section 2.2, "Configuration Registers" Section 2.3, "Ethernet Address Registers" Section 2.4, "Error Registers" Section 2.5, "Error Mask Registers" Section 2.6, "Statistics Counters Registers" Section 2.7, "Data FIFO Registers" Section 2.8, "Receive FIFO Head Pointer Registers" Section 2.9, "Receive FIFO Tail Pointer Registers" Section 2.10, "Transmit FIFO Head Pointer Registers" Section 2.11, "Transmit FIFO Tail Pointer Registers" Section 2.12, "Receive Counters" Section 2.13, "Transmit Counters"
Register Addresses
Table L64381 Register Summary
Table summarizes addresses L64381 registers. ADRS[5:0] inputs determine which register being accessed.
ADRS[5:0] 000010 000011 000100 000101 000110 000111 001000 001010 001001 001011 010000 010001 010010 010011 010110 011000 011001 011010 011011 011110 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011
Accessibility Register R/W1 R/O2 Configuration Register Configuration Register Ethernet Address Register Ethernet Address Register Ethernet Address Register Packet Configuration Register Error Register Error Register Error Mask Register Error Mask Register Statistics Counters Data Register Statistics Counters Data Register Statistics Counters Data Register Statistics Counters Data Register Statistics Counters Address Register Data FIFO Data Register Data FIFO Data Register Data FIFO Data Register Data FIFO Data Register Data FIFO Address Register Receive FIFO Head Pointer Register Receive FIFO Head Pointer Register Receive FIFO Tail Pointer Register Receive FIFO Tail Pointer Register Transmit FIFO Head Pointer Register Transmit FIFO Head Pointer Register Transmit FIFO Tail Pointer Register Transmit FIFO Tail Pointer Register Receive Counter Receive Counter Transmit Counter Transmit Counter
Registers
Read/Write. Read Only.
Configuration Registers
There three configuration registers: Configuration Register Configuration Register Packet Configuration Register. These registers initialize overall L64381. following subsections, letter used imply four ports. assignments made ascending order-Port assigned lowest bit, Port assigned highest bit. Figure shows assignments Configuration Register This 16-bit register read/write.
2.2.1 Configuration Register
Figure Configuration Register
PRTID PRTMDE DUPLEX
PRTID
Reserved These bits reserved read zeroes.
[15:14]
PORT [13:8] These bits assign unique, sequential numbers ports. This field useful applications with multiple L64381 devices. PORT assigned eight-bit number, which PORT field appended with 002, PORT assigned value {PORT 012}, PORT assigned number {PORT 102}, PORT assigned number {PORT 112}. SOPCFG must this field meaningful. Refer description SOPCFG Section 2.2.2, "Configuration Register
PRTMDE
PORT Mode [7:4] These four bits configure corresponding port receive packets that sent Ethernet. (Bit corresponds Port corresponds Port etc.) these bits reset zero (Port Mode OFF), then corresponding port receives only packets that exactly match Ethernet address specified
Configuration Registers
Ethernet Address Registers. broadcast multicast packets accepted mode. these bits (Port Mode ON), then corresponding port receives packets that sent Ethernet, regardless address specified Ethernet Address Registers. ports also receive broadcast multicast packets mode. DUPLEX PORT Duplex Mode [3:0] These four bits configure corresponding Ethernet ports half-duplex full-duplex mode Half Duplex; Full Duplex). configures Port configures Port etc.
2.2.2 Configuration Register
Figure shows assignments Configuration Register This 16-bit register read/write. modify these bits, processor should perform read-modify-write operation order retain values non-affected bits this register.
Figure Configuration Register
DIAG LOOPBK THRESH BURST
SOPCFG ENDN
Write Enable Port Setting this enables writing four bits ENPORTx field Packet Configuration Register. ENPORTx field enables/disables four ports. Diagnostic Modes [14:13] These bits determine type mode which L64381 operates.
DIAG
Registers
DIAG Mode Normal Register
Description L64381 normal operating mode (active) described this document. this mode, L64381 halted. This mode used reading writing values into FIFO Pointer Registers, Data FIFO, Statistics Counters. This mode provided testing Transmit Receive FIFO Pointer registers Data FIFO Counters. normal mode, possible processor directly write data into FIFO Pointer registers Data FIFO. This mode puts FIFO address register Statistics Counter address counter into increment mode. initial value loaded into address register, then address increments itself every read write operation FIFO counter. This mode useful testing Data FIFO Statistics Counters, well initializing them.
FIFO Counter Test
LOOPBK
Port Loopback Mode [12:9] When these bits one, corresponding port operates local loopback mode. this mode, transmitter output back into receiver input, thus allowing local testing without requiring external loopback connector. following table shows relationship between LOOPBK register bits their corresponding ports. This mode applies full-duplex configuration only.
LOOPBK Port
Configuration Registers
THRESH
Transmit Threshold [8:7] These bits determine number words that need stored Transmit FIFO before initiates packet transmit Ethernet.
Stored Words words words words words
Transfer Size [6:5] These bits specify maximum number words that L64381 transfers across Interface whenever L64381 asserts either PKT_AVAIL BUF_AVAIL response assertion STROBE.
Transfer Size words words words words
Note:
that externally control length transfer, system could deassert either READ_OUT_PKT WRITE_IN_PKT before amount words transferred across Interface. However, READ_OUT_PKT WRITE_IN_PKT should kept asserted after amount words been transferred, because L64381 does guarantee response. signal asserted middle transfer, L64381 drives idle data (zeros) until detects deassertion READ_OUT_PKT. L64381 detects while WRITE_IN_PKT asserted, then stops writing data into Transmit FIFO after that cycle.
Registers
SOPCFG
Start Packet Configuration When this one, L64381 assumes that first word packet that host writes into Transmit FIFO contains Packet Configuration Information. this case, least-significant four bits Packet Configuration Register ignored replaced with four least-significant bits from first word packet. Therefore, each port configured perpacket basis. addition, when L64381 receives packets from Ethernet, appends extra word containing PORT number front packet that host knows which port packet coming from, insert Packet Configuration Information into this space later. (The PORT number placed least-significant byte first word.) SOPCFG set, then Packet Configuration Information bits Packet Configuration Register used Packet Configuration Information packets that transmitted L64381. this case, PORT number used. Refer Figure timing.
ENDN
Endian Addressing When this zero, L64381 addressing mode Processor Interface endian (see Figure 2.3). When this one, addressing mode little endian (see Figure 2.4). Because L64381 byte addressable, this only affects Burst Read instruction.
Figure Big-Endian Addressing
PDATA15 Most-Significant bits
PDATA0 first read
Least-Significant bits
second read
Figure Little-Endian Addressing
PDATA15 Least-Significant bits
PDATA0 first read
Most-Significant bits
second read
Configuration Registers
When accessing statistics from Statistics Counters big-endian burst modes, most-significant bytes counter placed PDATA before least-significant bytes. little-endian burst modes, least-significant bytes placed PDATA before most-significant bytes. ENDN setting affects only Processor Interface effect little-endian Interface. During Interface write transaction, L64381 looks first valid byte from either DATA[7:0], DATA[15:8], DATA[23:16] DATA[31:24]. This choice depends value BYTE_VALID[3:0]. L64381 then sends valid byte network. first example below, DATA[7:0] goes network first, then DATA[15:8], finally DATA[23:16]. second example only valid bytes, DATA[23:16] passed network first, DATA[31:24] follows.
BYTE_VALID[3:0] BIts[31:24] Bits [23:16] Bits [15:8] Bits [7:0] 10002 Invalid Byte Third Byte Second Byte First Byte 00112 Second Byte First Byte Invalid Byte Invalid Byte
BURST
Burst Mode Size [2:1] These bits define number burst transfers that L64381 perform Processor Interface response burst mode instruction. Burst Mode allows processor quickly read statistics collected L64381 Ethernet port without having execute individual read instructions statistic.
BURST[2:1] Transfer Size 16-bit transfers 16-bit transfers 16-bit transfers 16-bit transfers
Note
These bits refer only Processor Interface; Transfer Size (BUS) bits define transfer size Interface.
Registers
Write Enable Ethernet Address Setting this enables writing six-byte Ethernet address ports. user should reset this soon address been assigned order reduce chances accidental overwrite address.
2.2.3 Packet Configuration Register
Figure shows Packet Configuration Register. This 16-bit read/write register contains programming information packets control bits that enable disable ports. information stored least-significant four bits this register applied four ports L64381. override information these four bits with packet specific information, SOPCFG Configuration Register one. most-significant four bits this register enable individual ports Enabled). disabled state, ports will respond internal external stimuli.
Figure Packet Configuration Register
ENPORTx LFORCEPPORTx LCORPPORTx AUTO
ENPORTx
Enable Port [15:12] When these bits set, associated port enabled functions specified Configuration Registers When these bits reset, associated port reset (disabled), associated port's outputs negated, Head Tail Pointers counters reset zeros. This field only written Configuration Register one.
LFORCEPPORTx Link Force Port [11:8] When these bits set, associated port allows transmit even link integrity fails. Refer Chapter "Signal Descriptions," Compacted Scalable Dedicated Ethernet (CASCADE) Core Technical Manual description LFORCEP signal.
Configuration Registers
LCORPPORTx Link Correct Polarity Port [7:4] When these bits set, associated port corrects inverted polarity twisted-pair interface, inverted polarity condition exists that port. Refer Chapter "Signal Descriptions," Compacted Scalable Dedicated Ethernet (CASCADE) Core Technical Manual description LCORPP signal. Store First Bytes When this set, each port's Transmit FIFO stores first bytes packet until bytes have been transmitted without collisions Network Interface. Once first bytes transmitted, FIFO releases locations that were used store these bytes, thereby allowing data fetched into FIFO. This feature allows port retransmit packet without requiring extra transfers Interface. This valid only when SOPCFG zero. Automatic Packet Padding When this set, ports automatically runt packet length bytes. This feature allows better utilization Transmit FIFO space, because runt packets need pre-padded minimum Ethernet packet size. This effect only when AI_FCS_IN asserted SOPCFG zero, else L64381 ignores this bit. Reserved This reserved reads zero.
AUTO
Auto Insert Source Address When this set, ports automatically insert address stored Ethernet Address Registers into source address field Ethernet packet. This valid only when SOPCFG zero.
Ethernet Address Registers
three Ethernet Address Registers through contain 48-bit Ethernet address assigned L64381. Ethernet Address Register contains least-significant bytes Ethernet port address, Ethernet Register contains most-significant bytes Ethernet address. These registers written only when Configuration Register one.
2-10
Registers
Note:
user should immediately reset write enable bits after address been written. This action reduces likelihood inadvertent change address software bug. When Port Mode ports accept packets received Ethernet regardless value these registers. When Port Mode OFF, only those packets that exactly match address these registers accepted.
Error Registers
L64381 Error Registers, Error Register Error Register fields within these registers indicate status errors L64381 detect. Upon detection error, L64381 asserts INTERRUPT output. clear interrupt, take one's complement Error Register that caused interrupt write value back into that register. Figure shows Error Register Error Register 16-bit read-write register. Upon power-up when RESET asserted, bits this register cleared zeros (all interrupts disabled).
2.4.1 Error Register
Figure Error Register
PINT BINT LATEC RCFIFO TRFIFO
PINT
Reserved These bits reserved read zeros.
Processor Interface Error this indicates that Processor Interface error occurred (for example, write unwritable location). Interface Error this indicates that Interface error occurred. This error occurs when WRITE_IN_PKT READ_OUT_PKT both asserted same time.
BINT
Error Registers
2-11
LATEC
PORT Late Collision Error [11:8] bits this field indicates that Late Collision error occurred specific port. Each this field corresponds four ports. least-significant corresponds Port mostsignificant corresponds Port PORT Receive FIFO Overrun Error [7:4] bits this field indicates that Receive FIFO Overrun error occurred specific port. Each this field corresponds four ports. least-significant corresponds Port most-significant corresponds Port PORT Transmit FIFO Underrun Error [3:0] bits this field indicates that Transmit FIFO Underrun error occurred specific port. Each this field corresponds four ports. least-significant corresponds Port most-significant corresponds Port
RCFIFO
TRFIFO
2.4.2 Error Register
Figure shows Error Register Error Register 16-bit read/write register. Upon power-up when RESET asserted, bits this register will zeros (all interrupts disabled). Each active field Error Register contains four bits. Each corresponds four ports. least-significant corresponds Port mostsignificant corresponds Port
Figure Error Register
TSQE EXCCOL LINKFL
TSQE
Reserved These bits reserved read zeros.
[15:12]
Transmit Error Port [11:8] these bits indicates that error occurred specific port.
2-12
Registers
EXCCOL
Excessive Collision Port Error [7:4] bits this field indicates that frame could transmitted after attempts specific port. L64381 aborts transmission with further retries. Link Failure Port Error [3:0] bits this field indicates that Link Failure error (either data link integrity pulses were received occurred specific port.
LINKFL
Error Mask Registers
Error Mask Registers contain mask bits error fields corresponding Error Registers. When Mask Register, corresponding error masked L64381 does assert INTERRUPT signal that error condition. Figure shows Error Mask Register This register contains mask bits error fields Error Register Upon power-up when RESET asserted, bits this register zeros.
2.5.1 Error Mask Register
Figure Error Mask Register
PIN13
BIN
LATECM
RCFIFOM
TRFIFOM
Enable Interrupts When this one, L64381 generates interrupt whenever Error Register written one, provided that bit's corresponding mask Error Mask Register. Processor Interface Error Mask this masks Processor Interface error. Reserved This reserved reads zero. Interface Error Mask this masks Interface error.
PINR BIN
Error Mask Registers
2-13
LATECM
PORT Late Collision Error Mask [11:8] bits this field masks corresponding port's late collision error. Each this field corresponds four ports. least-significant corresponds Port most-significant corresponds Port PORT Receive FIFO Overrun Error Mask [7:4] bits this field masks corresponding port's Receive FIFO overrun error. Each this field corresponds four ports. least-significant corresponds Port mostsignificant corresponds Port PORT Transmit FIFO Underrun Error Mask [3:0] bits this field masks corresponding port's Transmit FIFO underrun error. Each this field corresponds four ports. least-significant corresponds Port mostsignificant corresponds Port
RCFIFOM
TRFIFOM
2.5.2 Error Mask Register
Figure Error Mask Register
Figure shows Error Mask Register This register contains mask bits error fields Error Register Upon power-up when RESET asserted, bits this register cleared zeros.
TSQEM
EXCCOLM
LINKFLM
TSQEM
Reserved These bits reserved read zeros.
[15:12]
Transmit Error Port Mask [11:8] bits this field masks corresponding port's transmit error. Each this field corresponds four ports. leastsignificant corresponds Port most-significant corresponds Port
2-14
Registers
EXCCOLM
Excessive Collision Port Error Mask [7:4] bits this field masks corresponding port's excessive collision error. Each this field corresponds four ports. leastsignificant corresponds Port most-significant corresponds Port Link Failure Port Error Mask [3:0] bits this field masks corresponding port's link failure error. Each this field corresponds four ports. least-significant corresponds Port most-significant corresponds Port
LINKFLM
Statistics Counters Registers 2.6.1 Statistics Counters Address Register
This section describes five registers that used access Statistics Counters: Statistics Counters Address Register, Statistics Counters Data-In Registers, Statistics Counters Data-Out Registers. Figure 2.10 shows Statistics Counters Address Register. This read/write register stores pointer Statistics Counters. This pointer used either read counter value write value specified counter. When burst read instruction performed, L64381 increments counter value automatically, port number remains unaffected. Similarly autoincrement diagnostics mode, L64381 does increment port number.
Figure 2.10 Statistics Counters Address Register
STAT PORT
STAT
Reserved These bits reserved read zeros.
[15:7]
Statistics Counter [6:2] These bits determine which counter read/write access pertains.
Statistics Counters Registers
2-15
PORT
Port Number [1:0] These bits select port number selected counter STAT field.
2.6.2 Statistics Counters Data-In Registers
Figures 2.11 2.12 show Statistics Counters Data-In Registers. values these 16-bit registers written into Statistics Counters. Note: write statistical counter operation occur mode. Because L64381 internally uses big-endian addressing scheme, lower bits 32-bit data written Statistics Counters Data-In Register upper bits written Statistics Counters Data-In Register
Figure 2.11 Statistics Counters Data In-Register
Statistics Counters Data [15:0]
Figure 2.12 Statistics Counters Data In-Register
Statistics Counters Data [31:16]
2.6.3 Statistics Counters Data-Out Registers
Figures 2.13 2.14 show Statistics Counters Data-Out Registers. Values read from Statistics Counters placed these 16-bit, read-only registers. Because L64381 internally uses big-endian addressing scheme, lower bits 32-bit data read Statistics Counters Data-Out Register upper bits read Statistics Counters Data-Out Register
2-16
Registers
Figure 2.13 Statistics Counters Data Register
Statistics Counters Data [15:0]
Figure 2.14 Statistics Counters Data Register
Statistics Counters Data [31:16]
Data FIFO Registers
This section describes five registers that used access Data FIFO: Data FIFO Address Register, Data FIFO Data Registers, Data FIFO Data Registers. Transmit Receive FIFOs contain bytes array. Refer Section 4.2, "On-chip FIFOs," more information configuration FIFOs. Figure 2.15 shows Data FIFO Address Register. This 16-bit register contains address either Data FIFO read Data FIFO write. Note that transfers between Data FIFO Address Register Data FIFO occur only Diagnostic Modes Diagnostic Modes entire 36-bit wide FIFO tested. write 36-bit location Data FIFO, lower bits placed Data FIFO Data Registers. upper four bits written Data FIFO from WRAM field Data FIFO Address Register. read back Data FIFO location, lower bits read into Data FIFO Data Registers. upper four bits placed RRAM field Data FIFO Address Register.
2.7.1 Data FIFO Address Register
Data FIFO Registers
2-17
Figure 2.15 Data FIFO Address Register
RRAM WRAM FIFOS PORTNO WORDADDR
RRAM
Read Data FIFO [15:12] During Data FIFO read, L64381 writes value four most-significant bits selected Data FIFO location into these four bits. This value userencoded value BYTE_VALID[3:0], SOP, EOP, AI_FCS_IN. addition this field allows reading bits selected Data FIFO without requiring additional register decode. Write Data FIFO [11:8] These bits contain value written into upper four bits words selected Data FIFO. When interface transaction occurs, this value user-encoded value BYTE_VALID[3:0], SOP, EOP, AI_FCS_IN. addition this field allows writing bits Data FIFO without requiring additional register decode. FIFO Select This selects either Transmit FIFO (FIFOS Receive FIFO (FIFOS read write operation. Port Number [6:5] This field selects port number (3:0) read write operation.
WRAM
FIFOS
PORTNO
WORDADDR Word Address [4:0] This field selects words within 128-byte FIFO. When processor writes Data FIFO Address Register, bits register written, allowing testing register. processor executes Read Data FIFO instruction, highest four bits overwritten with encoded value field Data FIFO. Therefore, when testing Data FIFO Address Register, user should execute Read Data FIFO Address Register instruction before executing Read Data FIFO instruction.
2-18
Registers
2.7.2 Data FIFO Data-In Registers
Figures 2.16 2.17 show Data FIFO Data-In Registers. Values stored these registers written into Data FIFO Diagnostic Modes (refer DIAG field Configuration Register Because L64381 uses big-endian addressing scheme, places lower bits 32-bit data Data FIFO Data-In Register places upper bits Data FIFO Data-In Register
Figure 2.16 Data FIFO Data Register
Data FIFO Data [15:0]
Figure 2.17 Data FIFO Data Register
Data FIFO Data [31:16]
2.7.3 Data FIFO Data-Out Registers
Figures 2.18 2.19 show Data FIFO Data-Out Registers. Values read from Data FIFO written into these read-only registers. Because L64381 uses big-endian addressing scheme, lower bits 32-bit data read Data FIFO Data-Out Register upper bits read Data FIFO Data-Out Register
Figure 2.18 Data FIFO Data Register
Data FIFO Data [15:0]
Figure 2.19 Data FIFO Data Register
Data FIFO Data [31:16]
Data FIFO Registers
2-19
Receive FIFO Head Pointer Registers
Figures 2.20 2.21 show Receive FIFO Head Pointer Registers. These registers used read write Receive FIFO head pointers. head pointers point first location Receive FIFO with valid data read. Register contains head pointers Ports register contains head pointers Ports FIFO pointers each five bits length. most-significant bits both bytes (bits [15:13] [7:5]) ignored write instruction, read these registers returns zero bits [15:13] [7:5].
Figure 2.20 Receive FIFO Head Pointer Register
Reserved RHEAD1 Reserved RHEAD0
Figure 2.21 Receive FIFO Head Pointer Register
Reserved RHEAD3 Reserved RHEAD2
Receive FIFO Tail Pointer Registers
Figures 2.22 2.23 show Receive FIFO Tail Pointer Registers. These registers used read write Receive FIFO tail pointers. tail pointers point first empty location Receive FIFO writing data. Register contains tail pointers Ports register contains tail pointers Ports FIFO pointers each five bits length. most-significant bits both bytes (bits [15:13] [7:5]) ignored write instruction, read these registers returns zero bits [15:13] [7:5].
2-20
Registers
Figure 2.22 Receive FIFO Tail Pointer Register
Reserved RTAIL1 Reserved RTAIL0
Figure 2.23 Receive FIFO Tail Pointer Register
Reserved RTAIL3 Reserved RTAIL2
2.10 Transmit FIFO Head Pointer Registers
Figures 2.24 2.25 show Transmit FIFO Head Pointer Registers. These registers used read write Transmit FIFO head pointers. head pointers point first location Transmit FIFO with valid data read. Register contains head pointers Ports Register contains head pointers Ports FIFO pointers each five bits length. most-significant bits both bytes (bits [15:13] [7:5]) ignored write instruction, read these registers returns zero bits [15:13] [7:5].
Figure 2.24 Transmit FIFO Head Pointer Register
Reserved THEAD1 Reserved THEAD0
Figure 2.25 Transmit FIFO Head Pointer Register
Reserved THEAD3 Reserved THEAD2
Transmit FIFO Head Pointer Registers
2-21
2.11 Transmit FIFO Tail Pointer Registers
Figures 2.26 2.27 show Transmit FIFO Tail Pointer Registers. These registers used read write Transmit FIFO tail pointers. tail pointers point first empty location Transmit FIFO writing data. Register contains tail pointers Ports register contains tail pointers Ports FIFO pointers each five bits length. most-significant bits both bytes (bits [15:13] [7:5]) ignored write instruction, read these registers returns zero bits [15:13] [7:5].
Figure 2.26 Transmit FIFO Tail Pointer Register
Reserved TTAIL1 Reserved TTAIL0
Figure 2.27 Transmit FIFO Tail Pointer Register
Reserved TTAIL3 Reserved TTAIL2
2.12 Receive Counters
Figures 2.28 2.29 show Receive Counters. These counters count number packets (EOPs) that Receive FIFO. port increments counter when receives packet, decrements counter when Interface asserts bus. counter value greater than equal one, there least Receive FIFO. Even number bytes left FIFO less than programmed transfer size (BUS field), L64381 still asserts PKT_AVAIL allow host drain Receive FIFO. This scheme permits better Receive FIFO, because padding data needed align with Transfer Size, hence FIFO space wasted with data. Counter contains counter values Ports Counter contains counter values Ports
2-22
Registers
Figure 2.28 Receive Counter
Reserved RCOUNT1 Reserved RCOUNT0
Figure 2.29 Receive Counter
Reserved RCOUNT3 Reserved RCOUNT2
2.13 Transmit Counters
Figures 2.30 2.31 show Transmit Counters. These counters count number EOPs that present Transmit FIFO. port increments counter when Interface receives packet from (EOP asserted), decrements counter when packet sent port transmission. Similar Receive Counter, this scheme guarantees that packet transmitted when packet size smaller than Transmit Threshold field. Note that this transmit occur because L64381 allows automatic padding packets. This scheme permits better Transmit FIFO, since padding data needed align with Transmit Threshold, hence FIFO space wasted with data. Register contains counter values Ports Register contains counter values Ports
Figure 2.30 Transmit Counter
Reserved TCOUNT1 Reserved TCOUNT0
Figure 2.31 Transmit Counter
Reserved TCOUNT3 Reserved TCOUNT2
Transmit Counters
2-23
2-24
Registers
Chapter Signal Descriptions
This chapter describes signals that comprise L64381's bit-level interface other devices. This description intended hardware designers connecting product other components. This chapter divided into seven sections:
Section 3.1, "Network Interface Signals" Section 3.2, "Bus Interface Signals" Section 3.3, "Processor Interface Signals" Section 3.4, "Status Signals" Section 3.5, "Clock Signals" Section 3.6, "Test Signals" Section 3.7, "Miscellaneous Signals"
product's interface signals described alphabetical order mnemonic. Each signal definition contains mnemonic full signal name. mnemonics signals that active marked with overbar; others active HIGH. example, active LOW, active HIGH. descriptions that follow, verb assert means drive TRUE active. verb deassert means drive FALSE inactive. Figure shows logic diagram L64381.
Figure L64381 Logic Diagram
CLOCK ADRS[5:0] S_STROBE P_SELECT NTERRUPT TA[15:0] PREADY READ RESET COLLIN[3:0] COLLIP[3:0] CREF[3:0] DATAI[3:0] DATAN[3:0] DATAP[3:0] ATATN[3:0] ATATP[3:0] DREF[3:0] PREEN[3:0] PREEP[3:0] TP/AUI[3:0] P_TESTN TRSTN ABORT_IN ABORT_OUT AI_FCS_IN BUF_AVAIL BYTE_VALID[3:0] L64381 DATA[31:0] PKT_AVAIL PORT_BUSY PORT_NO[1:0] READ_OUT_PKT STROBE WRITE_IN_PKT PLLAGND PLLVDD PLLVSS Interface Signals CLOCK_20MHZ Clock Signals
Test Signals
COLLOUTN LBADN EDSEL[1:0] LPASSN RCVNGN TRNSMTN
Miscellaneous Signals
Signal Descriptions
Network Interface Signals
This section describes signals that comprise L64381 Network Interface. COLLIN[3:0] Negative Collision Threshold Input COLLIN[3:0] COLLIP[3:0] used detect collisions. COLLIN[3:0] valid only mode (TP/AUI signal LOW), should connected outputs negative collision threshold differential receivers. COLLIN[3:0] correspond Ports [3:0], respectively. Positive Collision Threshold Input COLLIN[3:0] COLLIP[3:0] used detect collisions. COLLIP[3:0] valid only mode (TP/AUI signal LOW), should connected outputs positive collision threshold differential receivers. COLLIP[3:0] correspond Ports [3:0], respectively. Collision Reference Input These inputs reference voltages COLLIN[3:0] COLLIP[3:0] inputs. internal circuitry follows:
COLLIP[3:0]
CREF[3:0]
COLLINP
COLLIPx
COLLINN Port L64381
COLLINx CREFx
DATAI[3:0]
Serial Data Input Each port receives serial data from network these pins. Negative Manchester-Encoded Data Output Each port transmits negative Manchester-encoded data these pins. Positive Manchester-Encoded Data Output Each port transmits positive Manchester-encoded data these pins.
DATAN[3:0]
DATAP[3:0]
Network Interface Signals
DATATN[3:0] Data Threshold Negative Input These pins, along with DATATP pins, control CASCADE squelch function link integrity pulse detection their respective port. DATATN inputs differential comparator that compares serial data received from network with negative voltage reference. DATATP[3:0] Data Threshold Positive Input These pins, along with DATATN pins, control CASCADE squelch function link integrity pulse detection their respective port. DATATP inputs compares serial data received with positive voltage reference. Data Threshold Reference Input These inputs reference voltages DATATN, DATATP, DATAI inputs. internal circuitry shown following figure:
DREF[3:0]
DATAI
DATAIx
DATATP
DATATPx
DATATN Port L64381
DATATNx DREFx
PREEN[3:0]
Negative Preemphasis Output ports transmit negative preemphasis these outputs. These outputs used twisted-pair mode only control negative preemphasis output. purpose PREEN increase amplitude higher frequencies output signal. Data preemphasis guarantees that twisted-pair mode drive signals properly Mbit/s cable meters long. These signals resistively combined: DATAP with PREEP DATAN with PREEN. technique resistively combining signals known digital preemphasis.
Signal Descriptions
PREEP[3:0]
Positive Preemphasis Output ports transmit positive preemphasis these outputs. These outputs used twisted-pair mode only control positive preemphasis output. purpose PREEP increase amplitude higher frequencies output signal. Data preemphasis guarantees that twisted-pair mode drive signals properly Mbit/s cable meters long. These signals resistively combined: DATAP with PREEP DATAN with PREEN. technique resistively combining signals known digital preemphasis. Twisted-Pair/AUI Select Input These signals determine whether specific port [3:0] mode twisted-pair mode. these signals indicates that corresponding port mode; HIGH indicates that corresponding port twisted-pair mode. following table lists principal differences between these modes.
Feature Test (heartbeat) Link Pulse Detection Link Pulse Polarity Detection Correction Link Integrity Pulses Generated Collision Pair Pins (COLLIP, COLLIN) Used Cause Transmit Carrier Loopback Error Twisted Pair Link Fail Carrier Loopback
TP/AUI[3:0]
Interface Signals
This section describes signals that comprise L64381's Interface. ABORT_IN Abort Input system uses ABORT_IN signal indicate that L64381 should ignore current transfer restore internal FIFO pointers their value before current transfer began. effect, current transfer happen. Assertion ABORT_IN does cause action network side.
Interface Signals
cases need considered when ABORT_IN asserted while either writing into Transmit FIFO reading from Receive FIFO:
While writing into Transmit FIFO, L64381
detects assertion ABORT_IN, then L64381 ignores that transfer restores internal Transmit FIFO tail pointer value contained before current transfer began.
While reading from Receive FIFO, L64381
detects assertion ABORT_IN, then stops current transfer restores Receive FIFO head pointer value contained just before transfer started. side, L64381 drives zeros data negates BYTE_VALID{3:0], SOP, signals rest transfer. ABORT_IN asserted after assertion current transfer, L64381 ignores PORT_NO inputs determine which port selected. ABORT_OUT Abort Output L64381 asserts ABORT_OUT upon detection failing condition either Transmit Receive operation. Receive operation, L64381 asserts ABORT_OUT only asserted during packet read operation. packet read operation Runt/Jabber packet, packet with FCS, internal error, receive FIFO overrun error. When failing condition occurs receiving port, L64381 reads last received byte bytes) from that port through Interface, asserts ABORT_OUT signal corrupted packet. necessary, L64381 also updates associated Statistics Counters. receive FIFO overrun error destroy portion packet occur reasons:
first error occurs when long packet overrun
middle packet (only some data missing). L64381 asserts ABORT_OUT when last byte bytes) current packet read.
second error occurs when packets arrive
from network: packet arrives first, packet follows. Because receive FIFO overrun condition,
Signal Descriptions
L64381 drops last several bytes packet signal packet before receives packet Even L64381 successfully receives packet without error, asserts ABORT_OUT with packet Transmit operation, L64381 assert ABORT_OUT anytime during packet write operation many reasons:
L64381 detects late collision detects excessive collisions detects collision Packet
Configuration Register
detects transmit FIFO underrun error detects invalid BYTE_VALID[3:0] combination
case, L64381 asserts ABORT_OUT only during write attempt same packet port that just encountered error. ABORT_OUT asserted when first write operation after failure occurs. L64381 ignores subsequent write transfers same packet until detects start packet. nontransmit FIFO underrun error occurs during last write transfer packet, L64381 does assert ABORT_OUT next packet. L64381 does assert ABORT_OUT current packet that packet ends within FIFO. L64381 simply flushes packet from FIFO. L64381 requires three cycles after write transfer send transmit FIFO pointer values network. L64381 detect transmit FIFO underrun error while write transfer last portion packet occurring (with asserted). L64381 detects this error within three cycles after asserts EOP. write transfer starts same port within five cycles previous write transfer, L64381 asserts ABORT_OUT. failing condition following:
L64381 detected Receive FIFO overrun Packet being received runt packet Packet being received oversized packet
Interface Signals
Packet being received L64381 detected error.
L64381 does read failing packet Interface packet resides Receive FIFO, L64381 does flush Receive FIFO. L64381 updates appropriate Statistics Counters waits external device remove data. When packet drains completely, L64381 asserts ABORT_OUT with external device errored packet signaling. When data being written Transmit FIFO Interface, current packet being written also being transmitted Network Interface, L64381 detects failing condition Network Interface, L64381 asserts ABORT_OUT signal, updates appropriate Statistics Counters based failing condition, flushes current packet from Transmit FIFO. failing condition following:
L64381 detected late collision L64381 detected excessive collisions L64381 detected collision, autostore
64-byte mode
L64381 detected Transmit FIFO underrun error L64381 detected invalid BYTE_VALID[3:0]
combination AI_FCS_IN Autoinsert Input L64381 latches AI_FCS_IN when WRITE_IN_PKT both asserted. Assertion this input while asserted causes L64381 automatically calculate insert value from packet data into field Ethernet packet. this input deasserted when WRITE_IN_PKT both asserted, then data provided transmission must contain field. Buffer Available Output L64381 asserts this signal response assertion STROBE when Transmit FIFO enough empty space available store data from transfer. FIFO deemed have enough space
BUF_AVAIL
Signal Descriptions
space equal more than number words specified Transfer Size field (BUS) L64381 Configuration Register This signal valid four cycles following assertion STROBE. state this signal four cycles following assertion STROBE indicates Transmit FIFO space availability Ports [3:0], respectively. time assertion STROBE, transfer occurring, then BUF_AVAIL asserted that particular port does indicate correct status other ports. BYTE_VALID[3:0] Valid Bytes Bidirectional These pins indicate which bytes valid current word. Byte refers DATA[7:0], Byte refers DATA[15:8], Byte refers DATA[23:16], Byte refers DATA[31:24]. following table shows valid combinations BYTE_VALID[3:0].
BYTE_VALID[3:0] 0000 1000 1100 1110 0001 0011 0111 DATA[31:0] Bytes Valid Bytes Valid Bytes Valid Byte Valid Bytes Valid Bytes Valid Byte Valid
Note:
bytes transferred with have above combinations except BYTE_VALID[3:0] 11112. Bytes transferred between have only BYTE_VALID[3:0] 00002. other combinations listed above invalid.
While writing packet from bus, L64381 accepts seven valid BYTE_VALID[3:0] combinations: 00002, 10002, 11002, 11102, 00012, 00112, 01112. However, receiving with asserted, L64381 always asserts BYTE_VALID[3:0] 00002. receiving with asserted, L64381 asserts BYTE_VALID[3:0] four combinations:
Interface Signals
11102, 11002, 10002, 00002. receiving with asserted dribbling bits, L64381 asserts both BYTE_VALID[3:0] 11112 ABORT_OUT signal error condition. invalid combination encountered packet already started transmission network, then L64381 aborts packet network (after transmitting alternating ones zeros). entire packet FIFO then flushed from FIFO without being transmitted network. entire packet FIFO, then L64381 asserts ABORT_OUT, system expected drop packet externally continue with packet. system continues write current packet, then L64381 ignores until next SOP. DATA[31:0] L64381 Data Bidirectional This data interface from L64381. Packet Bidirectional Assertion indicates Packet when occurs current word that being placed Interface. Packet Available Output L64381 asserts PKT_AVAIL response assertion STROBE when Receiver FIFO enough data transfer Interface. FIFO deemed have enough data either:
PKT_AVAIL
Contains data that equal more than number words specified Transfer Size field (BUS) Configuration Register
Contains Packet
This signal valid four cycles following assertion STROBE. state this signal four cycles following assertion STROBE indicates Receiver FIFO space availability Ports [3:0], respectively. time assertion STROBE, transfer occurring, then PKT_AVAIL asserted that particular port, continues indicate correct status other ports.
3-10
Signal Descriptions
PORT_BUSY Port Status Output half-duplex mode (the DUPLEX field Configuration Register reset zero), L64381 asserts PORT_BUSY indicate selected port either transmitting receiving. full-duplex mode, L64381 asserts PORT_BUSY indicate port transmitting. PORT_NO[1:0] Port Number Input state these inputs determines which port number [3:0] READ_OUT_PKT WRITE_IN_PKT inputs ABORT_OUT output refer. following table shows encoding these inputs.
PORT_NO[1:0] Port Number
READ_OUT_PKT Read Data from Receive FIFO Input This input informs L64381 place data Receive FIFO Interface. PORT_NO bits indicate which port's FIFO read. Start Packet Bidirectional Assertion indicates Start Packet when occurs current data transfer. Strobe Input four cycles following assertion STROBE, L64381 places status Ports [3:0] respectively PKT_AVAIL, BUF_AVAIL, PORT_BUSY signals. STROBE held asserted, status each four ports placed PKT_AVAIL, BUF_AVAIL, PORT_BUSY every four cycles.
STROBE
WRITE_IN_PKT Write Data Transmit FIFO Input This input informs L64381 write data that Interface Transmit FIFO. PORT_NO bits indicate which port's Transmit FIFO written.
Interface Signals
3-11
Processor Interface Signals
This section describes signals that comprise L64381's Processor Interface. ADRS[5:0] Register Select Address Input These pins determine which L64381 register access. ADRS[5:0] latched into L64381 rising system clock edge (CLOCK) immediately following assertion ADRS_STROBE CHIP_SELECT.
ADRS_STROBE Address Strobe Input Assertion ADRS_STROBE along with assertion CHIP_SELECT causes L64381 latch ADRS inputs. CHIP_SELECT Chip Select Input Assertion this input enables access from L64381 from Processor Interface. absolute worst-case condition, statistics counters need updated when host tries access them. access time from ADRS_STROBE PREADY 100+ cycles. applications with multiple L64381 devices sharing same processor interface, when such worst-case condition occurs, deassert particular L64381 chip select, which terminates current transaction allows other devices bus, desired. INTERRUPT Interrupt Output L64381 asserts INTERRUPT whenever error Error Register that been masked. interrupt generally indicates condition which processor needs resolve. Processor Data Bidirectional This 16-bit contains data that transferred between L64381 processor. Ready Output During write L64381's registers, L64381 asserts PREADY cycle after rising edge which PDATA data latched. read instruction, L64381 drives PREADY cycle after places data PDATA bus. Data read
PDATA[15:0]
PREADY
3-12
Signal Descriptions
rising edge CLOCK during which PREADY driven LOW. READ Read Input This input determines whether operation going write L64381 (READ HIGH) read from L64381 (READ LOW). with ADRS[5:0], L64381 latches this signal when ADRS_STROBE CHIP_SELECT asserted. Reset Input Assertion RESET resets L64381. RESET signal should asserted least reset, L64381 resets register contents zeros, 3-states bidirectional signals, places outputs their nonasserted states. Note: Asserting RESET sets Enable Port bits ones disable ports.
RESET
Status Signals
This section describes signals whose status intended viewed using LEDs. COLLOUTN Collision Output This multiplexes Collision Status from four ports. asserted when port detects collision Network Interface. LEDSEL[1:0] pins this used along with external logic drive LEDs. Link Inverted Output This Link Inverted Signal from four ports multiplexer selects which port's LBADN signal output). Each port asserts LBADN when inverted connection detected Network Interface. LBADN combined with external logic drive LED, allowing status LBADN viewed. LEDSEL[1:0] indicate which port selected.
LBADN
Status Signals
3-13
LEDSEL[1:0] Select Output These pins indicate which port's status being output COLLOUTN, LBADN, LPASSN, RCVNGN, TRNSMTN current cycle.
LEDSEL[1:0] Port Selected
LPASSN
Link Test Status Output This Link Test Status four ports multiplexer selects which port's LPASSN signal output). L64381 asserts LPASSN when Link test passes. LPASSN combined with external logic drive LED, allowing status LPASSN viewed. LEDSEL[1:0] indicate which port selected. Receiver Status Output This Receiver Status from four ports multiplexer selects which port's RCVNGN signal output). L64381 asserts RCVNGN when port receiving data Network Interface. RCVNGN combined with external logic drive LED, allowing status RCVNGN viewed. LEDSEL[1:0] indicate which port selected. Transmitter Status Output This Transmitter Status from four ports multiplexer selects which port's TRNSMTN signal output). asserted when port transmitting data Network Interface. TRNSMTN combined with external logic drive LED, allowing status TRNSMTN viewed. LEDSEL[1:0] indicate which port selected.
RCVNGN
TRNSMTN
3-14
Signal Descriptions
Clock Signals
This section describes input clocks required L64381's operation. CLOCK System Clock Input This 16-MHz 33-MHz clock used internal operation L64381, Interface, Processor Interface.
CLOCK_20MHZ Internal Clock Input L64381 uses this 20-MHz clock generate 80-, 20-, 10-MHz clocks used ports.
Test Signals
This section describes signals that comprise L64381's test circuitry. JTAG signals operate described IEEE Standard Test Access Port Boundary-Scan Architecture (IEEE1149) document. P_TESTN Global 3-State Input Assertion this input 3-states output bidirectional pins L64381. This input held HIGH during normal operation. JTAG Test Clock Input JTAG Test Clock. typically duty cycle clock running minimum. JTAG Test Data Input Serial test instructions data input through pin. JTAG Test Data Output result serial test instructions data that were input through output TDO. JTAG Test Mode Select Input controller decodes this input determine test operations. JTAG Test Reset Input Assertion this active signal provides asynchronous initialization controller.
TRSTN
Clock Signals
3-15
Miscellaneous Signals
This section describes remaining signals L64381. Phase Detector Output Output output phase detector, which embedded within on-chip PLL. Input Input input voltage-controlled oscillator (VCO). Phased-Locked Loop Analog Ground Output This output analog ground phased locked loop. Phased-Locked Loop Power Input This input provides power phased locked loop. Phased-Locked Loop Digital Ground Input This input digital ground phased locked loop. Power Input inputs power pins. inputs connected single supply. However, minimize digital noise coupling, L64381 provides individual inputs Ports [3:0]. Refer Section 7.3, "Special Connections," assignments these power pins. Ground Input inputs ground pins. inputs tied together. However, minimize digital noise coupling, L64381 provides individual inputs Ports [3:0]. Refer Section 7.3, "Special Connections," assignments these ground pins.
PLLAGND
PLLVDD PLLVSS
3-16
Signal Descriptions
Chapter L64381 Operation
This chapter provides detailed description functional blocks interfaces within L64381. This chapter contains eight sections:
Section 4.1, "Ethernet Cores" Section 4.2, "On-chip FIFOs" Section 4.3, "Bus Interface" Section 4.4, "Processor Interface" Section 4.5, "PLL Connections" Section 4.6, "Twisted-Pair Interface" Section 4.7, "AUI Interface" Section 4.8, "JTAG Initialization"
Figure shows L64381 block diagram.
Figure L64381 Block Diagram
Processor Interface
Statistics Counters
Configuration Control Receive FIFO
Port
Ethernet Core
Transmit FIFO
Statistics Counters Receive FIFO Port Ethernet Core Transmit FIFO Interface Receive FIFO Port Ethernet Core Transmit FIFO
Twisted-Pair Interface
Statistics Counters
Statistics Counters Receive FIFO Port Ethernet Core Transmit FIFO
Ethernet Cores
Ethernet cores that comprise four ports fully synchronous designs. synchronous design benefit being predictable reliable because logic output signals change known times with respect clock. core processes data Mbit/s half-duplex mode Mbit/s full-duplex mode provides comprehensive solution 10BASE-T based systems. core engine gives designer very effective
L64381 Operation
systems integration building block developing next-generation networking products switched router applications. core also enables highest form system integration workstation high-end converting system logic into singlechip solution. functional blocks within core are:
Manchester Encoder/Decoder. core contains integrated
Encoder/Decoder function that performs Manchester encoding decoding, utilizes digital phase-locked loop data recovery Mbit/s.
Media Access Control (MAC). Media Access Control function
provides simple efficient packet transmission reception control means parallel eight-bit data interfaces.
Transceiver Interface. core provides inputs outputs that
easily connected on-chip integrated 10BASE-T (twisted-pair) transceivers compatible with IEEE 802.3 networks. core also provide signals 10BASE-2, 10BASE-5, 10BASE-F media. core connected directly interface.
transceiver interface logic incorporates transmitter, receiver,
collision, link integrity, loopback functions defined standard.
On-chip FIFOs
Each Ethernet port L64381 contains 128-byte Transmit FIFO 128-byte Receive FIFO. Each location addresses word (four bytes) data, along with four encoded value bits. FIFO also maintains Start-of-Packet End-of-Packet information, which makes actual FIFO structure bits. FIFO pointers maintained registers L64381. FIFO access circuit designed that allows FIFO reads writes from Ethernet ports from Interface happen without conflicts delays. Figure shows 128-byte FIFO configuration. lower bits (four words) data; most-significant four bits user-encoded values BYTE_VALID[3:0], SOP, EOP, AI_FCS_IN when interface transaction occurs. RRAM WRAM fields Data FIFO Address Register correspond upper four bits FIFO reads writes, respectively. Refer Section 2.7, "Data FIFO Regis-
On-chip FIFOs
ters," more information accessing Data FIFOs using Data FIFO registers.
Figure Data FIFO Block Diagram
bits bits Words
4.2.1 Transmit FIFO
Transmit FIFO configured store first bytes packet until first bytes have been successfully transmitted. This allows chip retransmit packet without requiring access when collision occurs first 51.2 Once first bytes have been successfully transmitted, FIFO releases first bytes, thus allowing utilization whole FIFO storage. Transmit FIFO also allows storage succeeding packets transmitted while previous packet still being transmitted. This feature allows back-to-back transmissions packets without wasted bandwidth Ethernet, also allows better usage FIFO. late collision occurs transmission packet, then chip generates interrupt updates appropriate Statistics Counters. Processor then read error register, decide appropriate action. another packet available transmission
L64381 Operation
Words
Transmit FIFO, L64381 starts transmitting after waiting appropriate back-off time. Transmit FIFO asserts BUF_AVAIL signal when least many entries empty specified Transfer Size field (BUS). This assertion signals system that L64381 accommodate Transfer Size amount data into Transmit FIFO. system can, this point, write packet data into FIFO. Transmit FIFO initiates transmission Ethernet when detects that FIFO least many words specified Transmit Threshold field, Transmit FIFO detects stored FIFO. This situation arise when Auto feature enabled port. system must guarantee that place into FIFO data transmitted faster than time taken transmit data already FIFO. Transmit Threshold field provides means delaying start transmission slower systems. Transmit FIFO sets Transmit FIFO Underrun Error Error Register FIFO detects underrun condition. Transmit FIFO never overrun, because Bus-In State Machine (described Section 4.3.2, "Bus-In State Machine") does request write into Transmit FIFO until enough room data. 4.2.2 Receive FIFO Receive FIFO configured initiate transfer when Transfer Size threshold been met, Receive FIFO detects stored FIFO. This situation arise when packet size multiple Transfer Size, packet runt packet. Receive FIFO initiates this transfer setting PKT_AVAIL signal. This threshold programmed words. threshold setting four words allows transmission packet with minimal latency, while setting words allows greater bandwidth (since fewer idle cycles need inserted between transfers). Receive FIFO sets Receive FIFO Overrun Error Error register FIFO detects overrun condition. Receive FIFO never underrun, since Bus-Out State Machine (4.3.1, "Bus-Out State Machine,") does request read from Receive FIFO until enough data FIFO.
On-chip FIFOs
Interface 4.3.1 Bus-Out State Machine
L64381 Interface comprised state machines: This section describes both state machines detail. Interface four Bus-Out State Machines, each Ethernet port. Each Bus-Out State Machine responsible transferring data received port other devices Interface. When word data been received from Ethernet, L64381 places into Receive FIFO. When FIFO contains many words specified Transfer Size field Configuration Register FIFO contains EOP), Bus-Out State Machine asserts appropriate PKT_AVAIL_PORTx signal, where equals port number PKT_AVAIL_PORTx signals from four on-chip Ethernet ports multiplexed PKT_AVAIL signal device pins. multiplexing done with respect STROBE input. When L64381 receives assertion STROBE input, places states PKT_AVAIL_PORTx signals onto device following four cycles, with PORT placed first, PORT placed last. Figure shows timing relationship between these signals.
Figure STROBE PKT_AVAIL Timing Relationship
CLOCK STROBE
PORT PORT PORT PORT
PKT_AVAIL BUF_AVAIL
When Bus-Out State Machine receives assertion READ_OUT_PKT signal with corresponding port number PORT_NO[1:0] inputs, starts sending data DATA[31:0], BYTE_VALID[3:0], SOP, outputs following cycle. L64381 drives these output signals cycle following detection READ_OUT_PKT signal assertion. external device will unable latch data third cycle. Refer functional waveforms cycle count between signal transitions when such conflict occurs. state machine fetches data from head Receive FIFO, transfers number words specified Transfer Size field. Figure shows details handshaking during read.
L64381 Operation
Figure Reading Packets from L64381
CLOCK
STROBE PORT PORT PORT PORT PKT_AVAIL
READ_OUT_PKT
PORT_NO[1:0]
DATA[31:0]4 SOP4
DATA[31:0]5 SOP5 BYTE_VALID[3:0]
PID1
00002
00002
PORT PORT PORT PORT PORT_BUSY ABORT_OUT
first word contains port when SOPCFG Configuration Register Valid values BYTE_VALID[3:0] 00002, 10002, 11002 11102. When L64381 detects dribble bits, asserts ABORT_OUT with BYTE_VALID[3:0] 11112 SOPCFG, Configuration Register SOPCFG, Configuration Register
data being transferred start packet, then state machine also asserts output (Port Figure 4.4). Similarly, data being transmitted packet, then state machine asserts signal (Port Figure 4.4). Note that
Interface
always occurs first second word transfer, occur anywhere within transfer. L64381 assert ABORT_OUT failing condition only with during read. ABORT_OUT asserted only cycle. There should least wait cycle between consecutive reads. Figure shows wait states asserted between reads from Port Port When signal occurs middle transfer, state machine drives idle data (zeros) DATA[31:0] outputs ones BYTE_VALID[3:0], SOP, outputs following cycles until detects deassertion READ_OUT_PKT signal, which time 3-states DATA[31:0], BYTE_VALID[3:0], SOP, EOP. Figure shows read from Port with assertion middle transfer.
Figure Read Packet with Middle Transfer
CLOCK
STROBE PORT PORT PORT PORT PKT_AVAIL READ_OUT_PKT
PORT_NO[1:0]
00002 0x00000000
DATA[31:0] BYTE_VALID[3:0]
11112
Valid values BYTE_VALID[3:0] 00002, 00012, 00112 0111
current data transfer does contain packet, then state machine transfers number words specified Transfer Size, then 3-states DATA[31:0], BYTE_VALID[3:0], SOP, signals after READ_OUT_PKT signal deasserted. This operation allows external arbitration logic grant another device without having wait Transfer Size amount cycles. state machine detects that READ_OUT_PKT signal
L64381 Operation
deasserted before Transfer Size amount data been transferred (and this packet), then state machine assumes that external arbitration wanted preempt this transfer, 3-states DATA[31:0], BYTE_VALID[3:0], SOP, signals. When next transfer from this FIFO initiated, state machine starts fetching data from FIFO location following that last transferred previous access. L64381 detects assertion ABORT_IN signal while transfer progress, then stops current transfer resets Receive FIFO head pointer value contained just before transfer started. After asserted ABORT_IN signal latched L64381, READ_OUT_PKT still asserted, L64381 drives idle data (zeros) DATA[31:0] outputs ones BYTE_VALID[3:0], SOP, outputs throughout current cycle. abort read transfer, ABORT_IN should asserted that latched clock edges which L64381 puts data data bus. ABORT_IN needs asserted cycle only, ignored asserted after EOP. Figure shows read transfer that aborted asserting ABORT_IN. also shows window which ABORT_IN should asserted.
Interface
Figure Read Data with ABORT_IN Assertion
CLOCK
STROBE PORT PORT PORT PORT PKT_AVAIL READ_OUT_PKT
PORT_NO[1:0]
DATA[31:0] BYTE_VALID[3:0]
00002
11112
00002
ABORT_IN ABORT_IN Assertion Window
arbitration chip receives assertion PKT_AVAIL signal grants request asserting READ_OUT_PKT PORT_NO[1:0] signals. response these inputs, Bus-Out State Machine drives DATA[31:0], BYTE_VALID[3:0], SOP, signals. After state machine writes Transfer Size number words, 3-states DATA[31:0], BYTE_VALID[3:0], SOP, signals. Because arbitration chip knows that L64381 only drives Transfer Size cycles, pipeline READ_OUT_PKT PORT_NO[1:0] signals different devices ensure minimum idle cycles. 4.3.2 Bus-In State Machine There four Bus-In State Machines chip, Ethernet port. Bus-In State Machine responsible receiving data that transmitted Ethernet. When state machine detects that Transmit FIFO least many empty locations specified Transfer Size, drives BUF_AVAIL signal active corresponding port. This signal multiplexed onto BUF_AVAIL device output same manner PKT_AVAIL signal. Figure shows timing relationship between STROBE BUF_AVAIL signals.
4-10
L64381 Operation
Figure STROBE BUF_AVAIL Timing
CLOCK STROBE
PORT0 PORT1 PORT2 PORT3
PKT_AVAIL BUF_AVAIL
When Bus-In State Machine receives WRITE_IN_PKT signal corresponding port number PORT_NO[1:0] inputs, writes DATA[31:0] along with encoded BYTE_VALID[3:0], SOP, signals into Transmit FIFO using tail pointer (refer Chapter "Registers," more information tail pointer). state machine detects either asserted deasserted WRITE_IN_PKT signal input, stops writing more data into Transmit FIFO after that cycle. Figure shows details handshaking during write. There should least wait cycle between consecutive writes.
Interface
4-11
Figure Writing Packets L64381 with Port Operation Aborted
CLOCK
STROBE PORT PORT PORT PORT BUF_AVAIL WRITE_IN_PKT 00002
PORT_NO[1:0]
DATA[31:0] BYTE_VALID[3:0]
00002
00002
PORT PORT PORT PORT PORT_BUSY ABORT_IN
AI_FCS_IN
Valid values BYTE_VALID[3:0] 00002, 00012, 00112, 01112, 10002, 11002 11102.
L64381 detects assertion ABORT_IN signal while write progress, then restores Transmit FIFO Tail Pointer value contained just before transfer started. ABORT_IN should asserted that latched clock edges which L64381 latches data from data bus. ignored asserted after assertion EOP. ABORT_IN asserted cycle only. When ABORT_IN asserted, WRITE_IN_PKT terminated same time. Figure shows ABORT_IN assertion Port write operation, which effect following Port operation.
4-12
L64381 Operation
L64381 assert ABORT_OUT, failing condition, during write. ABORT_OUT deasserted only after WRITE_IN_PKT deasserted. Figure shows assertion ABORT_OUT during write transfer Port
Figure Writing Packets L64381 with ABORT_OUT Asserted
CLOCK
STROBE PORT PORT PORT PORT BUF_AVAIL WRITE_IN_PKT
PORT_NO[1:0]
DATA[31:0] BYTE_VALID[3:0]
00002
ABORT_OUT
arbitration chip receives assertion BUF_AVAIL, grants request asserting WRITE_IN_PKT PORT_NO[1:0] signals when data write L64381. source transfer then drives DATA[31:0], BYTE_VALID[3:0], SOP, signals, Bus-In State Machine writes data into Transmit FIFO. After state machine writes Transfer Size number words, stops writing FIFO. Because arbitration chip knows that L64381 only drives Transfer Size cycles, pipeline WRITE_IN_PKT PORT_NO[1:0] signals different devices ensure minimum latency. Figure 4.10 shows read transfer followed write, Figure 4.11 illustrates write transfer followed read. Figure 4.10 shows that least cycles needed between deassertion READ_OUT_PKT assertion WRITE_IN_PKT when read followed write. This prevent contention data bus. Figure 4.11 shows that there should least cycle between
Interface
4-13
deassertion WRITE_IN_PKT assertion READ_OUT_PKT, that PORT_NO[1:0] properly asserted throughout entire write cycle.
Figure 4.10 Read-then-Write Operations
CLOCK
STROBE
PORT
BUF_AVAIL PORT
PKT_AVAIL READ_OUT_PKT WRITE_IN_PKT
PORT_NO[1:0]
DATA[31:0] BYTE_VALID[3:0]
00002
00002
4-14
L64381 Operation
Figure 4.11 Write-then-Read Operations
CLOCK
STROBE PORT BUF_AVAIL PORT
PKT_AVAIL READ_OUT_PKT WRITE_IN_PKT
PORT_NO[1:0]
DATA[31:0] BYTE_VALID[3:0]
00002
00002
Processor Interface
Processor Interface used configure L64381, read port statistics, read write internal registers L64381. Since statistics counters shared resource between processor interface internal network interface, internal network interface higher priority over processor interface. access time processor accesses statistics counters vary. Refer description CHIP_SELECT page 3-12 more information. processor asserts CHIP_SELECT, READ, ADRS_STROBE signals read internal registers L64381. When chip detects both ADRS_STROBE CHIP_SELECT asserted, then next rising edge CLOCK, latches address from ADRS[5:0] inputs, latches instruction type from READ input. L64381 asserts PREADY signal cycle after placed read data onto PDATA[15:0] bus.
4.4.1 Reading L64381 Internal Registers
Processor Interface
4-15
Figure 4.12 shows timing relationship read accesses.
Figure 4.12 Processor Read Timing
CLOCK CHIP_SELECT ADRS_STROBE ADRS[5:0] READ PDATA[15:0] PREADY DATA
4.4.2 Writing L64381 Internal Registers
write internal registers L64381, processor asserts CHIP_SELECT ADRS_STROBE signals deasserts READ signal. When L64381 detects both ADRS_STROBE CHIP_SELECT asserted, then next rising edge CLOCK, latches address from ADRS[5:0] inputs, latches instruction type from READ input. L64381 asserts PREADY signal cycle after latched data PDATA[15:0]. Figure 4.13 shows timing relationship write accesses.
Figure 4.13 Processor Write Timing
CLOCK CHIP_SELECT ADRS_STROBE ADRS[5:0] READ PDATA[15:0] PREADY DATA
4-16
L64381 Operation
4.4.3 Burst Mode Reads Statistics Counters
burst mode read accesses from Statistics Counters, L64381 places data PDATA[15:0] bus, toggles PREADY signal cycle every time places data PDATA[15:0] bus. Figure 4.14 shows timing relationship burst mode accesses burst size four halfwords. Note that even though figure shows data being placed PDATA[15:0] every other clock cycle, actual number cycles that elapse between successive data being placed PDATA[15:0] vary. PREADY signal indicates when data valid PDATA[15:0] bus.
Figure 4.14 Burst Read Access Timing L64381
CLOCK CHIP_SELECT ADRS_STROBE ADRS[5:0] READ PDATA[15:0] PREADY
Connections
Each four ports within L64381 contains digital phase-locked loop (DPLL) data recovery. 80-MHz clock that drives DPLL synthesized using analog L64381. analog consists phase comparator, voltage-controlled oscillator, external loop filter. reference clock input 20-MHz clock (CLOCK_20MHZ). Figure 4.15 shows external loop filter circuit, which connects internal analog PLL. also shows PLLVDD decoupling circuit.
Connections
4-17
Figure 4.15 Loop Filter PLLVDD Decoupling
Loop Filter
PLLAGND
(Power Plane)
PLLVDD .047 PLLVDD Decoupling
Twisted-Pair Interface
Figure 4.16 shows L64381 port connected 10Base-T twisted-pair connector.
Figure 4.16 Typical L64381 TwistedPair Application
ASIC Ethernet Core DATAP PREEP DATAN PREEN Receivers IDIFH1D DDRV TXI+5 TXOCommon RCV+ RCVR9 RXT+ RXT8 Shield Transmitters B24A Integrated Filter/ Transformer/Choke PE-64026 Pulse TXI+ TXO+ Connector RJ45
DATATN DATAI DATATP
4-18
L64381 Operation
Interface
Figure 4.17 Typical L64381 Application
Figure 4.17 shows L64381 port connected connector.
ASIC Ethernet Core DATAP DATAN PE-64107 Pulse DDRV Receivers IDIFH1D Transmitters B24A 330pF Connector
DATATN DATAI DATATP
+12V
COLLIN
COLLIP
DDRV
JTAG Initialization
ensure proper operation L64381, internal JTAG circuitry must disabled. L64381 uses TRSTN signal this purpose. Asserting TRSTN asynchronously initializes controller Test-Logic-Reset state. Holding TRSTN keeps controller this state prevents JTAG circuitry from interfering with L64381's other on-chip logic. TRSTN connected guarantee permanent signal. Section 3.6, "Test Signals", more information TRSTN signal.
Interface
4-19
4-20
L64381 Operation
Chapter Statistics Counters
L64381 provides following statistics maintained 32-bit counters. this section, unless otherwise stated, size packet includes Source Destination Fields, Length Type field, Data Frame Check Sequence fields, does include Preamble Start Frame Delimiter fields. Statistics updated after attempt transfer receive packet made, regardless whether attempt successful not. Statistics Counters must initialized before they used. initialize counters, write zeros memory locations Statistics Counters. Each counter unique address that stored Statistics Counter Address Register. Table lists Statistics Counters, their contents, brief descriptions.
Table Descriptions Statistics Counters Counter Contents Number bytes received Number internal receive errors Description This counter counts bytes within packets received from receiver. This counter counts number packets that were lost because internal errors L64381, that affect this particular Ethernet connection. These errors FIFO overrun PLL. This counter counts total number packets received from receiver, regardless whether they were received with without error.
Number packets received
Number broadcast packets received This counter counts number packets received without errors, that also broadcast address destination field packet (all ones). Number multicast packets received This counter counts number packets received without errors, also that multicast address destination field packet. This number does include broadcast packets. Number receive errors This counter counts number packets received between bytes 1518 bytes length, were integral number bytes length, Frame Check Sequence. This counter counts number packets less than bytes long that were integral number bytes long.
Number runt packets received
Number oversized packets received This counter counts number packets more than 1518 bytes long that were integral number bytes long. Number total collisions This counter counts number collisions detected when transmitting half-duplex mode. This counter counts packets received L64381 that were bytes length. This counter counts packets received L64381 that were bytes length. This counter counts packets received L64381 that were bytes length.
Number byte packets received Number byte packets received Number byte packets received
(Sheet
Statistics Counters
Table (Cont.) Descriptions Statistics Counters Counter Contents Number byte packets received Number 1023 byte packets received Description This counter counts packets received L64381 that were bytes length. This counter counts packets received L64381 that were 1023 bytes length.
Number 1024 1518 byte packets This counter counts packets received received L64381 that were 1024 1518 bytes length. Number internal transmit errors This counter counts number internal errors L64381, affect this particular Ethernet connection. Typical errors would FIFO underrun errors invalid data BYTE_VALID[3:0], SOP, fields. This counter counts number collisions after first bytes packet were successfully transmitted Ethernet. This counter counts number packets transmitted from L64381 that were less than bytes length. This counter counts packets transmitted from L64381 that were greater than 1518 bytes length were integral number bytes long. This counter counts packets successfully transmitted from L64381. This counter counts total number bytes successfully transmitted from L64381. This counter counts total number multicast packets transmitted from L64381. This counter counts total number broadcast packets transmitted from L64381.
Number late collisions
Number runt packets transmitted
Number greater than 1518 byte packets transmitted Number packets successfully transmitted Number bytes successfully transmitted Number multicast packets transmitted Number broadcast packets transmitted Reserved Reserved
(Sheet
Statistics Counters
Chapter Instruction
Chapter lists instructions that sent L64381 Processor Interface. Most instructions read write L64381 internal registers. L64381 also provides special instructions that facilitate transfers statistical information that control observe registers FIFOs. Refer Chapter "Registers," more details register descriptions. This chapter contains following sections:
Section 6.1, "Instruction Summary" Section 6.2, "Accessing Data FIFO" Section 6.3, "Accessing Statistics Counters"
Instruction Summary Table lists L64381 instructions. instructions ordered according instruction type: read/write register, read autoincrement, burst read. Certain instructions operate only specific Diagnostic Modes. Table also specifies particular operating mode(s).
Table L64381 Instructions Opcode READ Valid Mode(s) Operation
Read/Write Register Instructions 000000 000000 000010 000010 000011 000011 000100 (Sheet Read Write Read Write Read Write Read Configuration Register Configuration Register Configuration Register Configuration Register Ethernet Address Register
Table (Cont.) L64381 Instructions Opcode READ Valid Mode(s) Operation
Read/Write Register Instructions (Cont.) 000100 Write Ethernet Address Register 000101 Read Ethernet Address Register 000101 Write Ethernet Address Register 000110 Read Ethernet Address Register 000110 Write Ethernet Address Register 000111 Read Packet Configuration Register 000111 Write Packet Configuration Register 001000 Read Error Register 001000 Write Error Register 001010 Read Error Register 001010 Write Error Register 001001 Read Error Mask Register 001001 Write Error Mask Register 001011 Read Error Mask Register 001011 Write Error Mask Register 010110 Read Statistics Counters Address Register 010110 Write Statistics Counters Address Register 100000 Read Receive FIFO Head Pointer Register Write Receive FIFO Head Pointer Register 100000 100001 Read Receive FIFO Head Pointer Register Write Receive FIFO Head Pointer Register 100001 100010 Read Receive FIFO Tail Pointer Register Write Receive FIFO Tail Pointer Register 100010 100011 Read Receive FIFO Tail Pointer Register Write Receive FIFO Tail Pointer Register 100011 100100 Read Transmit FIFO Head Pointer Register Write Transmit FIFO Head Pointer Register 100100 100101 Read Transmit FIFO Head Pointer Register Write Transmit FIFO Head Pointer Register 100101 100110 Read Transmit FIFO Tail Pointer Register Write Transmit FIFO Tail Pointer Register 100110 100111 Read Transmit FIFO Tail Pointer Register 100111 010000 (Sheet Write Transmit FIFO Tail Pointer Register Read Statistics Counters Data Register
Instruction
Table (Cont.) L64381 Instructions Opcode READ Valid Mode(s) Operation
Read/Write Register Instructions (Cont.) 010000 Write Statistics Counters Data Register 010001 Read Statistics Counters Data Register 010001 Write Statistics Counters Data Register 010010 Read Statistics Counters Data Register 010011 Read Statistics Counters Data Register 011000 Read Data FIFO Data Register Write Data FIFO Data Register 011000 011001 Read Data FIFO Data Register Write Data FIFO Data Register 011001 011010 Read Data FIFO Data Register 011011 Read Data FIFO Data Register 011110 Read Data FIFO Address Register 011110 Write Data FIFO Address Register 101000 Read Receive Counter Write Receive Counter 101000 101001 Read Receive Counter Write Receive Counter 101001 Read Transmit Counter 101010 101010 Write Transmit Counter 101011 Read Transmit Counter Write Transmit Counter 101011 Read Autoincrement Instructions 110100 110100 111000 111000 110011 (Sheet These instructions provided testing purposes, should used only when L64381 Diagnostics Modes However, L64381 does restrict these instructions other modes. result these instructions guaranteed other modes. Read Write Read Write Single Statistics Counter Single Statistics Counter Data FIFO Data FIFO
Burst Read Instructions Burst Read Statistics Counters
Instruction Summary
Care must taken when modifying configuration L64381 while actively transmitting receiving packet Network Interface Interface. change configuration lead unpredictable incorrect operation. Thus configuration modes should only changed when L64381 either Diagnostics Modes idle Diagnostic Modes
Accessing Data FIFO 6.2.1 Reading Data FIFO
This section details instructions that read write contents Data FIFO. These operations possible only Modes
following steps describe read location Data FIFO: Load FIFO address read (use Write Data FIFO Address Register instruction). Execute Read Data FIFO instruction. Read least-significant halfword from Data FIFO Data Register Read most-significant halfword from Data FIFO Data Register Read bits [15:12] Data FIFO Address Register (the RRAM field), which contain bits [35:32] Data FIFO.
6.2.2 Writing Data FIFO
following steps describe write location Data FIFO: Load FIFO address written (use Write Data FIFO Address Register instruction). same time, load bits [11:8] Data FIFO Address Register (the WRAM field) with desired value bits [35:32] Data FIFO. Load least-significant halfword into Data FIFO Data Register Load most-significant halfword into Data FIFO Data Register Execute Write Data FIFO instruction.
Instruction
Accessing Statistics Counters 6.3.1 Reading Statistics Counters
This section details three types instructions that access Statistics Counters: read, burst read, write.
following steps describe read single Statistics Counter: Load Statistics Counter number read (use Write Statistics Counters Address Register instruction). Execute Read Single Statistics Counter instruction. When autoincrement mode, this instruction causes Statistics Counters Address Register autoincrement it's value after read been performed. Read least-significant halfword from Statistics Counters Data-Out Register Read most-significant halfword from Statistics Counters Data-Out Register data read placed into PDATA[15:0] bus. Because Statistics FIFO 32-bits wide PDATA[15:0] 16-bits wide, Read Single Statistics Counter instructions executed. These instructions facilitate reads statistics from L64381 processor capable performing burst mode read operations.
6.3.2 Writing Statistics Counters
following steps describe write single Statistics Counter: Load Statistics Counter number written (use Write Statistics Counters Address Register instruction). Load least-significant halfword into Statistics Counters Data-In Register Load most-significant halfword into Statistics Counters Data-In Register Execute Write Single Statistics Counter instruction. This instruction causes data Statistics Counters Data-In Registers loaded into Statistics FIFO, address Statistics Counters Address Register autoincremented. This feature provided autoincrement mode reduce number instructions needed test Statistics Counters.
Accessing Statistics Counters
6.3.3 Burst Read Statistics Counters
L64381 Statistics Counters read from Processor Interface using Burst Read instructions. following steps describe implement burst read: Load Statistics Counter number read (use Write Statistics Counters Address Register instruction). Execute Burst Read Statistics Counter instruction. Upon detecting this instruction, L64381 automatically fetches statistics given port, places data Statistics Counters Data-Out registers. L64381 then places data from these registers PDATA[15:0] bus. number counters read depends value programmed Burst Size Field Configuration Register PREADY signal toggled after each register data placed PDATA[15:0] order delimit when data valid bus. Using burst mode fetch statistics allows Processor Interface fetch statistics without having generate separate read accesses.
Instruction
Chapter Specifications
This chapter provides electrical mechanical specifications L64381. This chapter useful hardware engineers interconnecting L64381 with other devices designers designing printed circuit board. This chapter contains four sections:
Section 7.1, Timing" Section 7.2, "Electrical Requirements" Section 7.3, "Special Connections" Section 7.4, "Packaging"
Timing This section describes timing characteristics L64381 interface. During testing, HIGH inputs driven inputs driven transitions between HIGH, LOW, invalid states, timing measurements made shown Figure 7.1. test load, each output signal given Table 7.1.
Test Point
Figure Test Load Waveform Standard Outputs
Output
three-state outputs, timing measurements made from point which output turns OFF. output when voltage greater than less than output when voltage less than greater than shown Figure 7.2.
Figure Test Load Waveform 3-State Outputs
Test Point
Iref
Output
Vref Vref
Iref
timing relationships between signals depicted Figures through 7.9. figures depict:
Figure 7.3, "Bus Interface Read Write Timing" Figure 7.4, "Abort Operation Timing" Figure 7.5, "Reset Timing" Figure 7.6, "Processor Interface Timing" Figure 7.7, "Interrupt Timing" Figure 7.8, "Status Timing" Figure 7.9, "Clock Timing"
Table lists timing L64381. numbers Figures through correspond timing parameters listed column table. parameters valid specified ambient temperature range These parameters preliminary subject change.
Specifications
Table Timing Values Load Units (pF)
Parameter Description STROBE Setup CLOCK STROBE Hold from CLOCK PKT_AVAIL Delay from CLOCK READ_OUT_PKT Setup CLOCK READ_OUT_PKT Hold from CLOCK PORT_NO[1:0] Setup CLOCK PORT_NO[1:0] Hold from CLOCK DATA[31:0] Delay from CLOCK During Read DATA[31:0] 3-state from CLOCK BYTE_VALID[3:0] Delay from CLOCK During Read BYTE_VALID[3:0] 3-state from CLOCK During Read Delay from CLOCK During Read 3-state from CLOCK During Read Delay from CLOCK During Read 3-state from CLOCK During Read BUF_AVAIL Delay from CLOCK WRITE_IN_PKT Setup CLOCK WRITE_IN_PKT Hold from CLOCK DATA[31:0] Setup CLOCK During Write DATA[31:0] Hold from CLOCK During Write BYTE_VALID[3:0] Setup CLOCK During Write BYTE_VALID[3:0] Hold from CLOCK During Write Setup CLOCK During Write Hold from CLOCK During Write Setup CLOCK During Write Hold from CLOCK During Write ABORT_IN Setup CLOCK ABORT_IN Hold from CLOCK PORT_BUSY Delay from CLOCK
(Sheet
Timing
Table (Cont.) Timing Values Load Units (pF)
Parameter Description AI_FCS_IN Setup CLOCK AI_FCS_IN Hold from CLOCK ABORT_OUT Delay from CLOCK RESET Pulse Width ADRS_STROBE Setup CLOCK ADRS_STROBE Hold from CLOCK CHIP_SELECT Setup CLOCK CHIP_SELECT Hold CLOCK READ Setup CLOCK READ Hold from CLOCK ADRS[5:0] Setup CLOCK ADRS[5:0] Hold CLOCK PDATA[15:0] Setup CLOCK During Write PDATA[15:0] Hold from CLOCK During Write PREADY Delay from CLOCK PDATA[15:0] Delay from CLOCK During Read PDATA[15:0] 3-state from CLOCK During Read PREADY Asserted CHIP_SELECT Sampled Deasserted INTERRUPT Delay from CLOCK LEDSEL[1:0] Delay from CLOCK RCVNGN Delay from CLOCK TRNSMTN Delay from CLOCK COLLOUTN Delay from CLOCK LBADN Delay from CLOCK LPASSN Delay from CLOCK CLOCK Period CLOCK High/Low CLOCK_20MHZ Period CLOCK_20MHZ High/Low
62.5
(Sheet
Specifications
Figure Interface Read Write Timing
CLOCK STROBE PKT_AVAIL READ_OUT_PKT PORT_NO[1:0] DATA[31:0] BYTE_VALID[3:0] BUF_AVAIL
Port0 Port1 Port2 Port3 Port0 Port1 Port2 Port3
00002
WRITE_IN_PKT PORT_NO[1:0] DATA[31:0] BYTE_VALID[3:0] AI_FCS_IN PORT_BUSY
Port0 Port1 Port2 Port3
00002
MD95.134
Timing
Figure Abort Operation Timing
CLOCK
STROBE
PKT_AVAIL
PORT PORT
PKT_AVAIL
READ_OUT_PKT
WRITE_IN_PKT
PORT_NO[1:0]
DATA[31:0]
DATA
DATA
BYTE_VALID[3:0]
00002
11112
00002
ABORT_IN ABORT_OUT
MD95.135
Specifications
Figure Reset Timing
RESET
Figure Processor Interface Timing
CLOCK ADRS_STROBE CHIP_SELECT READ
ADRS[5:0]
Write Write DATA
Read Read DATA
PDATA[15:0]
PREADY
MD95.137
Figure Interrupt Timing
CLOCK
ERR_REG0/1 INTERRUPT
4000
MD195.139
Timing
Figure Status Timing
RESET
CLOCK LEDSEL[1:0] RCVNGN TRNSMTN COLLOUTN LBADN LPASSN
Figure Clock Timing
CLOCK
CLOCK_20MHZ
Electrical Requirements
This section specifies electrical requirements L64381. Five tables list electrical data following categories:
Absolute Maximum Ratings (Table 7.2) Recommended Operating Conditions (Table 7.3) Capacitance (Table 7.4) Characteristics (Table 7.5)
Specifications
Description Summary (Table 7.6)
Table Absolute Maximum Ratings Symbol Parameter TSTG Supply Input Voltage Input Current Storage Temperature Range, Plastic Limits1 -0.3 -0.3 +0.3 +125 Unit
Referenced VSS. Table Recommended Operating Conditions Symbol Parameter Supply, Commercial Case Temperature Limits +4.75 +5.25 Unit
thermal characteristics 208-pin Plastic Quad Flat Pack (PQFP) defined follows: °C/Watt 29.5 °C/Watt 25.8 °C/Watt 24.3 °C/Watt 23.0 °C/Watt junction-to-case junction-to-ambient Still lfpm lfpm lfpm
L64381 will operate from 65.29 (110 1.84 24.3 65.29) ambient temperature range, with flow Ifpm without heat sink. Also, junction temperature should exceed long-term reliability.
Electrical Requirements
Table Capacitance
Symbol COUT
Parameter1 Input Capacitance Output Capacitance
Unit
Capacitance
Measurement conditions clock frequency MHz. Output using single buffer structure (excluding package). Table Characteristics Symbol Parameter Voltage Input Voltage Input High Voltage Output High Max, Condition1 -117 Units
Voltage Output
IIPU IIPD IOSP4 IOSP8 IOSP24 IOSN4 IOSN8 IOSN24
Current Input Leakage Current Input Pull-up
Current 3-State Output Leakage Max, VOUT Current 3-State Output w/Pull-up Current P-Channel Output Short Max, VOUT Circuit Output Buffers)2 Current P-Channel Output Short Max, VOUT Circuit Output Buffers)2 Current P-Channel Output Short Max, VOUT Circuit Output Buffers)2 Current N-Channel Output Short Max, VOUT Circuit Output Buffers)2 Current N-Channel Output Short Max, VOUT Circuit Output Buffers)2 Current N-Channel Output Short Max, VOUT Circuit Output Buffers)2 Quiescent Supply Current Dynamic Supply Current Max,
-115 -214 -115 -222
-234 -150
-702 -450 -240
Specified equals over specified case temperature range. maximum power dissipation L64381 1.84
7-10
Specifications
more than output shorted time maximum duration second. Table Description Summary Mnemonic ABORT_IN ABORT_OUT ADRS[5:0] ADRS_STROBE AI_FCS_IN BUF_AVAIL BYTE_VALID[3:0] CHIP_SELECT CLOCK CLOCK_20MHZ COLLIN[3:0] COLLIP[3:0] COLLOUTN CREF[3:0] DATA[31:0] DATAI[3:0] DATAN[3:0] DATAP[3:0] DATATN[3:0] DATATP[3:0] DREF[3:0] INTERRUPT LBADN LEDSEL[1:0] LPASSN PDATA[15:0] PKT_AVAIL PLLAGND PLLVDD PLLVSS PORT_BUSY PORT_NO[1:0] (Sheet Description Abort Abort Register Select Address Address Strobe Auto-Insert Buffer Available Valid Bytes Chip Select System Clock Internal Clock Negative Collision Threshold Positive Collision Threshold Collision Collision Reference L64381 Data Serial Data Negative Manchester-Encoded Data Positive Manchester-Encoded Data Data Threshold Negative Data Threshold Positive Data Threshold Reference Packet Interrupt Link Inverted Select Phase Detector Link Test Status Processor Data Packet Available Analog Ground Power Digital Ground Port Status Port Number Type Input Output Input Input Input Output Bidirectional Input Input Input CMOS Input CMOS Input Output Input Bidirectional CMOS Input Output Output CMOS Input CMOS Input Input Bidirectional Output Output Output Output Input Output Bidirectional Output Output Input Input Output Input, Drive (mA) Active
Electrical Requirements
7-11
Table (Cont.) Description Summary Mnemonic PREADY PREEN[3:0] PREEP[3:0] P_TESTN RCVNGN READ READ_OUT_PKT RESET STROBE TP/AUI[3:0] TRNSMTN TRSTN WRITE_IN_PKT (Sheet Description Ready Negative Pre-emphasis Positive Pre-emphasis Global 3-State Receiver Status Read Read Data from Receive FIFO Reset Start Packet Strobe JTAG Test Clock JTAG Test Data JTAG Test Data JTAG Test Mode Select Twisted-Pair/AUI Select Transmitter Status JTAG Test Reset Write Data Transmit FIFO Type Output Output Output CMOS Input, Output Input Input Input Bidirectional Input Input Input, Output Input, Input Output Input, Input Drive (mA) Active
Special Connections
minimize digital noise coupling, L64381 provides separate power ground each port. output buffers driving DATAP[3:0], DATAN[3:0], PREEP[3:0], PREEN[3:0] pins each port have their pins, thus decoupled from pins remaining chip output buffers. Table lists pins each port.
Port Number Number Number
Table VDD/VSS Numbers Port
7-12
Specifications
Packaging 7.4.1 Ordering Information
Table L64381 Ordering Information
L64381 available 208-pin Plastic Quad Flat Pack (PQFP) package. Table lists L64381 according order number package type.
Order Number L64381
Clock Frequency (MHz)
Package Type 208-pin PQFP
Operating Range Commercial
7.4.2 Package Information
This subsection provides three types information each package type: alphabetical list (Table 7.9), pinout (Figure 7.10), mechanical drawing (Figure 7.11).
Packaging
7-13
Table Alphabetical List 208-Pin PQFP
7-14
Specifications
Signal
ABORT_IN ABORT_OUT ADRS0 ADRS1 ADRS2 ADRS3 ADRS4 ADRS5 ADRS_STROBE AI_FCS_IN BUF_AVAIL BYTE_VALID0 BYTE_VALID1 BYTE_VALID2 BYTE_VALID3 CHIP_SELECT CLOCK CLOCK_20MHZ COLLIN0 COLLIN1 COLLIN2 COLLIN3 COLLIP0 COLLIP1 COLLIP2 COLLIP3 COLLOUTN CREF0 CREF1 CREF2 CREF3 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 DATA16 DATA17 DATA18 DATA19 DATA20
Signal
DATA21 DATA22 DATA23 DATA24 DATA25 DATA26 DATA27 DATA28 DATA29 DATA30 DATA31 DATAI0 DATAI1 DATAI2 DATAI3 DATAN0 DATAN1 DATAN2 DATAN3 DATAP0 DATAP1 DATAP2 DATAP3 DATATN0 DATATN1 DATATN2 DATATN3 DATATP0 DATATP1 DATATP2 DATATP3 DREF0 DREF1 DREF2 DREF3 INTERRUPT LBADN LEDSEL0 LEDSEL1 LPASSN PDATA0 PDATA1 PDATA2 PDATA3 PDATA4 PDATA5 PDATA6 PDATA7 PDATA8
Signal
PDATA9 PDATA10 PDATA11 PDATA12 PDATA13 PDATA14 PDATA15 PKT_AVAIL PLLAGND PLLVDD PLLVSS PORT_BUSY PORT_NO0 PORT_NO1 PREADY PREEN0 PREEN1 PREEN2 PREEN3 PREEP0 PREEP1 PREEP2 PREEP3 P_TEST RCVNGN READ READ_OUT_PKT RESET STROBE TP/AUI0 TP/AUI1 TP/AUI2 TP/AUI3 TRNSMTN TRSTN WRITE_IN_PKT
Signal
VDD3 VDD2 VDD1 VDD0 VSS3 VSS2 VSS1 VSS0
Packaging
7-15
Figure 7.10 208-Pin PQFP Pinout
PDATA0 PDATA1 PDATA2 PDATA3 PDATA4 PDATA5 PDATA6 PDATA7 PDATA8 PDATA9 PDATA10 PDATA11 PDATA12 PDATA13 PDATA14 PDATA15 ADRS_STROBE CLOCK AI_FCS_IN COLLOUTN CHIP_SELECT BYTE_VALID3 BYTE_VALID2 BYTE_VALID1 BYTE_VALID0 BUF_AVAIL CLOCK_20MHZ PLLVDD PLLVSS PLLAGND DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 DATA16 DATA17 DATA18 DATA19 DATA20 DATA21 DATA22 DATA23 DATA24 DATA25 DATA26 DATA27 DATA28 DATA29 DATA30 DATA31 ADRS0 ADRS1
View
P_TESTN TRSTN DATATN0 DATATP0 DREF0 TP/AUI0 DATAI0 DATAP0 DATAN0 PREEP0 PREEN0 VSS02 VDD02 COLLIN0 COLLIP0 CREF0 DATATN1 DATATP1 DREF1 TP/AUI1 DATAI1 DATAP1 DATAN1 PREEP1 PREEN1 COLLIN1 COLLIP1 CREF1 DATATN2 VDD13 VSS13 DATATP2 DREF2 TP/AUI2 DATAI2 DATAP2 DATAN2 PREEP2 PREEN2 COLLIN2 COLLIP2 VSS24 VDD24 95.L64380.UP
pins connected. decoupled separate power ground Port decoupled separate power ground Port decoupled separate power ground Port decoupled separate power ground Port
7-16
ADRS2 ADRS3 ADRS4 ADRS5 RESET READ_OUT_PKT STROBE TRNSMTN WRITE_IN_PKT READ ABORT_IN ABORT_OUT RCVNGN PORT_NO0 PORT_NO1 PREADY INTERRUPT PORT_BUSY PKT_AVAIL LPASSN LEDSEL1 LEDSEL0 LBADN PREEN3 PREEP3 DATAN3 DATAP3 DATAI3 TP/AUI3 DREF3 DATATP3 DATATN3 CREF3 COLLIP3 COLLIN3 CREF2 VDD35 VSS35
Specifications
Figure 7.11 208-Pin PQFP Mechanical Drawing
Pins Detail
Dimension
4.10 0.25 3.20 3.40 3.60 0.17 0.23 0.27 0.13 0.16 0.20 30.40 30.60 30.80 27.90 28.00 28.10 0.50 30.40 30.60 30.80 27.90 28.00 28.10 0.45 0.60 0.75
Detail
Detail Sides Even Lead Sides
Total number pins 208. Controlling dimension millimeter. Drawing scale. Datum plane located mold parting line coincident with bottom leads, where lead exits plastic body. Datums determined datum plane determined seating plane Dimensions include mold protrusion. Allowable protrusion 0.25 side. These dimensions include mold mismatch determined Details identifier optional must located within zone indicated. Dimension does include dambar protrusion. Allowable dambar protrusion shall 0.08 total excess dimension maximum material condition. Dambar cannot located lower radius foot. Minimum spacing between adjacent leads 0.07 board layout manufacturing, obtain engineering drawings from your Logic marketing representative requesting outline drawing package code
MD92.UPe
Packaging
7-17
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