GANGES Supports full duplex mapping Acells packets single STS-192

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GANGES Supports full duplex mapping Acells packets single STS-192

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Part Number S19202 Revision June 2000
GANGES
Supports full duplex mapping Acells packets single STS-192c/AU-4-64c, four STS-48c/AU-416c sixteen STS-12c/AU-4-4c SONET/SDH payloads. Supports quad STS-48/STM-16 line interfaces. Each STS-48/STM-16 support concatenated payload, channelized down STS-12c/AU-4-4c. Terminates generates SONET/SDH section, line, path layers, with transport/section overhead interfaces both transmit receive directions. Provides 622.08 16-bit interface line side both directions. Provides 64-bit, system interface that supports transfer either packets Acells. Selectable scrambling/descrambling (1+X6+X7) SONET/SDH frame. 16-bit synchronous microprocessor interface configuration, control, status monitoring. Supports independent loop timing when quad STS48/STM-16 mode. Supports Automatic Protection Switching (APS) Packaged 624-pin CBGA. Implemented micron, 1.8V 2.5V technology.
ADVANCED SUMMARY DATASHEET
STS-192 POS/ASONET/SDH MAPPER
General Description
GANGES highly-integrated VLSI device that provides full-duplex mapping packets Acells into SONET/SDH payloads. GANGES provides full section line overhead processing either single STS-192/STM-64, four STS48/STM-16s. supports framing, scrambling descrambling, alarm signal insertion detection, interleaved parity (B1/B2) processing. also provides path overhead processing STS-192c/AU-4-64c, STS48c/AU-4-16c STS-12c/AU-4-4c SONET/SDH payloads includes interleaved parity (B3) processing. GANGES includes automatic protection switching (APS) port, that permits protection switching between GANGES devices. S19202 SONET/SDH standards compliant with Bellcore GR-253, G.707, ANSI T1.105 -1995. general purpose 16-bit microprocessor interface provided control, monitoring.
Applications
Aswitches Packet over SONET Routers SONET/SDH Drop Multiplexers, Terminal Multiplexers Digital Cross Connects DWDM
S19202 Block Diagram
PROT_DATA_OUT[1:4][3:0] TX_TOH_DATA_IN[1:4] TX_TOH_FRM_OUT[1:4] TX_TOH_CLK_OUT[1:4] PROT_CLK _OUT[1:4]
LINE SIDE INTERFACE
INSERT FRGEN FRTX FRAM
FRMR
RDYB(DTACKB) BUSMODE APS_INTB UPCLK
RSTB INTB D[15:0] ADDR[12:0] WRB(RWB)
GPIO[15:0]
MICROPROCESSOR SPE/VC GENERATOR GENERATION ATM/ HDLC Proc
SYSTEM INTRFC/ ATM/POS FIFO
Control STX_DATA_IN[63:0]
TX_CLK_OUT[1:4] TX_DATA_OUT[15:0]
RX_DATA_IN[15:0] RX_CLK_IN_[1:4]
MON. SYS_REFCLK_IN SYS_ASYNC_FRM_IN SYS_REFCLK_OUT PROT_CLK_IN [1:4] POINTER INTERPRETER
MONITOR JTAG ATM/ HDLC Proc SYSTEM INTRFC/ ATM/POS FIFO SRX_DATA_OUT[63:0] Control
EXTRACT
TRSTB TS_EN
RX_ALM_OUT_[1:4] RX_LOSEXT_[1:4] RX_REFCLK_IN[1:4]
RX_TOH_CLK_OUTI1:4] RX_TOH_DATA_OUT[1:4] RX_TOH_FRM_OUT1:4]
PROT_DATA_IN[1:4][3:0]
AMCC
Advanced Information information contained this document about product design phase subject change without notice time. features described herein design goals. Contact AMCC updates this document latest product status.
Revision June 2000
S19202 STS-192 POS/ASONET/SDH MAPPER
ADVANCED PRODUCT SPECIFICATION
Overview Applications
SONET Processing
S19202 supports either single STS-192/STM-64, four STS-48/STM-16 SONET/SDH Line interfaces. provides full duplex mapping Acells packets STS-192c/AU-4-64c, STS-48c/AU-4-16c, and/or STS12c/AU-4-4c SONET/SDH payloads. TOH/SOH interface provides direct add/drop capability both Section Line channels. S19202 also includes clear channel mode that enables direct transmission system payload from system interface line-side interface. Side door interfaces supported both directions. transmit side S19202 generates section, line, path overhead. performs framing pattern insertion (A1, A2), scrambling, alarm signal insertion, generates section, line path Interleaved Parity (B1/B2/ far-end performance monitoring. receive side S19202 processes section, line, path overhead. performs framing (A1, A2), descrambling, alarm detection, pointer interpretation, interleaved parity monitoring (B1/B2/B3), error count accumulation performance monitoring.
AProcessing
When configured Acell processing, S19202's Aprocessor(s) will perform necessary cell processing defined AUNI3.1 ITU-T I.432.1 I.432.2.
HDLC Processing
When configured mode, S19202's HDLC processor(s) provide insertion HDLC framed packets into SPE(s)/SVC(s). S19202 performs HDLC processing defined IETF RFCs 1661, 1662 2615.
Line-side Interface
line-side, S19202 supports 16-bit parallel interface, operating 622MHz, single OC-192 optical interface. quad STS-48/STM-16 operation, S19202 supports four 4-bit, MHz, line interfaces. (See figure below.)
System Interface
GANGES provides 64-bit, MHz, system interface transport either packets Acells.
TYPICAL APPLICATIONS: GANGES STS-192/AU-4-64 channelized System
Microprocessor Control Control Addr Reference Clock System Control SIgnals SONET Line Side Interface OC-192 Line Interface SONET XMIT SerRxD± SONET RCVR with Recovery SerTxD± TX_SONETCLK TX_DATA[15:0] RX_LOS_[1] RX_SONETCLK_[1] RX_DATA[15:0] STX_DATA_IN[63:0] SAR/LINK LAYER DEVICE Data
Fiber Optic Transceiver
GANGES S19202
SRX_DATA_OUT[63:0]
AMCC S3091/S3092
Insertion Extraction
AMCC Brickstone Square, Andover, 01810 (978) 623-0009 Fax:(978) 623-0024

GANGES Supports full duplex mapping Acells packets single STS-192

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